CN219123222U

CN219123222U - Chip packaging structure

Info

Publication number: CN219123222U
Application number: CN202223584154.9U
Authority: CN
Inventors: 王兆攀
Original assignee: Hunan Yuemo Advanced Semiconductor Co ltd
Current assignee: Hunan Yuemo Advanced Semiconductor Co ltd
Priority date: 2022-12-30
Filing date: 2022-12-30
Publication date: 2023-06-02
Anticipated expiration: 2032-12-30

Abstract

The utility model relates to the technical field of chip packaging, and particularly discloses a chip packaging structure. The device comprises a chip, a substrate and a plastic package body; the upper plate surface of the chip is provided with a SENSOR layer; the two ends of the upper plate surface of the substrate are respectively provided with a device area and a chip area, the lower plate surface of the chip is fixedly connected in the chip area, the chip is connected with the substrate through a lead wire in an electric signal manner, an electronic device is arranged in the device area, the lower plate surface of the substrate is provided with a connecting area corresponding to the device area, and the connecting area is connected with the PCB electric signal; the plastic package body covers the side wall of the SENSOR layer, the lead and the upper plate surface of the substrate. The device improves the layout of the chip packaging structure, improves the heat dissipation performance of the product and simplifies the structure of the product by optimally designing the layout positions of the chips and the electronic devices on the substrate.

Description

Chip packaging structure

Technical Field

The present utility model relates to the field of chip packaging technologies, and in particular, to a chip packaging structure.

Background

As shown in fig. 1, the conventional chip packaging technology is a COB (chip on Board) technology, that is, a chip 100' is directly adhered to a PCB (Printed Circuit Board ) 300' by a bonding adhesive 200', then an electrical signal of the chip 100' is transferred to the PCB300' by means of bonding a lead 400', and then a circle of protective adhesive 500' is applied to a bonding area of the lead 400' to protect the lead 400', and meanwhile, a mounting groove 301' is formed at the bottom of the central position of a contact area of the chip 100' on the PCB300', so as to connect a heat conducting pad 600' with the PCB300' by means of mounting the heat conducting pad in the mounting groove 301', thereby improving heat dissipation performance and enabling a gene detection sample to flow through a SENSOR layer 110' on the chip 100', so as to achieve the detection purpose.

However, since the PCB300 'is thick, heat generated during operation of the chip 100' needs to pass through the thicker PCB300 'to reach the heat conducting pad 600', and the electronic device 700 'is arranged around the chip 100', which increases the heat dissipation distance and reduces the heat dissipation performance of the product.

Disclosure of Invention

The utility model aims to provide a chip packaging structure so as to improve the heat dissipation performance of a product and simplify the structure of the product.

To achieve the purpose, the utility model adopts the following technical scheme:

the chip packaging structure comprises a chip, a substrate and a plastic package body; the upper plate surface of the chip is provided with a SENSOR layer; the device comprises a substrate, a chip area, a connecting area, a lead wire, an electronic device, a PCB (printed circuit board) and a circuit board, wherein the two ends of the upper surface of the substrate are respectively provided with the device area and the chip area, the lower surface of the chip is fixedly connected in the chip area, the chip is connected with the substrate through the lead wire through the electric signal, the electronic device is arranged in the device area, the lower surface of the substrate is provided with the connecting area corresponding to the device area, and the connecting area is connected with the PCB through the electric signal; the plastic package body wraps the side wall of the SENSOR layer, the lead and the upper plate surface of the substrate.

As the preferable technical scheme of the chip packaging structure, the chip packaging structure further comprises a heat conduction cushion block which is contacted with the chip, and the heat conduction cushion block is used for radiating the chip.

As a preferable technical scheme of the chip packaging structure, the substrate is penetrated with a window hole, the projection of the window hole on the upper surface of the substrate is positioned in the chip area, and the heat conducting cushion block is inserted into the window hole from the lower part.

As a preferable embodiment of the chip packaging structure, the projection of the chip on the upper surface of the substrate covers the projection of the window hole on the upper surface of the substrate.

As the preferable technical scheme of the chip packaging structure, the heat conducting cushion block is a T-shaped piece, and the vertical end part of the T-shaped piece is inserted into the window hole.

As a preferable technical scheme of the chip packaging structure, two ends of the lead are respectively connected to the upper plate surface of the chip and the upper plate surface of the substrate.

As the preferable technical scheme of the chip packaging structure, the top surface of the plastic packaging body is flush with the upper surface of the SENSOR layer.

As the preferable technical scheme of the chip packaging structure, bonding glue is clamped between the lower plate surface of the chip and the upper plate surface of the substrate, and the substrate is fixedly connected with the chip through the bonding glue.

As a preferable technical scheme of the chip packaging structure, the bonding glue is DA glue.

As the preferable technical scheme of the chip packaging structure, the connecting area is fixedly connected with a plurality of spheres, and the substrate is connected with the PCB through the spheres.

The utility model has the beneficial effects that:

the chip packaging structure determines the mounting positions of the chip and the electronic device by distinguishing the device area from the chip area, completes the scattered arrangement of the heating sources, and realizes the optimization of the layout on the substrate. Through the design of the connection area corresponding to the device area and the PCB electric signal connection, the heat dissipation efficiency of the device area and the connection area is improved, the packaging distance is shortened, and meanwhile, the connection between the substrate and the PCB is realized, so that the structural flexibility of the chip packaging structure is improved in a split setting mode, and the heat dissipation effect is improved. The arrangement of the plastic package body not only plays a role in protecting the chip and the leads, but also is beneficial to improving the heat dissipation effect of the chip and the substrate, and the design of the side wall of the cladding SENSOR layer exposes the upper surface of the SENSOR layer so that the SENSOR layer can run smoothly. The structural improvement improves the layout of the chip packaging structure, improves the heat dissipation performance of the product, and simplifies the structure of the product.

Drawings

FIG. 1 is a cross-sectional view of a conventional chip package structure;

FIG. 2 is a cross-sectional view of a chip package structure according to an embodiment of the present utility model;

FIG. 3 is a top view of a substrate provided by an embodiment of the present utility model;

FIG. 4 is a cross-sectional view of a chip, substrate and electronic device provided by an embodiment of the utility model;

FIG. 5 is a cross-sectional view of a chip, substrate, leads and electronic device provided by an embodiment of the utility model;

FIG. 6 is a cross-sectional view of a chip, substrate, leads, plastic package, and electronic device provided by an embodiment of the present utility model;

fig. 7 is a cross-sectional view of a chip, a substrate, a lead, a molding, a ball, and an electronic device according to an embodiment of the present utility model.

In fig. 1:

100', chip; 110', SENSOR layers; 200', bonding glue; 300', PCB;301', a cartridge slot; 400', lead wires; 500', protective glue; 600', heat conducting pads; 700', electronic device.

Fig. 2-7:

100. a chip; 110. a SENSOR layer; 200. bonding glue; 300. a substrate; 301. a window hole; 400. a lead wire; 500. a plastic package body; 600. a thermally conductive pad; 700. an electronic device; 800. a sphere; 900. and a PCB.

Detailed Description

The following description of the embodiments of the present utility model will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the utility model are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

In the description of the present utility model, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Wherein the terms "first location" and "second location" are two distinct locations and wherein the first feature is "above," "over" and "over" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is level above the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.

In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.

Embodiments of the present utility model are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the utility model.

As shown in fig. 2-7, the present embodiment provides a chip package structure, including a chip 100, a substrate 300, and a plastic package 500; the upper plate surface of the chip 100 is provided with a SENSOR layer 110; the two ends of the upper plate surface of the substrate 300 are respectively provided with a device area and a chip area, the lower plate surface of the chip 100 is fixedly connected in the chip area, the chip 100 is connected with the substrate 300 through a lead 400 in an electric signal manner, an electronic device 700 is arranged in the device area, the lower plate surface of the substrate 300 is provided with a connecting area corresponding to the device area, and the connecting area is connected with the PCB900 in an electric signal manner; the molding compound 500 encapsulates the sidewalls of the SENSOR layer 110, the leads 400, and the upper surface of the substrate 300.

The chip packaging structure determines the mounting positions of the chip 100 and the electronic device 700 by distinguishing the device area from the chip area, completes the scattered arrangement of the heating sources, and realizes the optimization of the layout on the substrate 300. Through the design of the connection between the connection area corresponding to the device area and the PCB900 electric signal, the heat dissipation efficiency of the device area and the connection area is improved, the packaging distance is shortened, and meanwhile, the connection between the substrate 300 and the PCB900 is realized, so that the structural flexibility of the chip packaging structure is improved in a split arrangement mode, and the heat dissipation effect is improved. The arrangement of the plastic package 500 not only protects the chip 100 and the leads 400, but also helps to improve the heat dissipation effect of the chip 100 and the substrate 300, and the design of the side wall of the cladding SENSOR layer 110 exposes the upper surface of the SENSOR layer 110, so that the SENSOR layer 110 can run smoothly. The structural improvement improves the layout of the chip packaging structure, improves the heat dissipation performance of the product, and simplifies the structure of the product.

In this embodiment, the chip package structure is applied to gene detection, and the SENSOR layer 110 is used for carrying and detecting a gene detection sample flowing through the upper surface of the SENSOR layer 110; the electronic device 700 is an electronic component such as an electronic capacitor.

In this embodiment, the chip package structure further includes a heat conducting pad 600 in contact with the chip 100, where the heat conducting pad 600 is used for dissipating heat from the chip 100. The heat-conducting cushion block 600 greatly improves the heat dissipation efficiency of the chip 100, and reduces the risk of chip 100 failure, thereby ensuring the smooth operation of the chip packaging structure and prolonging the service life.

Further, the substrate 300 is penetrated with a window 301, the projection of the window 301 on the upper surface of the substrate 300 is located in the chip area, and the heat conducting pad 600 is inserted into the window 301 from the lower part. The plugging mode is simple and reliable, the occupied space is small, the connection is stable, and the processing difficulty is low; the design of plugging the heat conducting cushion block 600 on the substrate 300 optimizes the layout of the chip packaging structure, effectively reduces the risk of damage to the PCB900 due to overhigh temperature, and further prolongs the service life of the chip packaging structure.

Still further, the projection of the chip 100 onto the upper surface of the substrate 300 covers the projection of the window 301 onto the upper surface of the substrate 300. The above design avoids the situation that the chip 100 cannot be in direct contact with the substrate 300, ensures the connection stability of the chip 100 on the substrate 300, ensures that the heat conduction cushion block 600 can achieve the purpose of radiating the chip 100, ensures the structural strength of the chip packaging structure, and further reduces the risk of damage.

Illustratively, the thermally conductive pad 600 is a T-shaped member with a vertical end portion that is inserted into the aperture 301.

In this embodiment, both ends of the lead 400 are connected to the upper surface of the chip 100 and the upper surface of the substrate 300, respectively. The design reduces the setting difficulty of the lead 400, reduces the risk of damage to the lead 400, ensures the electric signal connection effect between the chip 100 and the substrate 300, and ensures the smooth operation of the chip packaging structure.

Illustratively, the top surface of the plastic package 500 is flush with the upper surface of the SENSOR layer 110. The design ensures that the outer surface of the plastic package body 500 is regular in shape, so that the problems in the subsequent operation are reduced; meanwhile, the design ensures that the plastic package body 500 can be smoothly exposed on the upper surface of the SENSOR layer 110, and ensures that the chip packaging structure can smoothly run.

In the present embodiment, a bonding adhesive 200 is sandwiched between the lower surface of the chip 100 and the upper surface of the substrate 300, and the substrate 300 is fixedly connected to the chip 100 through the bonding adhesive 200. The connecting mode is simple and reliable, the structure is compact, the connection is stable, the risk of damage to the chip packaging structure is reduced, and the service life is prolonged.

Specifically, the bonding adhesive 200 is a DA (Die Attach) adhesive.

In this embodiment, a plurality of balls 800 are fixedly connected to the connection region, and the substrate 300 is connected to the PCB900 through the balls 800. The sphere 800 has simple and reliable structure, small occupied space and high connection stability, not only can realize smooth transmission of electric signals between the substrate 300 and the PCB900, but also fixes the relative positions of the substrate 300 and the PCB900, reduces the risk of relative position deviation between the substrate 300 and the PCB900 caused by accidents, is beneficial to improving the stability of transmission of the electric signals between the substrate 300 and the PCB900, and prolongs the service life of the chip packaging structure.

The embodiment also provides a chip packaging structure processing method, which is applied to the chip packaging structure and comprises the following steps: determining the positions of a chip area, a device area and a connection area on the substrate 300, and processing window holes 301 in the chip area; mounting the electronic device 700 on the device region, dispensing DA glue on the chip region, and then mounting the chip 100 on the chip region through the DA glue; wire bonding the leads 400 from above the chip 100 to the upper surface of the substrate 300 by means of wire bonding 400; performing open molding and plastic packaging on the substrate 300 from above; ball 800 is planted in the connection area, so that the substrate 300 is connected with the PCB900 through solder ball welding; the heat conductive pad 600 is inserted into the window 301 from below the substrate 300.

It is to be understood that the above examples of the present utility model are provided for clarity of illustration only and are not limiting of the embodiments of the present utility model. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the utility model are desired to be protected by the following claims.

Claims

1. Chip packaging structure, its characterized in that includes:

a SENSOR layer (110) is arranged on the upper plate surface of the chip (100);

the device comprises a substrate (300), wherein device areas and chip areas are respectively arranged at two ends of an upper plate surface of the substrate (300), a lower plate surface of the chip (100) is fixedly connected in the chip areas, the chip (100) is connected with the substrate (300) through leads (400) in an electric signal mode, an electronic device (700) is arranged in the device areas, a connecting area corresponding to the device areas is arranged on the lower plate surface of the substrate (300), and the connecting area is connected with a PCB (900) in an electric signal mode;

and a plastic package (500) which covers the side wall of the SENSOR layer (110), the lead (400) and the upper plate surface of the substrate (300).

2. The chip package structure according to claim 1, further comprising a thermally conductive pad (600) in contact with the chip (100), the thermally conductive pad (600) being configured to dissipate heat from the chip (100).

3. The chip package structure according to claim 2, wherein the substrate (300) has a window (301) penetrating therethrough, a projection of the window (301) on an upper surface of the substrate (300) is located in the chip area, and the heat conductive pad (600) is inserted into the window (301) from a lower portion.

4. A chip package structure according to claim 3, wherein the projection of the chip (100) onto the upper surface of the substrate (300) covers the projection of the window (301) onto the upper surface of the substrate (300).

5. A chip package according to claim 3, wherein the heat conducting pad (600) is a T-shaped member, and a vertical end portion of the T-shaped member is inserted into the window hole (301).

6. The chip package structure according to claim 1, wherein both ends of the lead (400) are connected to an upper surface of the chip (100) and an upper surface of the substrate (300), respectively.

7. The chip packaging structure according to claim 1, wherein a top surface of the plastic package body (500) is flush with an upper surface of the SENSOR layer (110).

8. The chip packaging structure according to claim 1, wherein a bonding adhesive (200) is interposed between a lower surface of the chip (100) and an upper surface of the substrate (300), and the substrate (300) is fixedly connected to the chip (100) through the bonding adhesive (200).

9. The chip package structure according to claim 8, wherein the bonding adhesive (200) is a DA adhesive.

10. The chip packaging structure according to any one of claims 1-9, wherein the connection area is fixedly connected with a plurality of balls (800), and the substrate (300) is connected with the PCB (900) through the balls (800).