CN219107301U - Source-load integrated circuit, device and equipment - Google Patents

Source-load integrated circuit, device and equipment Download PDF

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Publication number
CN219107301U
CN219107301U CN202222936263.6U CN202222936263U CN219107301U CN 219107301 U CN219107301 U CN 219107301U CN 202222936263 U CN202222936263 U CN 202222936263U CN 219107301 U CN219107301 U CN 219107301U
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mos tube
driving module
module
microprocessor
amplifier
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石利军
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Shenzhen Kesai Electronics Co ltd
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Shenzhen Kesai Electronics Co ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The embodiment of the application provides a source-carried integrated circuit, a device and equipment, wherein the circuit comprises: the multifunctional test device comprises a first power supply, a second power supply, a first capacitor, a second capacitor, a third capacitor, a first driving module, a second driving module, a third driving module, a fourth driving module, a fifth driving module, a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a transformer, a first resistor, a second resistor, a first inductor, a first amplifier, a second amplifier, a reference voltage module, a switch module and a microprocessor, wherein the multifunctional test of the tested device can be realized through the modules of double power supply functions in the source-load integrated circuit, and the convenience of the device in use is improved.

Description

Source-load integrated circuit, device and equipment
Technical Field
The application relates to the technical field of circuit structures, in particular to a source-load integrated circuit, a device and equipment.
Background
When the conventional burn-in test of equipment, power supply and the like is performed, the test equipment is usually powered by a common power supply to perform the burn-in test and the like on the equipment, that is, the common power supply can only be used for power supply, so that other tests on the tested equipment cannot be performed, for example, the charge-discharge cycle test and the like are performed, and the convenience of the test equipment in use is low.
Disclosure of Invention
The embodiment of the application provides a source-load integrated circuit, a device and equipment, which can realize the multifunctional test of tested equipment through a module with double power supply functions in the source-load integrated circuit, and improve the convenience of the equipment in use.
A first aspect of embodiments of the present application provides a source-loaded integrated circuit, the circuit comprising: the first power supply, the second power supply, the first capacitor, the second capacitor, the third capacitor, the first driving module, the second driving module, the third driving module, the fourth driving module, the fifth driving module, the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the transformer, the first resistor, the second resistor, the first inductor, the first amplifier, the second amplifier, the reference voltage module, the switch module and the microprocessor,
the first end of the first power supply is connected with the first end of the first capacitor, the first end of the first MOS tube, the first end of the second MOS tube and the first end of the microprocessor,
the second end of the first power supply is connected with the second end of the second capacitor, the second end of the third MOS tube and the second end of the fourth MOS tube, the second end of the first capacitor is connected with the first end of the second capacitor and the first end of the transformer,
the second end of the first MOS tube is connected with the first end of the third MOS tube and the second end of the transformer,
the third end of the first MOS tube is connected with the first end of the first driving module, the second end of the first driving module is connected with the third end of the third MOS tube, the third end of the first driving module is connected with the second end of the microprocessor,
the second end of the second MOS tube is connected with the third end of the transformer and the first end of the fourth MOS tube, the third end of the second MOS tube is connected with the first end of the second driving module,
the second end of the second driving module is connected with the third end of the fourth MOS tube, the third end of the second driving module is connected with the third end of the microprocessor,
the fourth end of the transformer is connected with the second end of the fifth MOS tube and the first end of the seventh MOS tube, the fifth end of the transformer is connected with the second end of the sixth MOS tube and the first end of the eighth MOS tube,
the first end of the fifth MOS tube is connected with the first end of the sixth MOS tube, the first end of the third capacitor and the first end of the first inductor, the third end of the fifth MOS tube is connected with the first end of the third driving module,
the second end of the third driving module is connected with the third end of the seventh MOS tube, the third driving module obtains the third end to be connected with the fourth end of the microprocessor,
the third end of the sixth MOS tube is connected with the first end of the fourth driving module, the second end of the fourth driving module is connected with the third end of the eighth MOS tube, the third port of the fourth driving module is connected with the fifth port of the microprocessor,
the second end of the third capacitor is connected with the first end of the ninth MOS tube, the third end of the ninth MOS tube is connected with the fifth driving module, the second end of the ninth MOS tube is connected with the first end of the second resistor, the second end of the seventh MOS tube, the second end of the eighth MOS tube and the first end of the second amplifier,
the second end of the first inductor is connected with the first end of the second resistor and the first end of the second amplifier, the second end of the first resistor is connected with the first end of the second power supply and the second end of the second amplifier, the third end of the second amplifier is a signal output port,
the second end of the second power supply is connected with the second end of the first resistor and the second end of the first amplifier and grounded, the third end of the first amplifier is connected with the sixth end of the microprocessor, the fourth end of the first amplifier is connected with the reference voltage module,
the seventh port of the microprocessor is connected with the switch module.
In the example, the source-load integrated circuit formed by the circuit, the first power supply module and the second power supply module can be used for realizing the multifunctional test of the tested equipment, so that the convenience of the equipment in use is improved.
In one possible implementation, the circuit further includes a third amplifier disposed between the first end of the first capacitor and the first end of the microprocessor, at least for connecting the first end of the first capacitor and the first end of the microprocessor.
In one possible implementation, the circuit further includes a fourth amplifier disposed between the second end of the third amplifier and the first end of the microprocessor, at least for connecting the second end of the third amplifier and the first end of the microprocessor.
In one possible implementation, the eighth port of the microprocessor is connected to the first transceiver module, the ninth port of the microprocessor is connected to the I2C isolator, and the tenth port of the microprocessor is connected to the second transceiver module.
In one possible implementation, the circuit further includes a grid-tie inverter connected to the second power source.
In one possible implementation, the circuit further includes a first load module, the first load module including a power source under test, a battery pack, and a DC/DC module, the load module being connected to the first power source.
In one possible implementation, the circuit further includes a dc power source, the dc power source being connected to the second power source.
In one possible implementation, the circuit further includes a second load module, the second load module including a battery pack, the second load module being connected to the first power supply, the first power supply being configured to charge the load module.
A second aspect of an embodiment of the present application provides an on-board device comprising a circuit board and a bi-directional power supply circuit as set forth in any one of the first aspects.
A third aspect of embodiments of the present application provides a source-carried integrated apparatus comprising a housing and a source-carried integrated device as described in the second aspect.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a source-load integrated circuit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another source-load integrated circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another source-load integrated circuit according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another source-load integrated circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of another source-carrier integrated circuit according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.
In order to better understand the source-carrier integrated device and the like provided in the embodiments of the present application, a brief description of the source-carrier integrated device is provided below. The source-load integrated equipment is a product based on the combination of a bidirectional power supply technology and a feedback type load technology, and can be used as a programmable power supply for providing power to the outside and also can be used as an energy-saving load for performing aging test. Because the energy can be transmitted in two directions, the power supply mode and the load mode can be switched at will, namely, each channel of the module can be independently set to be the power supply mode or the load mode, so that different testing tasks are realized, and the convenience of the equipment in use is improved.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a source-load integrated circuit according to an embodiment of the present application. As shown in fig. 1, the circuit includes: a first power supply 1, a second power supply 7, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first driving module 2, a second driving module 3, a third driving module 4, a fourth driving module 5, a fifth driving module 6, a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a fifth MOS transistor Q5, a sixth MOS transistor Q6, a seventh MOS transistor Q7, an eighth MOS transistor Q8, a ninth MOS transistor Q9, a transformer 8, a first resistor R1, a second resistor R2, a first inductor L1, a first amplifier 9, a second amplifier 10, a reference voltage module 11, a switch module 12 and a microprocessor 13, wherein,
the first end of the first power supply is connected with the first end of the first capacitor C1, the first end of the first MOS tube Q1, the first end of the second MOS tube Q2 and the first end of the microprocessor 13,
the second end of the first power supply 1 is connected with the second end of the second capacitor C2, the second end of the third MOS transistor Q3 and the second end of the fourth MOS transistor Q4, the second end of the first capacitor C1 is connected with the first end of the second capacitor C2 and the first end of the transformer 8,
the second end of the first MOS transistor Q1 is connected with the first end of the third MOS transistor Q3 and the second end of the transformer 8,
the third end of the first MOS transistor Q1 is connected with the first end of the first driving module 2, the second end of the first driving module 2 is connected with the third end of the third MOS transistor Q3, the third end of the first driving module 2 is connected with the second end of the microprocessor 13,
the second end of the second MOS tube Q2 is connected with the third end of the transformer 8 and the first end of the fourth MOS tube Q4, the third end of the second MOS tube Q2 is connected with the first end of the second driving module 3,
the second end of the second driving module 3 is connected with the third end of the fourth MOS transistor Q4, the third end of the second driving module 3 is connected with the third end of the microprocessor 13,
the fourth end of the transformer 8 is connected with the second end of the fifth MOS tube Q5 and the first end of the seventh MOS tube Q7, the fifth end of the transformer 8 is connected with the second end of the sixth MOS tube Q6 and the first end of the eighth MOS tube Q8,
the first end of the fifth MOS transistor Q5 is connected with the first end of the sixth MOS transistor Q6, the first end of the third capacitor C3 and the first end of the first inductor L1, the third end of the fifth MOS transistor Q5 is connected with the first end of the third driving module 4,
the second end of the third driving module 4 is connected with the third end of the seventh MOS transistor Q7, the third end of the third driving module 4 is connected with the fourth end of the microprocessor 13,
the third end of the sixth MOS transistor Q6 is connected to the first end of the fourth driving module 5, the second end of the fourth driving module 5 is connected to the third end of the eighth MOS transistor Q8, the third port of the fourth driving module 5 is connected to the fifth port of the microprocessor 13,
the second end of the third capacitor C3 is connected with the first end of the ninth MOS transistor Q9, the third end of the ninth MOS transistor Q9 is connected with the fifth driving module 6, the second end of the ninth MOS transistor Q9 is connected with the first end of the second resistor R2, the second end of the seventh MOS transistor Q7, the second end of the eighth MOS transistor Q8 and the first end of the second amplifier 10,
the second end of the first inductor L1 is connected to the first end of the second resistor R2 and the first end of the second amplifier 10, the second end of the first resistor R1 is connected to the first end of the second power supply 7 and the second end of the second amplifier 10, the third end of the second amplifier 10 is a signal output port,
a second end of the second power supply 7 is connected to the second end of the first resistor R1, the second end of the first amplifier 9 and to ground, a third end of the first amplifier 9 is connected to the sixth end of the microprocessor 13, a fourth end of the first amplifier 9 is connected to the reference voltage module 11,
the seventh port of the microprocessor 13 is connected to the switch module 12.
In the example, the source-load integrated circuit formed by the circuit, the first power supply module and the second power supply module can be used for realizing the multifunctional test of the tested equipment, so that the convenience of the equipment in use is improved.
In one possible implementation, as shown in fig. 2, the circuit further includes a third amplifier 14, where the third amplifier 14 is disposed between the first end of the first capacitor C1 and the first end of the microprocessor 13, and is at least used to connect the first end of the first capacitor C1 and the first end of the microprocessor 13.
In a possible implementation, as shown in fig. 2, the circuit further includes a fourth amplifier 15, where the fourth amplifier 15 is disposed between the second end of the third amplifier 14 and the first end of the microprocessor 13, and is at least used to connect the second end of the third amplifier 14 and the first end of the microprocessor 13.
The strength of signals collected by the microprocessor can be improved by arranging the third amplifier and the fourth amplifier, and the accuracy in subsequent processing is improved.
In one possible implementation, as shown in fig. 3, the eighth port of the microprocessor 13 is connected to the first transceiver module 16, the ninth port of the microprocessor 13 is connected to the I2C isolator 17, and the tenth port of the microprocessor 13 is connected to the second transceiver module 18.
In one possible implementation, as shown in fig. 4, the circuit further includes a grid-connected inverter 19, and the grid-connected inverter 19 is connected to the second power source 7.
In one possible implementation, the circuit further includes a first load module 20, where the first load module 20 includes a power source under test, a battery pack, and a DC/DC module, and the load module is connected to the first power source.
When the battery pack is charged, the module is used as a power source to provide energy for the battery pack, and conversely, when the battery pack is fully charged and enters a discharging state, the module is used as a feedback type load to return the discharging energy of the battery pack to a power grid through a rear-stage inverter, so that a bus end needs to be matched with the grid-connected inverter, and the module can work stably in both modes.
In a possible implementation, as shown in fig. 5, the circuit further comprises a dc power supply 21, the dc power supply 21 being connected to the second power supply 7.
In one possible implementation, the circuit further includes a second load module 22, the second load module 22 includes a battery pack, and the second load module 22 is connected to the first power source, and the first power source is used to charge the load module 22.
When the source load module is only used as a power supply, all the modules output energy outwards, so that the bus end is required to be matched with an AC/DC direct current power supply or a grid-connected inverter to provide energy for the source load module, and stable operation of the modules is ensured.
The dc power supply in the above embodiment may be replaced by a grid-connected inverter.
The third amplifier in the above embodiment may be an AMC1301 amplifier, the fourth amplifier may be an OPA376 amplifier, the microprocessor may be a TMS320F28033 chip, the first driving module and the second driving module may have the same model, and the third driving module and the fourth driving module may have the same model. The switch module may be a temperature switch module, the first amplifier may be OPA376, the second amplifier may be INA240, the fifth driver module may be UCC27517a, etc. The present utility model is not limited to the specific examples, and may be any other type of module.
The embodiment of the application also provides a source-carried integrated device, which comprises a circuit board and the bidirectional power supply circuit according to any one of the previous embodiments.
The embodiment of the application also provides a source-carried integrated device, which comprises a shell and the source-carried integrated device as in the previous embodiment.
It should be noted that, for simplicity of description, the foregoing method embodiments are all expressed as a series of action combinations, but it should be understood by those skilled in the art that the present application is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required in the present application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, such as the division of the units, merely a logical function division, and there may be additional manners of dividing the actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.
Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the above embodiments may be implemented by a program that instructs associated hardware, and the program may be stored in a computer readable memory, which may include: flash disk, read-only memory, random access memory, magnetic or optical disk, etc.
The foregoing has outlined rather broadly the more detailed description of embodiments of the present application, wherein specific examples are provided herein to illustrate the principles and embodiments of the present application, the above examples being provided solely to assist in the understanding of the methods of the present application and the core ideas thereof; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims (10)

1. A source-loaded integrated circuit, the circuit comprising: the first power supply, the second power supply, the first capacitor, the second capacitor, the third capacitor, the first driving module, the second driving module, the third driving module, the fourth driving module, the fifth driving module, the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the transformer, the first resistor, the second resistor, the first inductor, the first amplifier, the second amplifier, the reference voltage module, the switch module and the microprocessor,
the first end of the first power supply is connected with the first end of the first capacitor, the first end of the first MOS tube, the first end of the second MOS tube and the first end of the microprocessor,
the second end of the first power supply is connected with the second end of the second capacitor, the second end of the third MOS tube and the second end of the fourth MOS tube, the second end of the first capacitor is connected with the first end of the second capacitor and the first end of the transformer,
the second end of the first MOS tube is connected with the first end of the third MOS tube and the second end of the transformer,
the third end of the first MOS tube is connected with the first end of the first driving module, the second end of the first driving module is connected with the third end of the third MOS tube, the third end of the first driving module is connected with the second end of the microprocessor,
the second end of the second MOS tube is connected with the third end of the transformer and the first end of the fourth MOS tube, the third end of the second MOS tube is connected with the first end of the second driving module,
the second end of the second driving module is connected with the third end of the fourth MOS tube, the third end of the second driving module is connected with the third end of the microprocessor,
the fourth end of the transformer is connected with the second end of the fifth MOS tube and the first end of the seventh MOS tube, the fifth end of the transformer is connected with the second end of the sixth MOS tube and the first end of the eighth MOS tube,
the first end of the fifth MOS tube is connected with the first end of the sixth MOS tube, the first end of the third capacitor and the first end of the first inductor, the third end of the fifth MOS tube is connected with the first end of the third driving module,
the second end of the third driving module is connected with the third end of the seventh MOS tube, the third driving module obtains the third end to be connected with the fourth end of the microprocessor,
the third end of the sixth MOS tube is connected with the first end of the fourth driving module, the second end of the fourth driving module is connected with the third end of the eighth MOS tube, the third port of the fourth driving module is connected with the fifth port of the microprocessor,
the second end of the third capacitor is connected with the first end of the ninth MOS tube, the third end of the ninth MOS tube is connected with the fifth driving module, the second end of the ninth MOS tube is connected with the first end of the second resistor, the second end of the seventh MOS tube, the second end of the eighth MOS tube and the first end of the second amplifier,
the second end of the first inductor is connected with the first end of the second resistor and the first end of the second amplifier, the second end of the first resistor is connected with the first end of the second power supply and the second end of the second amplifier, the third end of the second amplifier is a signal output port,
the second end of the second power supply is connected with the second end of the first resistor and the second end of the first amplifier and grounded, the third end of the first amplifier is connected with the sixth end of the microprocessor, the fourth end of the first amplifier is connected with the reference voltage module,
the seventh port of the microprocessor is connected with the switch module.
2. The circuit of claim 1, further comprising a third amplifier disposed between the first end of the first capacitor and the first end of the microprocessor for connecting at least the first end of the first capacitor and the first end of the microprocessor.
3. The circuit of claim 2, further comprising a fourth amplifier disposed between the second end of the third amplifier and the first end of the microprocessor for connecting at least the second end of the third amplifier and the first end of the microprocessor.
4. A circuit according to any one of claims 1 to 3, wherein the eighth port of the microprocessor is connected to the first transceiver module, the ninth port of the microprocessor is connected to the I2C isolator, and the tenth port of the microprocessor is connected to the second transceiver module.
5. The circuit of claim 4, further comprising a grid-tie inverter connected to the second power source.
6. The circuit of claim 5, further comprising a first load module comprising a power source under test, a battery pack, a DC/DC module, the load module being connected to the first power source.
7. The circuit of claim 4, further comprising a dc power source connected to the second power source.
8. The circuit of claim 7, further comprising a second load module comprising a battery pack, the second load module being connected to the first power source for charging the load module.
9. A source-borne integrated device comprising a circuit board and a source-borne integrated circuit as claimed in any one of claims 1 to 8.
10. A source-borne integrated apparatus comprising a housing and the source-borne integrated device of claim 9.
CN202222936263.6U 2022-11-04 2022-11-04 Source-load integrated circuit, device and equipment Active CN219107301U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202222936263.6U CN219107301U (en) 2022-11-04 2022-11-04 Source-load integrated circuit, device and equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202222936263.6U CN219107301U (en) 2022-11-04 2022-11-04 Source-load integrated circuit, device and equipment

Publications (1)

Publication Number Publication Date
CN219107301U true CN219107301U (en) 2023-05-30

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Country Status (1)

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CN (1) CN219107301U (en)

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