CN219085020U - Overcurrent detection circuit and isolating switch controller - Google Patents
Overcurrent detection circuit and isolating switch controller Download PDFInfo
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- CN219085020U CN219085020U CN202223270331.6U CN202223270331U CN219085020U CN 219085020 U CN219085020 U CN 219085020U CN 202223270331 U CN202223270331 U CN 202223270331U CN 219085020 U CN219085020 U CN 219085020U
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Abstract
The embodiment of the utility model provides an overcurrent detection circuit and an isolating switch controller, which comprise: the first end of the first current detection resistor is electrically connected with the first power supply end, and the second end of the first current detection resistor is electrically connected with the second power supply end; the inverting input end of the first operational amplifier is electrically connected with the first end of the first current detection resistor, and the non-inverting input end of the first operational amplifier is electrically connected with the second end of the first current detection resistor; the first input end of the first comparator is electrically connected with the output end of the first operational amplifier, and the second input end of the first comparator is electrically connected with the first reference source; and the input end of the first D trigger is electrically connected with the output end of the first comparator. The embodiment of the utility model automatically disconnects the first power supply end and the second power supply end when the overcurrent fault occurs, and automatically restores the connection between the first power supply end and the second power supply end after the overcurrent fault disappears.
Description
Technical Field
The utility model relates to an automobile electronic design technology, in particular to an overcurrent detection circuit and an isolating switch controller.
Background
With the increasing sophistication and popularization of automatic driving, the whole vehicle also puts higher demands on the safety of a power supply network for realizing the safety function in an automatic mode. In order to avoid accidents caused by the fact that a vehicle braking system cannot work normally when a power supply network fails, the whole vehicle power supply architecture needs to be added with an isolating switch controller module of a power supply. The power supply network failure protection device provides necessary guarantee for the automatic driving part and the automobile safety part to complete the functions according to the established design requirements under the power supply network failure condition.
The main function of the power isolation module is to monitor the current passing through the controller, and when the current passing through the isolation switch controller exceeds a set threshold value, the MOSFET (i.e. the metal-oxide semiconductor field effect transistor) in the isolation switch controller can be actively disconnected, so that the isolation switch controls the power networks at two sides to be isolated, and the controllers at two ends of the power supply can be protected to work normally.
Disclosure of Invention
The embodiment of the utility model provides an overcurrent detection circuit and an isolating switch controller, which are used for automatically disconnecting a first power end from a second power end when an overcurrent fault occurs and automatically recovering the connection between the first power end and the second power end after the overcurrent fault disappears.
In a first aspect, an embodiment of the present utility model provides an overcurrent detection circuit, including:
the first end of the first current detection resistor is electrically connected with the first power supply end, and the second end of the first current detection resistor is electrically connected with the second power supply end;
the inverting input end of the first operational amplifier is electrically connected with the first end of the first current detection resistor, and the non-inverting input end of the first operational amplifier is electrically connected with the second end of the first current detection resistor;
the first input end of the first comparator is electrically connected with the output end of the first operational amplifier, and the second input end of the first comparator is electrically connected with a first reference source;
and the input end of the first D trigger is electrically connected with the output end of the first comparator.
Optionally, the device further comprises a first driving chip, wherein the first driving chip is electrically connected with the first output end of the first D trigger and is configured to control on-off between the first power end and the second power end according to an output signal of the first D trigger.
Optionally, the circuit further comprises a first transistor and a second transistor;
the first end of the first transistor is electrically connected with the first power supply end, the second end of the first transistor is electrically connected with the first end of the second transistor, and the second end of the second transistor is electrically connected with the first end of the first current detection resistor;
the control end of the first transistor and the control end of the second transistor are electrically connected with the first driving chip.
Optionally, the first power end is a DC/DC power network, and the second power end is a storage battery.
Optionally, the method further comprises:
the first end of the second current detection resistor is electrically connected with the first power end, and the second end of the second current detection resistor is electrically connected with the first end of the first current detection resistor;
the non-inverting input end of the second operational amplifier is electrically connected with the first end of the second current detection resistor, and the inverting input end of the second operational amplifier is electrically connected with the second end of the second current detection resistor;
the first input end of the second comparator is electrically connected with the output end of the second operational amplifier, and the second input end of the second comparator is electrically connected with a second reference source;
and the input end of the second D trigger is electrically connected with the output end of the second comparator.
Optionally, the circuit further comprises a second driving chip, wherein the second driving chip is electrically connected with the first output end of the second D trigger and is configured to control on-off between the first power end and the first end of the first current detection resistor according to an output signal of the second D trigger.
Optionally, a third transistor and a fourth transistor are further included;
the first end of the third transistor is electrically connected with the second end of the second current detection resistor, the second end of the third transistor is electrically connected with the first end of the fourth transistor, and the second end of the fourth transistor is electrically connected with the first end of the first current detection resistor;
and the control end of the third transistor and the control end of the fourth transistor are electrically connected with the second driving chip.
Optionally, the first reference source and the second reference source have the same voltage.
Optionally, the device further comprises a microcontroller, wherein an input end of the microcontroller is electrically connected with a second output end of the first D trigger.
In a second aspect, an embodiment of the present utility model provides an isolating switch controller, including the overcurrent detection circuit in the first aspect.
The overcurrent detection circuit provided by the embodiment of the utility model comprises a first current detection resistor, a first operational amplifier, a first comparator, a first reference source and a first D trigger. When the overcurrent fault occurs, the connection between the first power supply end and the second power supply end is automatically disconnected, and after the overcurrent fault disappears, the connection between the first power supply end and the second power supply end is automatically restored.
Drawings
Fig. 1 is a schematic diagram of an overcurrent detection circuit according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of another overcurrent detection circuit according to an embodiment of the present utility model;
fig. 3 is a schematic diagram of another overcurrent detection circuit according to an embodiment of the present utility model.
Detailed Description
The utility model is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present utility model are shown in the drawings.
Fig. 1 is a schematic diagram of an overcurrent detection circuit according to an embodiment of the utility model, and referring to fig. 1, the overcurrent detection circuit includes a first current detection resistor R1, a first operational amplifier 11, a first comparator 12, a first reference source 13, and a first D flip-flop 14. The first end of the first current detection resistor R1 is electrically connected to the first power supply end U1, and the second end of the first current detection resistor R1 is electrically connected to the second power supply end U2. The inverting input terminal IN-of the first operational amplifier 11 is electrically connected to the first terminal of the first current detecting resistor R1, and the non-inverting input terminal in+ of the first operational amplifier 11 is electrically connected to the second terminal of the first current detecting resistor R1. A first input of the first comparator 12 is electrically connected to an output of the first operational amplifier 11, and a second input of the first comparator 12 is electrically connected to the first reference source 13. The first reference source 13 is configured to provide a first reference voltage. An input of the first D flip-flop 14 is electrically connected to an output of the first comparator 12.
Illustratively, when current flows from the second power terminal U2 to the first power terminal U1, the first current detecting resistor R1 is required to determine whether there is an overcurrent fault. The first operational amplifier 11 obtains the voltage of the first end of the first current detecting resistor R1 and the voltage of the second end of the first current detecting resistor R1, calculates the difference between the voltage of the first end of the first current detecting resistor R1 and the voltage of the second end of the first current detecting resistor R1, amplifies the difference, outputs the amplified difference to the first comparator 12, and compares the amplified difference with the first reference voltage by the first comparator 12. If the difference value amplified by the first comparator 12 is greater than the first reference voltage, the current flowing from the second power terminal U2 to the first power terminal U1 has an overcurrent fault, and the first D flip-flop 14 sends a level signal to automatically disconnect the connection between the first power terminal U1 and the second power terminal U2.
After the overcurrent fault existing in the current flowing from the second power supply terminal U2 to the first power supply terminal U1 disappears, the difference value amplified by the first comparator 12 is smaller than the first reference voltage, the first D flip-flop 14 sends a level signal, and the connection between the first power supply terminal U1 and the second power supply terminal U2 is automatically restored.
The overcurrent detection circuit provided by the embodiment of the utility model comprises a first current detection resistor R1, a first operational amplifier 11, a first comparator 12, a first reference source 13 and a first D trigger 14. When the overcurrent fault occurs, the connection between the first power supply end and the second power supply end is automatically disconnected, and after the overcurrent fault disappears, the connection between the first power supply end and the second power supply end is automatically restored.
Optionally, referring to fig. 1, the over-current detection circuit further includes a first driving chip 15. The first driving chip 15 is electrically connected to the first output terminal of the first D flip-flop 14, and the first driving chip 15 is configured to control on-off between the first power supply terminal U1 and the second power supply terminal U2 according to an output signal of the first D flip-flop 14. It can be appreciated that, when an overcurrent fault occurs, the first driving chip 15 is configured to control the first power supply terminal U1 to be disconnected from the second power supply terminal U2 according to the output signal of the first D flip-flop 14; after the overcurrent fault disappears, the first driving chip 15 is configured to control the first power supply terminal U1 and the second power supply terminal U2 to resume connection according to the output signal of the first D flip-flop 14.
Optionally, referring to fig. 1, the over-current detection circuit further includes a first transistor T1 and a second transistor T2. The first end of the first transistor T1 is electrically connected to the first power supply terminal U1, the second end of the first transistor T1 is electrically connected to the first end of the second transistor T2, and the second end of the second transistor T2 is electrically connected to the first end of the first current detecting resistor R1. The control terminal of the first transistor T1 and the control terminal of the second transistor T2 are electrically connected to the first driving chip 15 (connection relationship between the control terminal of the first transistor T1 and the control terminal of the second transistor T2 and the first driving chip 15 is not shown in fig. 1). In the embodiment of the present utility model, the first transistor T1 and the second transistor T2 are connected in series between the first power terminal U1 and the first end of the first current detection resistor R1, that is, the first transistor T1 and the second transistor T2 are connected in series between the first power terminal U1 and the second power terminal U2, and the first driving chip 15 controls the on/off between the first power terminal U1 and the second power terminal U2 by controlling the on/off of the first transistor T1 and the second transistor T2.
Optionally, referring to fig. 1, the first power terminal U1 is a DC/DC power network, and the second power terminal U2 is a battery.
Fig. 2 is a schematic diagram of another over-current detection circuit according to an embodiment of the present utility model, and referring to fig. 2, the over-current detection circuit further includes a second current detection resistor R2, a second operational amplifier 21, a second comparator 22, a second reference source 23, and a second D flip-flop 24. The first end of the second current detecting resistor R2 is electrically connected to the first power end U1, and the second end of the second current detecting resistor R2 is electrically connected to the first end of the first current detecting resistor R1. The non-inverting input terminal in+ of the second operational amplifier 21 is electrically connected to the first terminal of the second current detecting resistor R2, and the inverting input terminal IN-of the second operational amplifier 21 is electrically connected to the second terminal of the second current detecting resistor R2. The first input of the second comparator 22 is electrically connected to the output of the second operational amplifier 21, and the second input of the second comparator 22 is electrically connected to the second reference source 23. The second reference source 23 is configured to provide a second reference voltage. An input of the second D flip-flop 24 is electrically connected to an output of the second comparator 22.
Illustratively, when current flows from the first power terminal U1 to the second power terminal U2, the second current detecting resistor R2 is required to determine whether there is an overcurrent fault. The second operational amplifier 21 obtains the voltage of the first end of the second current detecting resistor R2 and the voltage of the second end of the second current detecting resistor R2, calculates the difference between the voltage of the first end of the second current detecting resistor R2 and the voltage of the second end of the second current detecting resistor R2, amplifies the difference, outputs the amplified difference to the second comparator 22, and compares the amplified difference with the second reference voltage by the second comparator 22. If the amplified difference of the second comparator 22 is greater than the second reference voltage, the current flowing from the first power terminal U1 to the second power terminal U2 has an overcurrent fault, and the second D flip-flop 24 sends a level signal to automatically disconnect the connection between the first power terminal U1 and the second power terminal U2.
After the overcurrent fault existing in the current flowing from the first power supply terminal U1 to the second power supply terminal U2 disappears, the difference value amplified by the second comparator 22 is smaller than the second reference voltage, and the second D flip-flop 24 sends a level signal to automatically restore the connection between the first power supply terminal U1 and the second power supply terminal U2.
The overcurrent detection circuit provided by the embodiment of the utility model not only realizes that the connection between the first power supply end and the second power supply end is automatically disconnected when an overcurrent fault occurs, but also automatically restores the connection between the first power supply end and the second power supply end after the overcurrent fault disappears. In addition, according to the flow direction of the unused current, two current detecting resistors, namely a first current detecting resistor R1 and a second current detecting resistor R2, are correspondingly arranged, so that the bidirectional detection and control of the current are realized.
Optionally, referring to fig. 2, the over-current detection circuit further includes a second driving chip 25. The second driving chip 25 is electrically connected to the first output terminal of the second D flip-flop 24, and the second driving chip 25 is configured to control the on-off between the first power supply terminal U1 and the first terminal of the first current detection resistor R1 according to the output signal of the second D flip-flop. It can be appreciated that, when the overcurrent fault occurs, the second driving chip 25 is configured to control the first power supply terminal U1 to be disconnected from the first terminal of the first current detecting resistor R1 according to the output signal of the second D flip-flop 24; after the overcurrent fault disappears, the second driving chip 25 is configured to control the first power supply terminal U1 to resume the connection with the first terminal of the first current detecting resistor R1 according to the output signal of the second D flip-flop 24.
Optionally, referring to fig. 2, the over-current detection circuit further includes a third transistor T3 and a fourth transistor T4. The first end of the third transistor T3 is electrically connected to the second end of the second current sensing resistor R2, the second end of the third transistor T3 is electrically connected to the first end of the fourth transistor T4, and the second end of the fourth transistor T4 is electrically connected to the first end of the first current sensing resistor R1. The control terminal of the third transistor T3 and the control terminal of the fourth transistor T4 are electrically connected to the second driving chip 25. (the connection relationship of the control terminal of the third transistor T3 and the control terminal of the fourth transistor T4 with the second driving chip 25 is not shown in fig. 2). In the embodiment of the present utility model, the third transistor T3 and the fourth transistor T4 are connected in series between the second end of the second current detecting resistor R2 and the first end of the first current detecting resistor R1, that is, the third transistor T3 and the fourth transistor T4 are connected in series between the first power end U1 and the second power end U2, and the second driving chip 25 controls the on/off between the first power end U1 and the second power end U2 by controlling the on/off of the third transistor T3 and the fourth transistor T4.
Alternatively, referring to fig. 2, the first reference source 13 and the second reference source 23 have the same voltage. The first reference voltage is the same as the second reference voltage so that the first reference source 13 can be multiplexed as the second reference source 23, simplifying the circuit configuration.
Fig. 3 is a schematic diagram of another over-current detection circuit according to an embodiment of the present utility model, and referring to fig. 3, the over-current detection circuit further includes a microcontroller 30, and an input terminal of the microcontroller 30 is electrically connected to the second output terminal of the first D flip-flop 14. When the overcurrent fault exists or disappears in the current flowing from the second power supply terminal U2 to the first power supply terminal U1, the first D flip-flop 14 sends a level signal, and the connection between the first power supply terminal U1 and the second power supply terminal U2 is automatically disconnected or restored. In addition, the first D flip-flop 14 also sends a level signal to the microcontroller 30 to inform the microcontroller 30 whether the current flowing from the second power terminal U2 to the first power terminal U1 has an overcurrent fault.
Illustratively, referring to fig. 3, an input of microcontroller 30 is electrically connected to a second output of second D flip-flop 24. When the overcurrent fault exists or disappears in the current flowing from the first power supply terminal U1 to the second power supply terminal U2, the second D flip-flop 24 sends a level signal, and the connection between the first power supply terminal U1 and the second power supply terminal U2 is automatically disconnected or restored. In addition, the second D flip-flop 24 also sends a level signal to the microcontroller 30 to inform the microcontroller 30 whether the current flowing from the first power terminal U1 to the second power terminal U2 has an overcurrent fault.
As an example, when current flows from the second power terminal U2 to the first power terminal U1, the first current detecting resistor R1 is needed to determine whether there is an overcurrent fault. Through the voltage difference across the first current detecting resistor R1, the voltage at the non-inverting input terminal in+ of the first operational amplifier 11 is greater than the voltage at the inverting input terminal IN-of the first operational amplifier 11, the first operational amplifier 11 amplifies the voltage difference between the non-inverting input terminal in+ and the inverting input terminal IN-by one hundred times and outputs the amplified voltage difference to the first comparator 12, and the first reference source 13 outputs 2.5V to the other pin of the first comparator 12 as the first reference voltage of the first comparator 12. The amplified differential voltage value output by the first operational amplifier 11 will be compared with the set reference voltage of 2.5V, if the differential voltage value is greater than 2.5V, it is considered that an overcurrent fault occurs in the direction from the second power supply terminal U2 to the first power supply terminal U1, at this time, the first D flip-flop 14 will send two different level signals, a high level signal to the first driving chip 15, so that it terminates the output of the driving voltage within 1ms to turn off the first transistor T1 and the second transistor T2, and a low level signal is output to the microcontroller 30, to tell the microcontroller 30 that the overcurrent fault occurs. In normal, the first D flip-flop 14 outputs a low level signal to the first driving chip 15 to keep the first transistor T1 and the second transistor T2 turned on, and outputs a high level signal to the microcontroller 30 to tell the microcontroller 30 that no overcurrent fault occurs. If the overcurrent fault is recovered, the overcurrent detection circuit can be automatically reset to recover to close the first transistor T1 and the second transistor T2.
When current flows from the first power supply terminal U1 to the second power supply terminal U2, the second current detecting resistor R2 is needed to determine whether there is an overcurrent fault, and the voltage difference across the second current detecting resistor R2 is collected, so that the voltage at the IN-phase input terminal in+ of the second operational amplifier 21 is greater than the voltage at the IN-phase input terminal IN-phase of the second operational amplifier 21, the voltage difference between the IN-phase input terminal in+ and the IN-phase input terminal IN-phase of the second operational amplifier 21 is amplified by one hundred times and then outputted to the second comparator 22, and the second reference source 23 outputs 2.5V to the other pin of the second comparator 22 as the second reference voltage of the second comparator 22. The amplified differential voltage value output by the second operational amplifier 21 will be compared with the set reference voltage of 2.5V, if the differential voltage value is greater than 2.5V, it is considered that an overcurrent fault occurs in the direction of the first power supply terminal U1 flowing to the second power supply terminal U2, at this time, the second D flip-flop 24 will send two different level signals, a high level signal to the second driving chip 25, so that it terminates the output driving voltage at 1ms to turn off the third transistor T3 and the fourth transistor T4, and a low level signal is output to the microcontroller 30, to tell the microcontroller 30 that the overcurrent fault occurs. In normal, the second D flip-flop 24 outputs a low level signal to the second driving chip 25 to keep the third transistor T3 and the fourth transistor T4 turned on, and outputs a high level signal to the microcontroller 30 to tell the microcontroller 30 that no overcurrent fault occurs. If the overcurrent fault is recovered, the overcurrent detection circuit may be automatically reset to recover the third transistor T3 and the fourth transistor T4.
The overcurrent threshold calculation process is as follows: the threshold value of the overcurrent is set to 125A, the resistance value of the current detection resistor (for example, the first current detection resistor R1 or the second current detection resistor R2) is set to 0.2mΩ, and the amplification factor of the operational amplifier (for example, the first operational amplifier 11 or the second operational amplifier 21) is set to 100. The voltage threshold that is output to a comparator (e.g., first comparator 12 or second comparator 22) to compare with the 2.5V reference voltage is: 125A (0.2 x 10-3) Ω x 100=2.5V. Then, if the voltage output to the operational amplifier is greater than 2.5V, we can consider that the current value exceeds 125A, i.e., an overcurrent fault occurs, and if the voltage value is not greater than 2.5V, no overcurrent fault occurs. Meanwhile, according to different overcurrent thresholds, the current detection resistor with different resistance values or the operational amplifier with different amplification factors can be selected.
The embodiment of the utility model also provides an isolating switch controller, which comprises the overcurrent detection circuit in the embodiment.
The over-current detection circuit may be provided on the PCB of the isolating switch controller, for example.
Note that the above is only a preferred embodiment of the present utility model and the technical principle applied. It will be understood by those skilled in the art that the present utility model is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the utility model. Therefore, while the utility model has been described in connection with the above embodiments, the utility model is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the utility model, which is set forth in the following claims.
Claims (10)
1. An overcurrent detection circuit, comprising:
the first end of the first current detection resistor is electrically connected with the first power supply end, and the second end of the first current detection resistor is electrically connected with the second power supply end;
the inverting input end of the first operational amplifier is electrically connected with the first end of the first current detection resistor, and the non-inverting input end of the first operational amplifier is electrically connected with the second end of the first current detection resistor;
the first input end of the first comparator is electrically connected with the output end of the first operational amplifier, and the second input end of the first comparator is electrically connected with a first reference source;
and the input end of the first D trigger is electrically connected with the output end of the first comparator.
2. The overcurrent detection circuit of claim 1, further comprising a first driver chip electrically connected to the first output of the first D flip-flop and configured to control the on-off between the first power supply terminal and the second power supply terminal according to an output signal of the first D flip-flop.
3. The overcurrent detection circuit of claim 2, further comprising a first transistor and a second transistor;
the first end of the first transistor is electrically connected with the first power supply end, the second end of the first transistor is electrically connected with the first end of the second transistor, and the second end of the second transistor is electrically connected with the first end of the first current detection resistor;
the control end of the first transistor and the control end of the second transistor are electrically connected with the first driving chip.
4. The overcurrent detection circuit of claim 1, wherein the first power supply terminal is a DC/DC power supply network and the second power supply terminal is a battery.
5. The overcurrent detection circuit of claim 4, further comprising:
the first end of the second current detection resistor is electrically connected with the first power end, and the second end of the second current detection resistor is electrically connected with the first end of the first current detection resistor;
the non-inverting input end of the second operational amplifier is electrically connected with the first end of the second current detection resistor, and the inverting input end of the second operational amplifier is electrically connected with the second end of the second current detection resistor;
the first input end of the second comparator is electrically connected with the output end of the second operational amplifier, and the second input end of the second comparator is electrically connected with a second reference source;
and the input end of the second D trigger is electrically connected with the output end of the second comparator.
6. The overcurrent detection circuit of claim 5, further comprising a second driver chip electrically connected to the first output of the second D flip-flop and configured to control the on-off between the first power supply terminal and the first terminal of the first current sensing resistor according to an output signal of the second D flip-flop.
7. The overcurrent detection circuit of claim 6, further comprising a third transistor and a fourth transistor;
the first end of the third transistor is electrically connected with the second end of the second current detection resistor, the second end of the third transistor is electrically connected with the first end of the fourth transistor, and the second end of the fourth transistor is electrically connected with the first end of the first current detection resistor;
and the control end of the third transistor and the control end of the fourth transistor are electrically connected with the second driving chip.
8. The over-current detection circuit of claim 5, wherein the first reference source and the second reference source have the same voltage.
9. The over-current detection circuit of claim 1, further comprising a microcontroller having an input electrically connected to the second output of the first D flip-flop.
10. An isolating switch controller comprising the overcurrent detection circuit of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223270331.6U CN219085020U (en) | 2022-12-06 | 2022-12-06 | Overcurrent detection circuit and isolating switch controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223270331.6U CN219085020U (en) | 2022-12-06 | 2022-12-06 | Overcurrent detection circuit and isolating switch controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219085020U true CN219085020U (en) | 2023-05-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223270331.6U Active CN219085020U (en) | 2022-12-06 | 2022-12-06 | Overcurrent detection circuit and isolating switch controller |
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| Country | Link |
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| CN (1) | CN219085020U (en) |
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2022
- 2022-12-06 CN CN202223270331.6U patent/CN219085020U/en active Active
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