CN219066824U - Semiconductor structure and semiconductor multiphase power management module - Google Patents

Semiconductor structure and semiconductor multiphase power management module Download PDF

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Publication number
CN219066824U
CN219066824U CN202220800166.1U CN202220800166U CN219066824U CN 219066824 U CN219066824 U CN 219066824U CN 202220800166 U CN202220800166 U CN 202220800166U CN 219066824 U CN219066824 U CN 219066824U
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chip
integrated capacitor
conductive layer
power
substrate
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宋璐瑶
樊航
吴健
时磊
许曙明
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Shanghai Bright Power Semiconductor Co Ltd
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Shanghai Bright Power Semiconductor Co Ltd
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Abstract

A semiconductor structure and a semiconductor multiphase power management module, wherein the semiconductor structure comprises at least one first chip, the first chip comprises a semiconductor substrate and an active layer formed on the upper surface of the substrate, one or more lateral metal oxide semiconductor devices formed in the active layer of the first chip. The semiconductor structure further includes at least one first integrated capacitor disposed on a back side of the semiconductor substrate of the first chip. The first integrated capacitor includes a first conductive layer electrically connected to the back surface of the substrate, an insulating layer formed on at least a portion of an upper surface of the first conductive layer, and a second conductive layer formed on at least a portion of an upper surface of the insulating layer.

Description

Semiconductor structure and semiconductor multiphase power management module
Technical Field
The present utility model relates generally to electrical, electronic and computer technology, and more particularly to an improved bipolarcmos DMOS (BCD) structure.
Background
After the advent of Integrated Circuits (ICs) in the 50 s of the 20 th century, branches of several basic technology routes have emerged: bipolar junction transistor (Bipolar) technology was invented in the 50 s of the 20 th century; complementary Metal Oxide Semiconductor (CMOS) devices invented in the 60 s of the 20 th century; and double Diffused Metal Oxide Semiconductor (DMOS) devices invented in the 70 s of the 20 th century. However, since the beginning of the 80 s of the 20 th century, it is sometimes necessary to employ both of these three technologies simultaneously to meet the higher voltage and faster switching speed requirements. As the name suggests, BCD technology combines the advantages of bipolars, CMOS and DMOS technologies, integrated into the same IC package. Accordingly, BCD technology has become a widely used platform such as Power Management Integrated Circuits (PMIC), analog integrated circuits, and radio frequency integrated circuits.
However, integration of bipolars, CMOS and DMOS technologies presents some design challenges. For example, integrating low voltage CMOS devices with high voltage DMOS devices increases latch-up (latch-up) and noise in the overall chip design, and care must be taken to effectively isolate the low and high voltage devices from each other. For a fixed area chip, the required isolation space between low and high voltage devices can significantly reduce the active chip area available or otherwise increase the overall size of the chip. In conventional designs, off-chip (off-chip) or discrete capacitors (discrete capacitors) mounted on a circuit board or inside a chip package are typically used to reduce noise and stabilize the supply voltage. However, this increases the size of the module. In addition, the electrical connection between the capacitor and the high voltage device typically introduces significant parasitic impedance (mainly inductance and capacitance), thereby degrading high frequency performance.
Disclosure of Invention
The present utility model, in one or more illustrative embodiments, advantageously provides an enhanced bipolarcmos-DMOS (BCD) device, and methods for fabricating such a device. Embodiments of the present utility model include three-dimensional (3D) structures in which low voltage Bipolar devices and CMOS devices and/or circuits are advantageously arranged in a stacked fashion relative to high voltage DMOS devices and/or circuits. The 3D structure includes backside devices and passive components, such as integrated capacitors formed using lateral Metal Oxide Semiconductor (MOS) technology, that advantageously eliminate or at least reduce stray impedance (especially parasitic inductance) to reduce noise and voltage spikes on the switching node (SW) to provide excellent high frequency performance.
According to one embodiment of the present utility model, a semiconductor structure includes at least a first chip including a semiconductor substrate and an active layer formed on an upper surface of the substrate, one or more lateral metal oxide semiconductor devices being formed in the active layer of the first chip. The BCD structure further includes at least a first integrated capacitor disposed on a back side of the semiconductor substrate of the first chip. The first integrated capacitor includes a first conductive layer electrically connected to the back surface of the substrate, an insulating layer formed on at least a portion of the upper surface of the first conductive layer, and a second conductive layer formed on at least a portion of the upper surface of the insulating layer.
According to yet another embodiment of the present utility model, a three-dimensional BCD structure includes at least one first chip including at least one power MOS transistor, and at least one second chip including a driving circuit disposed in a stacked arrangement with respect to the first chip. The BCD structure further includes at least a first integrated capacitor disposed between the first and second chips and electrically coupled to the at least one drive circuit and the at least one power MOS transistor.
According to another embodiment of the present utility model, a semiconductor multi-phase power management module includes a multi-phase power chip including a semiconductor substrate and an active layer formed on an upper surface of the substrate, with a plurality of lateral MOS devices formed in the active layer of the multi-phase power chip. The multi-phase power management module further includes a plurality of driver chips arranged in a stacked manner on a back side of the multi-phase power stage chip, each driver chip including a driver circuit for controlling a respective one of the lateral MOS devices formed in the multi-phase power stage chip. At least one integrated capacitor is disposed between the plurality of driver chips and the multi-phase power stage chip, the integrated capacitor including a first conductive layer electrically connected to a back surface of a substrate of the multi-phase power stage chip, an insulating layer formed on at least a portion of an upper surface of the first conductive layer, and a second conductive layer formed on at least a portion of an upper surface of the insulating layer.
The technical scheme of the utility model can provide substantial beneficial technical effects. By way of example only and not limitation, a three-dimensional BCD structure with backside integrated capacitors in accordance with one or more embodiments of the present utility model may provide one or more of the following advantages:
Minimizing the distance between the integrated capacitor and the associated load;
effectively reducing the size of the application module;
effectively eliminating noise caused by parasitic impedance;
have lower switching node electrical overstress and enhanced power stage robustness;
enabling the fabrication of low and high voltage devices on different platforms separately;
by multiplexing the known good designs, only the necessary devices or components are changed, thereby speeding up the development cycle;
the enhanced isolation between low and high voltage devices may reduce noise and reduce the risk of latch-up;
the active area in a particular application is greater due to the reduced or eliminated isolation space between the low and high voltage devices;
higher power capacity and/or higher power density and lower conduction loss due to higher active area utilization in a particular application;
compatible flexible packaging designs.
The above features, technical features, advantages and implementation thereof will be further described in the following detailed description of preferred embodiments with reference to the accompanying drawings in a clearly understandable manner.
Drawings
The following figures are shown by way of example only and not limitation, in which like reference numerals refer to corresponding elements throughout the several views (when used), and in which:
FIG. 1 is a schematic diagram schematically illustrating at least a portion of a power management circuit suitable for use in applications such as a standard Direct Current (DC) -DC converter with an off-chip capacitor;
FIG. 2 is a cross-sectional view schematically illustrating a semiconductor structure including at least one Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device integrated with a single back-side capacitor, in accordance with one or more embodiments of the present utility model;
fig. 3 is a flow diagram illustrating an exemplary method of at least a portion of one or more embodiments of the present utility model for a semiconductor structure including at least one MOSFET device and a back-side integrated capacitor;
FIGS. 4A through 4D are cross-sectional views schematically illustrating intermediate steps of at least a portion of the exemplary manufacturing method shown in FIG. 3 in accordance with one or more embodiments of the present disclosure;
fig. 5 is a cross-sectional view schematically illustrating a semiconductor structure including a single back side capacitor integrated with a MOS structure, wherein the single integrated capacitor includes a first conductive layer formed on a substrate of a chip and a second conductive layer formed of a metal film, respectively, in accordance with at least a portion of one or more embodiments of the present utility model;
FIG. 6 is a cross-sectional view schematically illustrating a semiconductor structure of at least a portion consistent with the exemplary semiconductor structure shown in FIG. 5, in which a single integrated capacitor includes first and second conductive layers formed of different metals, in accordance with one or more embodiments of the present utility model;
FIG. 7 schematically illustrates a cross-sectional view of an exemplary structure including a single integrated capacitor formed between two stacked semiconductor structures, wherein the single integrated capacitor includes a first conductive layer formed on a substrate of a first chip and a second conductive layer formed on a substrate of a second chip, respectively, in accordance with one or more embodiments of the utility model;
FIG. 8 is a cross-sectional view schematically illustrating at least a portion of an exemplary semiconductor structure including at least one MOSFET device integrated with a plurality of back-side capacitors, each capable of being biased to a different voltage based on a circuit application, in accordance with one or more embodiments of the present utility model;
fig. 9A is a top perspective view, and fig. 9B and 9C are cross-sectional views schematically illustrating a stacked power management module including at least one integrated capacitor in accordance with one or more embodiments of the present utility model;
FIGS. 10-14 are top perspective views schematically showing at least a portion of an exemplary power management module from various illustrative directions of a driver chip and a power chip in accordance with an illustrative embodiment of the present utility model;
15-18 are top perspective views showing at least a portion of an exemplary power management module having various illustrative connection arrangements between integrated capacitors, power and driver chips and a carrier (e.g., interposer) or other substrate, according to an illustrative embodiment of the utility model;
FIG. 19A is a schematic diagram illustrating at least a portion of an exemplary multi-phase power management circuit that may incorporate one or more aspects of the present utility model;
FIG. 19B is a top perspective view of at least a portion of the exemplary multi-phase power management circuit shown in FIG. 19A;
FIG. 20A is a schematic diagram illustrating at least a portion of an exemplary multi-phase power circuit with shared integrated input capacitors in accordance with one or more embodiments of the utility model; and
FIG. 20B is a top perspective view illustrating at least a portion of the exemplary multi-phase power management circuit shown in FIG. 20A in accordance with one or more embodiments of the present utility model.
It should be appreciated that the drawing of elements in the drawings are for simplicity and clarity of illustration, and that certain commonly practiced but well-understood elements have not been shown in order to facilitate a less obstructed view of these embodiments, although they may be useful or necessary in commercially feasible embodiments.
Detailed Description
As shown in one or more embodiments, the principles of the present utility model, including low voltage bipolardevices and CMOS devices and/or circuits, disposed in a stacked arrangement of high voltage DMOS devices and/or circuits, will be described herein in the context of various illustrative three-dimensional (3D) structures and methods of fabricating such structures. The 3D structure also includes a back-side integrated capacitor formed using semiconductor processing steps compatible with CMOS or DMOS processing flows that advantageously eliminate or at least reduce parasitic impedance (particularly inductance) to reduce noise and voltage peaks on the switching node (SW) to achieve superior high frequency performance. However, it should be understood that the utility model is not limited to the particular apparatus and/or methods illustrated and described herein. Rather, it will be apparent to those skilled in the art from this disclosure that many modifications can be made to the embodiments that are within the scope of the described utility model. That is, the limitations with respect to the embodiments shown and described herein are not intended, nor should they be inferred.
For purposes of describing and protecting embodiments of the present utility model, the default meaning of terms that may be used herein should be construed broadly and include any type of metal-insulator-semiconductor field-effect transistor. For example, the term MISFET is meant to include semiconductor field effect transistors that use an oxide material as a gate dielectric (i.e., MOSFET), as well as semiconductor field effect transistors that do not use an oxide material. Furthermore, although the term "metal" is mentioned in the acronym MISFET and MOSFET, the meaning of the term MISFET and MOSFET also encompasses semiconductor field effect transistors in which the gate is formed of a non-metallic material, such as polysilicon; the terms "mis et" and "MOSFET" are used interchangeably herein.
Although the overall fabrication method and structure formed thereby is entirely new, certain individual processing steps required for one or more portions of the method in accordance with one or more embodiments of the present utility model may utilize conventional semiconductor fabrication techniques and conventional semiconductor processing equipment. Such techniques and process equipment are familiar to those having ordinary skill in the relevant art. In addition, many of the processing steps and process equipment used to fabricate semiconductor devices are also described in some of the available publications and may be incorporated by reference in their entirety, including: h. holloway et al, handbook of composite semiconductors: growth, processing, properties and devices, university of cambridge press, 2008; and R.K. Willardson et al, academic Press, 2001. It is emphasized that although individual processing steps are set forth herein, these steps are merely illustrative and that those skilled in the art are familiar with a number of equally suitable alternatives, which are also within the scope of the utility model.
It should be understood that the various layers and/or regions illustrated in the figures are not necessarily drawn to scale. Furthermore, one or more types of semiconductor layers commonly used in such integrated circuit devices may not be explicitly shown in a given figure for the sake of more concise description. However, this does not mean that a semiconductor layer not explicitly shown is omitted in an actual integrated circuit device.
The schematic diagram of fig. 1 illustrates at least a portion of an exemplary power management circuit 100 suitable for use in, for example, standard DC-DC converter applications. The power management circuit 100 includes a controller 102 coupled to a driver 104. The driver 104 is configured to generate control signals for activating the high side MOSFET device HS and/or the low side MOSFET device LS from the controller 102 generating at least one signal. More specifically, a first control signal generated by the driver 104 is provided to the gate (G) of the high-side MOSFET device, and a second control signal generated by the driver is provided to the gate of the low-side MOSFET device. The source (S) of the high side MOSFET device is connected to the drain (D) of the low side MOSFET device at a switching node SW. Drain of high-side MOSFET device and input voltage terminal V of power management circuit 100 IN Connected, while the source of the low-side MOSFET device is coupled to the voltage return (voltage return) of the circuit, which is preferably Ground (GND).
Normally at input voltage terminal V IN An external input capacitor C is arranged between the ground potential and the capacitor C IN To reduce voltage spikes at the input voltage terminals of the power management circuit 100. Input capacitor C IN Is typically located external to the power management circuit 100 because the capacitance required to reduce voltage spikes is typically too large to be fabricated inside the chip without consuming a significant amount of chip area. However, because of the input capacitor C IN Is located externally with respect to the power management circuit 100 so it cannot be tightly connected to the power MOSFET devices HS and LS. Thus, the capacitor C will be input IN And significant stray (i.e., parasitic) inductance L is introduced in series between the power MOSFET devices HS and LS STRAY And resistance R STRAY . Such stray impedance (L STRAY And R is STRAY ) Will cause the switch node to ring, which is undesirable.
Fig. 2 is a cross-sectional view illustrating at least a portion of an exemplary semiconductor structure 200 including at least one MOSFET device integrated with a single back-side capacitor in accordance with one or more embodiments of the present utility model. In one or more embodiments, the MOSFET devices and the integrated capacitors are formed using lateral MOS technology. Referring to fig. 2, a structure 200 includes a substrate 202 having an active layer 204, wherein one or more MOSFET devices are formed near an upper surface of the substrate. The structure 200 also includes an integrated capacitor 206 disposed on the backside of 202.
Integrating the input capacitor with the power device in this manner advantageously eliminates the need for an external input capacitor, thereby eliminating (or at least reducing) parasitic inductance and resistance between the input capacitor and the power device, thereby providing a more stable input voltage and yielding better voltage spike suppression effects, among other benefits. The integrated capacitor can be manufactured using a simple growth process and is therefore well suited for integration using standard lateral MOS technology. In addition, since the input capacitor is formed on the back surface of the substrate, it does not consume a large amount of additional chip area.
In the illustrative embodiment, the capacitor 206 includes a first conductive layer 208 formed on the back side of the substrate 202, a dielectric layer 210 formed on a surface of the first conductive layer opposite the back side of the substrate, and a second conductive layer 212 formed on a surface of the dielectric layer opposite the first conductive layer. The first and second conductive layers 208, 212 are preferably formed of a metal (e.g., aluminum, titanium, or TiN), although embodiments of the utility model are not limited to any particular conductive material. Further, in some embodiments, the first and second conductive layers 208, 212 may be formed of different materials. Dielectric layer 210 is configured to electrically isolate the first and second conductive layers from each other, preferably formed of an oxide (e.g., silicon dioxide, etc.) or silicon nitride or other dielectric/insulating material having a higher dielectric constant, although embodiments of the utility model are not limited to any particular insulating material.
Fig. 3 is a flow diagram schematically illustrating at least a portion of an exemplary method 300 for fabricating a semiconductor structure including at least one MOSFET device and a back-side integrated input capacitor, in accordance with one or more embodiments of the present utility model. Fig. 4A-4D are cross-sectional views illustrating intermediate steps of at least a portion of the illustrative manufacturing method 300 shown in fig. 3, in accordance with one or more embodiments of the present utility model.
Referring now to fig. 3, method 300 begins at step 302 by performing a particular initial process (e.g., photolithography, etching, deposition, etc.) on an upper surface of a semiconductor substrate 404, such as shown in fig. 4A, that is typically used to form an active layer, such as active layer 402 shown in fig. 4A. At least one MOSFET device is fabricated in step 304, and more preferably high-side and low-side MOSFET devices for power management circuits (e.g., 100 shown in fig. 1) or similar applications are fabricated.
In step 306, the wafer is flipped so that the active layer 402 is disposed downward and the backside of the substrate 404 is disposed upward as shown in fig. 4B. In step 308, a first conductive layer, such as conductive layer 406 shown in fig. 4B, is formed on the back side of the substrate (404 in fig. 4B). In one or more embodiments, the first conductive layer (406 in fig. 4B) can be formed using standard deposition processes (e.g., metal vapor deposition, silicidation process, etc.). In some embodiments, the first conductive layer 406 may be formed on the back side of the substrate 404 by doping impurities having a prescribed doping concentration (e.g., using ion implantation, etc.), such that at least a surface of the substrate proximate to the back side has a low resistivity (e.g., 0.001 to 10 ohm-cm). In step 310, an insulating layer, such as insulating layer 408 shown in fig. 4C, is formed on the upper surface of first conductive layer 406. Insulating layer 408 may comprise an oxide or other dielectric material, preferably formed using a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process, or the like.
In step 312, a second conductive layer, such as conductive layer 410 shown in fig. 4D, is formed on the upper surface of insulating layer 408. The second conductive layer may be formed using a process consistent with the process of forming the first conductive layer (e.g., metal deposition), although embodiments of the utility model are not limited to any particular process or material for forming the second conductive layer. As previously described, the first and second conductive layers may be formed of different materials, and thus, in one or more embodiments, the process for forming the first and second conductive layers may also be different. The method 300 of fabrication ends at step 314, which may include back end of line (BEOL) processing to form an electrical connection with the integrated capacitor.
The cross-sectional views of fig. 5 through 7 illustrate some ways in which an exemplary single integrated capacitor may be formed according to embodiments of the present utility model, by way of example only and not limitation. As will be appreciated by those skilled in the art in light of the teachings herein, there are various other ways in which capacitors may be integrated with MOS structures, which are also within the scope of the present utility model.
Fig. 5 is a cross-sectional view illustrating at least a portion of an exemplary semiconductor structure 500 in accordance with one or more embodiments, the exemplary semiconductor structure 500 including a single back side capacitor integrated with a MOS structure. The semiconductor structure 500 includes a semiconductor structure 502, such as doped silicon, having an active layer 504 in which one or more MOSFET devices are formed near the upper surface of the substrate. During fabrication, the semiconductor structure 500 is flipped over and an integrated capacitor is formed on the back side of the substrate 502, opposite the active layer 504. In the illustrative semiconductor structure 500, the integrated capacitor includes a first conductive layer 506, which in this embodiment is formed as part of the back side of the substrate 502. In forming the first conductive layer 506, at least a portion of the back surface of the substrate 502 is doped with an n-type or p-type impurity at a prescribed doping concentration level, thereby reducing the resistivity of the back surface portion of the substrate. This reduces the deposition steps required to form the first conductive layer using a different material (e.g. metal) than the substrate.
The integrated capacitor further includes an insulating layer 508 formed on the upper surface of the first conductive layer 506. As previously described, in one or more embodiments, the insulating layer 508 may be formed using a thermal oxidation or deposition process. A second conductive layer 510 is formed on at least a portion of the upper surface of the insulating layer 508. In this embodiment, the second conductive layer 510 preferably includes a metal, and may be formed using deposition or the like. In one or more embodiments, the second conductive layer 510 may be formed during BEOL processing of the structure 500.
Fig. 6 illustrates an exemplary embodiment of a single integrated capacitor including first and second conductive layers formed of different metals in accordance with one or more embodiments of the present utility model. In particular, referring to fig. 6, the semiconductor structure 600 includes a first conductive layer 602 disposed on the backside of the substrate 502 opposite the active layer 504. In this embodiment, the first conductive layer 602 comprises a first metal material, which may be formed on the backside of at least a portion of the substrate 502 using a deposition process (e.g., metal deposition). An insulating layer 604 is then formed over at least a portion of the upper surface of the first conductive layer 602. Similar to the insulating layer 508 shown in fig. 5, the insulating layer 604 can be formed using, for example, a thermal oxidation or deposition process. A second conductive layer 606 is disposed on at least a portion of the upper surface of the insulating layer 604, the second conductive layer 606 comprising a second metallic material in this embodiment. The second metal material used in the second conductive layer 606 may be the same as or different from the first metal material forming the first conductive layer 602. In one or more embodiments, the first and second conductive layers 602, 606 may be formed during BEOL processing of the structure 600.
Fig. 7 is a cross-sectional view illustrating an exemplary structure 700 including a single integrated capacitor formed between two stacked semiconductor structures in accordance with one or more embodiments of the present utility model. Referring to fig. 7, a structure 700 includes a first substrate 502 having a first active layer 504, wherein one or more MOSFET devices are formed near an upper surface of the first substrate. As shown, the first substrate is preferably flipped over so that the back side of the first substrate faces upward.
Similar to the exemplary integrated capacitor embodiment shown in fig. 5, the first conductive layer 506 is formed as a first plate of the integrated capacitor on a portion of the back side of the first substrate 502, for example, by using a conductive material having a predetermined doping concentration level (e.g., 1 x 10 15 Up to 1X 10 19 cm -3 ) At least a portion of the back side of first substrate 502 is doped with an n-type or p-type impurity. Ion implantation or similar processes may be used to dope the backside of the substrate 502. An insulating layer 508 including an oxide (e.g., silicon dioxide) may be formed over at least a portion of the upper surface of the first conductive layer 506, for example, by using a thermal oxidation or deposition process in a manner similar to the formation of insulating layers 508 and 604 shown in fig. 5 and 6, respectively.
The structure 700 further includes a second substrate 702 disposed on an upper surface of at least a portion of the insulating layer 508. The second substrate 702 is similar to the first substrate 502 and includes a second active layer 704, wherein one or more MOSFET devices are formed near an upper surface of the second substrate. At least a portion of the backside of the second substrate 702 is disposed on the upper surface of the insulating layer 508 and forms a second conductive layer 706 that serves as a second plate of the integrated capacitor.
In one or more embodiments, the first and second substrates 502, 702 are part of first and second semiconductor die (semiconductor dies) that are stacked such that their back sides face each other and are separated by an insulating layer 508 sandwiched therebetween. For example, the first die may contain power MOSFET devices fabricated using DMOS technology and the second die may include drive circuitry fabricated using low voltage CMOS technology. The area between the two stacked dies formed in this manner is advantageously used to build an integrated capacitor without consuming additional chip area. The insulating layer may include an epoxy or adhesive film or other standard die attach material. In this regard, in one or more embodiments, the second die is formed separately from the first die and stacked together during the packaging process.
Although a single integrated capacitor of various exemplary embodiments has been described in connection with fig. 5-7 in accordance with one or more embodiments of the utility model, these same steps may be extended to form multiple integrated capacitors. By way of example only and not limitation, the cross-sectional view of fig. 8 illustrates at least a portion of an exemplary semiconductor structure 800 including at least one MOSFET device integrated with a plurality of back-side capacitors in accordance with one or more embodiments of the present utility model. In one or more embodiments, the MOSFET devices and integrated capacitors are preferably formed using lateral MOS technology in a manner consistent with the semiconductor structure 200 shown in fig. 2.
Referring now to fig. 8, a semiconductor structure 800 includes a substrate 802 having an active layer 804 in which one or more MOSFET devices are formed near an upper surface of the substrate. The structure 800 also includes a plurality of integrated capacitors formed using alternating conductive and insulating layers disposed on the backside of the substrate 802. Specifically, a first conductive layer 806 is formed on at least a portion of the back surface of the substrate 802, for example, by using a deposition process or the like.
A first insulating layer 808 is formed over an upper surface (i.e., a surface opposite the substrate) of the first conductive layer 806, for example, by using thermal oxidation, CVD, PVD deposition, or the like. The first insulating layer 808 preferably has a lateral width that is less than the first conductive layer 806 to allow one or more conductive terminals (e.g., metal) to be formed for connecting the first conductive layer to a first bias source (bias 1).
Similarly, a second conductive layer 810 may be formed on at least a portion of the upper surface of the first insulating layer 808. Then, a second insulating layer 812 is formed on the upper surface of the second conductive layer 810, for example, by using thermal oxidation, deposition, or the like. The second insulating layer 812 preferably has a lateral width that is less than the second conductive layer 810 to allow formation of one or more conductive terminals for electrically connecting the second conductive layer to a second bias source (bias 2). The third conductive layer 814 is preferably formed on at least a portion of the upper surface of the second insulating layer 812 in a manner consistent with the formation of the first and second conductive layers 806, 810. One or more conductive terminals formed on the upper surface of the third conductive layer 814 provide electrical connection to a third bias source (bias 3).
The same method is generalized to a plurality of integrated capacitors comprising N conductive layers, where N is an integer, with an (N-1) th insulating layer 816 formed on the upper surface of the (N-1) th conductive layer (not explicitly shown, but implied). As with the other insulating layers 808, 812 in the semiconductor structure 800, the (N-1) th insulating layer 816 preferably has a lateral width that is less than the (N-1) th conductive layer, thereby being arranged to allow formation of one or more conductive terminals for electrically connecting the (N-1) th conductive layer to a corresponding (N-1) th bias source. An nth conductive layer 818 is then formed on at least a portion of the upper surface of the (N-1) th insulating layer 816. One or more conductive terminals are formed on the upper surface of the nth conductive layer 818 for electrically connecting the nth conductive layer 818 to an nth bias source (bias N).
The first conductive layer 806 forms a first plate of the first integrated capacitor. The second plate of the first integrated capacitor and the first plate of the second integrated capacitor are shared by a common second conductive layer 810. Likewise, the second plate of the second integrated capacitor and the first plate of the third integrated capacitor are shared by the common third conductive layer 814, and so on. As shown, each layer of the capacitor may be connected to a separate bias source. Alternatively, two or more multilayer capacitors may be connected together in parallel to form a larger capacitor. For example, in one or more embodiments, bias 1, bias 3, and bias N may be connected to VDD, bias 2, bias 4, and bias (N-1) may be connected to ground.
Each of the insulating layers 808, 812, 816 in the semiconductor structure 800 preferably comprises an oxide (e.g., silicon dioxide) or other dielectric material (e.g., nitride, etc.); the insulating layers may all be formed of the same material, alternatively one or more insulating layers may be formed of different materials. Similarly, each of the conductive layers 806, 810, 814, 818 includes a conductive material such as, but not limited to, metal, polysilicon, doped silicon, and the like. In one or more embodiments, all conductive layers in semiconductor structure 800 are formed of the same material; it will be apparent to those skilled in the art based on the teachings herein that in other embodiments, one or more conductive layers may be formed of different materials.
As previously mentioned, embodiments of the present utility model are well suited for use in system applications, such as DC-DC converters, wherein at least one first die comprising circuitry (e.g., drive circuitry) fabricated using bipolars and/or CMOS technology is integrated with at least one second die comprising one or more power devices and/or circuitry fabricated using DMOS technology. Fig. 9A is a top perspective view and fig. 9B and 9C are cross-sectional views, respectively, illustrating a stacked power management module including at least one integrated capacitor in accordance with one or more embodiments of the present utility model. The power management module 900 includes driver chips that may be fabricated using low voltage bipolars and/or CMOS technology, as well as power level chips (e.g., power MOSFET devices) fabricated using high voltage DMOS technology. The driver chip and the power level chip are configured as a stacked structure disposed on an upper surface of a substrate or interposer (interposer). As shown in fig. 9A, at least one integrated capacitor is formed on the back side of the power stage chip in a manner consistent with the single and multiple integrated capacitors previously described in connection with fig. 5-8.
In one or more embodiments, a portion of the substrate backside (e.g., 902 in fig. 9B) of the power stage chip may be formed as a first plate of an integrated capacitor, e.g., by doping at least a portion of the substrate backside with an n-type or p-type impurity having a predetermined doping concentration level, similar to the integrated capacitor shown in fig. 5. This doped portion of the back side of the power chip substrate forms substantially the first conductive layer 906 shown in fig. 9B. The second conductive layer of the integrated capacitor (e.g., 910 in fig. 9B) preferably comprises a metal. In one or more embodiments, the connection terminal of the first plate of the integrated capacitor shares the same pad (pad) with a corresponding terminal (e.g., GND) of the power stage chip, which is located on a bottom pad of the power stage chip, not explicitly shown in FIGS. 9A-18 (e.g., 1004 in FIG. 10). Alternatively, it is contemplated that the first plate of the integrated capacitor may be connected to other terminals, such as a bootstrap capacitor. The pad labeled "capacitor pin" is a terminal for providing an electrical connection to a second plate of the integrated capacitor (e.g., second conductive layer 910 in fig. 9B).
Fig. 9B illustrates an exemplary embodiment in accordance with one or more embodiments of the utility model, wherein a driving chip without an integrated capacitor is arranged on a power stage chip with an integrated capacitor. Referring to fig. 9B, the power-level chip in the power management module 900 includes a substrate 902 (e.g., silicon, germanium, gallium arsenide, etc.) having an active layer 904, wherein one or more power MOSFET devices (e.g., laterally Diffused MOS (LDMOS) devices) are formed near an upper surface of the substrate. During fabrication, the power level chip is inverted (i.e., active layer 904 is facing downward) and at least one integrated capacitor is formed on the back side of substrate 902 opposite active layer 904.
In the exemplary power management module 900, the integrated capacitor includes a first conductive layer 906 formed on at least a portion of the backside of the substrate 902. In one or more embodiments, the first conductive layer 906 includes a metal formed using a metal deposition or the like process; in other embodiments, the first conductive layer 906 is formed from a portion of the backside of the substrate 902, such as by doping the backside of the substrate with an n-type or p-type impurity having a prescribed doping concentration level and depth to reduce the resistivity of the backside portion of the substrate. The integrated capacitor further includes an insulating layer 908 formed on the upper surface of the first conductive layer 906. In one or more embodiments, the insulating layer 908 includes an oxide, which may be formed using a thermal oxidation or deposition process. A second conductive layer 910 is formed on at least a portion of the upper surface of the insulating layer 908. In one or more embodiments, the second conductive layer 910 includes a metal that may be formed using deposition or similar processes. The first and second conductive layers may comprise the same material (e.g., metal) or, in some embodiments, may be formed of different materials (e.g., metal and polysilicon). Although a single integrated capacitor is shown in fig. 9B, it should be understood that multiple integrated capacitors may be similarly employed (e.g., consistent with the exemplary multiple integrated capacitors shown in fig. 8).
With continued reference to fig. 9B, the driver chip in the power management module 900 includes a substrate 922 (e.g., silicon, germanium, gallium arsenide, etc.) having an active layer 924, wherein one or more bipolars and/or CMOS devices and/or circuits are formed near an upper surface of the substrate 922. After completion of the fabrication, in this illustrative embodiment, the power stage chip and the driving chip are stacked with their respective back surfaces facing each other, and the integrated capacitor is disposed between the stacked power stage chip and driving chip. More specifically, the back surface of the substrate 922 of the driving chip is preferably attached to the upper surface of the second conductive layer 910. The connection of the driver chip and the power level chip may be made using a die attach layer 926 (e.g., epoxy, etc.) or the like.
It should be appreciated that in one or more alternative embodiments, an integrated capacitor may be formed on the back side of the driver chip prior to connection to the power stage chip. In this case, the structure including the driving chip and the integrated capacitor may be inverted such that the front side (i.e., upper) conductive layer of the capacitor is connected to the rear side of the power stage chip through the chip attach layer 926. That is, the integrated capacitor need not be formed first on the back side of the power chip.
Fig. 9C illustrates an exemplary power management module 950 in accordance with one or more embodiments of the utility model in which a driver chip having a second integrated capacitor is disposed on a power stage chip having a first integrated capacitor. Consistent with the exemplary integrated capacitor embodiment shown in fig. 9B, the power stage chip in the power management module 950 includes a substrate 902 having an active layer 904, wherein one or more power MOSFET devices are formed near the upper surface of the substrate. The power level chip is flipped over and at least one integrated capacitor is formed on the back side of the substrate 902 opposite the active layer 904 using the same or similar fabrication process.
The structure in each of the first and second integrated capacitors preferably corresponds to the integrated capacitor shown in fig. 9B. In the exemplary power management module 950, the first integrated capacitor includes a first conductive layer 906 formed on at least a portion of the backside of the substrate 902, an insulating layer 908 formed on a surface of the first conductive layer 906, and a second conductive layer 910 formed on at least a portion of an upper surface of the insulating layer 908.
With continued reference to fig. 9C, the driver chip in the power management module 950 includes a substrate 922 (e.g., silicon, germanium, gallium arsenide, etc.) having an active layer 924, wherein one or more bipolars and/or CMOS devices and/or circuits are formed near an upper surface of the substrate 922. After the completion of the fabrication, in this exemplary embodiment, the power stage chip and the driving chip are stacked with their respective back surfaces facing each other, and the first and second integrated capacitors are disposed between the stacked power stage chip and driving chip.
The second integrated capacitor associated with the drive chip includes a first conductive layer 952 formed on at least a portion of the back side of the substrate 922, an insulating layer 954 formed on an upper surface of the first conductive layer 952, and a second conductive layer 956 formed on at least a portion of the upper surface of the insulating layer 954 in a manner consistent with the layers 906, 908, and 910, respectively, of the first integrated capacitor associated with the power level chip.
The driver chip and the power stage chip and their corresponding integrated capacitors are stacked together to form a power module 950. More specifically, the front side of the second conductive layer 956 of the second integrated capacitor disposed on the back side of the substrate 922 of the driver chip is preferably attached to the front side of the second conductive layer 910 of the first integrated capacitor of the power stage chip. In one or more embodiments, as shown, the driver chip and the power stage chip may be connected using a die attach layer 926 (e.g., epoxy, etc.) or similar means disposed between the front side surfaces of the first and second integrated capacitors.
Electrical connection between the driver chip and devices and/or circuits on the power level chip may be accomplished using several contemplated methods, including Through Silicon Vias (TSVs), bond wires, solder bump/controlled collapse chip connection (C4) connections, etc., as will be described in further detail in connection with the exemplary embodiments shown in fig. 10-18. Furthermore, as will be described in further detail below, in one or more other embodiments, the driver chip and the power stage chip are not necessarily connected with their respective back surfaces facing each other.
10-18 depict at least a portion of an exemplary power management module in various orientations and connection arrangements of a driver chip and a power chip, in accordance with an exemplary embodiment of the present utility model; fig. 10-14 depict exemplary orientations of the power chip, the integrated capacitor, and the driver chip, and fig. 15-18 depict exemplary connection arrangements between the integrated capacitor, the power chip, and the driver chip and a carrier (e.g., interposer) or other substrate. The orientation and connection arrangement shown in fig. 10-18 is by way of example only and not by way of limitation. Other arrangements of the power management module not explicitly shown herein may be envisaged in a similar manner and are within the scope of the utility model, as will become apparent to those skilled in the art in view of the teachings herein.
Referring now to the top perspective view of fig. 10, at least a portion of an exemplary power management module 1000 is shown in accordance with one or more embodiments of the present disclosure. The power management module 1000 includes a driver chip (which may be fabricated using bipolars and/or CMOS technology), a power stage chip (which may be fabricated using DMOS technology), and an integrated capacitor disposed between the driver chip and the power stage chip. In this embodiment, the power management module 1000 includes a carrier (e.g., interposer) or substrate 1002, which may be formed of a rigid material (e.g., silicon, etc.) having a plurality of conductive pads 1004 disposed on an upper surface of the substrate. The power stage chip is oriented downward such that connection structures (e.g., solder bumps, etc.) formed on the front side of the power stage chip (not explicitly shown but implied) are aligned with corresponding pads 1004 formed on the substrate 1002 to provide electrical connection with devices and/or circuits formed in the active layer of the power stage chip, proximate the front side of the power stage chip.
An integrated capacitor is disposed on at least a portion of the back side of the power stage chip. The integrated capacitor may be formed in a manner consistent with the integrated capacitors described above, for example as shown in fig. 9A and 9B. Conductive pads 1004 disposed on the upper surface of the substrate and conductive pads 1008 formed on the back side of the power chip each provide electrical connection to the first and second conductive layers of the integrated capacitor.
In this exemplary embodiment, the driver chip in the power management module 1000 is oriented downward such that connection structures (e.g., solder bumps, etc.) formed on the front side of the driver chip (not explicitly shown but implied) are aligned with corresponding conductive pads 1006 formed on the back side of the power level chip, which may be used to provide electrical connection to the driver chip (e.g., between the driver chip and the power level chip and/or between the driver chip and the integrated capacitor), for example, through the use of solder joints, bond wires, or Through Silicon Vias (TSVs), etc., not explicitly shown in fig. 10. The driver chip may be attached to the power level chip using various known connection means, such as a chip attach layer (e.g., epoxy, solder, etc.).
Fig. 11 is a top perspective view of at least a portion of an exemplary power management module 1100 in accordance with one or more alternative embodiments of the utility model. Similar to the exemplary power management module 1000 shown in fig. 10, the power management module 1100 includes a driver chip (which may be fabricated using bipolars and/or CMOS technology), a power stage chip (which may be fabricated using DMOS technology), and an integrated capacitor disposed between the driver chip and the power stage chip. In this embodiment, the power management module 1100 includes a carrier or substrate 1102, which may be formed from a multi-layer PCB or laminate (e.g., silicon, etc.) having a plurality of conductive pads 1104 disposed on an upper surface of the substrate. It should be appreciated that the substrate 1102 may include an electrical PCB, an interposer for TSVs, or other materials that may be used to make electrical connection between the power stage chip and the driver chip, in accordance with an embodiment of the present utility model. The power chip is oriented downward such that connection structures (e.g., solder bumps, etc.) formed on the front side of the power chip (not explicitly shown, but implicitly) are aligned with corresponding pads 1104 formed on the substrate 1102 to provide electrical connection to devices and/or circuits in an active layer formed near the upper surface of the power chip.
An integrated capacitor is disposed on at least a portion of the back side of the power stage chip. The integrated capacitor may be formed in a manner consistent with the integrated capacitors described above, for example as shown in fig. 9A and 9B. Conductive pads 1106 formed on the back side of the power chip provide electrical connection to the top conductive layer of the integrated capacitor. In this embodiment, the top conductive layer of the integrated capacitor does not completely cover the back side of the power stage chip, but is formed in an L-shaped structure, leaving a region 1108 at the back side of the power stage chip in which the driving chip is disposed without the integrated capacitor.
In this embodiment, the driver chip is oriented upward and disposed on the back side of the power stage chip in region 1108 such that the back side of the driver chip and the back side of the power stage chip face each other. The driver chip may be connected to the power level chip using various known connection means, such as a chip attach layer (e.g., epoxy, solder, etc.). The conductive pads 1110 formed on the upper surface of the driver chip provide electrical connection with devices and/or circuits formed in the active layer of the driver chip (e.g., between the driver chip and the power level chip and/or between the driver chip and the integrated capacitor), such as by using solder joints, bond wires, TSVs, etc., not explicitly shown in fig. 11.
Fig. 12 is a top perspective view of at least a portion of an exemplary power management module 1200 in accordance with one or more alternative embodiments of the utility model. The power management module 1200 includes a driver chip (which may be fabricated using bipolars and/or CMOS technology), a power stage chip (which may be fabricated using DMOS technology), and an integrated capacitor disposed between the driver chip and the power stage chip. In this embodiment, the power management module 1200 includes a carrier or substrate 1202, which may be formed of a rigid material (e.g., silicon, etc.) having a plurality of conductive pads 1204 formed on an upper surface of the substrate. In this exemplary embodiment, the power chip is oriented downward so that connection structures (e.g., pads, etc.) formed on the front side of the power chip (not explicitly shown, but implicitly) are aligned with corresponding pads 1204 formed on the substrate 1202 to provide electrical connection with devices and/or circuits in the active layer formed near the front side of the power chip.
The integrated capacitor may be formed in a similar manner as the integrated capacitor described above, for example as shown in fig. 9A and 9B. Conductive pads 1206 formed on the back side of the power chip provide electrical connection to the top conductive layer of the integrated capacitor. In this regard, the arrangement of the power management module 1200 is similar to the exemplary power management module 1000 shown in fig. 10, except that the integrated capacitors in the power management module 1200 are not formed on the entire back side of the power stage chip. Instead, the top conductive layer of the integrated capacitor is formed in an L-shaped structure, leaving a region 1208 on the back side of the power stage chip in which the driver chip is disposed without the integrated capacitor.
In this embodiment, the driver chip is directed downward and disposed on the back side of the power stage chip in region 1208 such that the front side of the driver chip is facing the back side of the power stage chip. Connection structures (e.g., bond pads, etc.) formed on the front side of the driver chip (not explicitly shown but implied) are preferably aligned with corresponding conductive pads 1210 formed on the back side of the power chip for providing electrical connection to the driver chip (e.g., between the driver chip and the power chip and/or between the driver chip and the integrated capacitor), for example, by using bond pads, bond wires, TSVs, etc. not explicitly shown in fig. 12. The driver chip may be attached to the power level chip using various known connection means, for example, by a chip attach layer (e.g., epoxy, solder, etc.).
Fig. 13 is a top perspective view of at least a portion of an exemplary power management module 1300 in accordance with one or more alternative embodiments of the present utility model. The power management module 1300 includes a driver chip (which may be fabricated using bipolars and/or CMOS technology), a power chip (which may be fabricated using DMOS technology), and an integrated capacitor disposed between the driver chip and the power chip. In this embodiment, the power management module 1300 includes a carrier or substrate 1302, which may be formed of a rigid material (e.g., silicon, etc.) having a plurality of conductive pads 1304 disposed on an upper surface of the substrate. The power chip is oriented downward such that connection structures (e.g., solder bumps, etc.) formed on the front side of the power chip (not explicitly shown but implied) are aligned with corresponding pads 1304 formed on the substrate 1302 for providing electrical connection to devices and/or circuits formed in the active layer near the front side of the power chip.
An integrated capacitor is disposed on at least a portion of the back side of the power stage chip. The integrated capacitor may be formed in a manner consistent with the integrated capacitors described above, for example as shown in fig. 9A and 9B. Conductive pads 1306 formed on the back side of the power chip provide electrical connection to the top conductive layer of the integrated capacitor. In this embodiment, the top conductive layer of the integrated capacitor does not completely cover the back side of the power stage chip, but rather is formed as a circular ring structure surrounding the area 1308 on the back side of the power stage chip where the driver chip is arranged without the integrated capacitor.
In this embodiment, the driver chip is oriented upward and disposed on the back side of the power stage chip in region 1308 such that the back side of the driver chip and the back side of the power stage chip face each other. In this exemplary embodiment, the integrated capacitor completely encloses the driver chip. The driver chip may be attached to the power level chip using various known connection means, such as a chip attach layer (e.g., epoxy, solder, etc.). Conductive pads 1310 formed on the front side of the driver chip provide electrical connection to devices and/or circuits formed in the active layer of the driver chip (e.g., between the driver chip and the power level chip and/or between the driver chip and the integrated capacitor), such as by using solder bumps, bond wires, TSVs, etc., not explicitly shown in fig. 13.
Fig. 14 is a top perspective view of at least a portion of an exemplary power management module 1400 in accordance with one or more alternative embodiments of the utility model. The power management module 1400 includes a driver chip (which may be fabricated using bipolars and/or CMOS technology), a power chip (which may be fabricated using DMOS technology), and an integrated capacitor disposed between the driver chip and the power chip. In this embodiment, the power management module 1400 includes a carrier or substrate 1402, which may be formed of a rigid material (e.g., silicon, etc.) having a plurality of conductive pads 1404 disposed on an upper surface of the substrate. The power chip is oriented downward such that connection structures (e.g., solder bumps, etc.) formed on the front side of the power chip (not explicitly shown but implied) are aligned with corresponding pads 1404 formed on the substrate 1402 for providing electrical connection to devices and/or circuits formed in the active layer of the power chip that are proximate to the front side of the power chip.
The integrated capacitors in the power management module 1400 are disposed on at least a portion of the back side of the power chip. The integrated capacitor may be formed in a manner consistent with the integrated capacitor shown in fig. 9A and 9B. Conductive pads 1306 formed on the back side of the power chip provide electrical connection to the top conductive layer of the integrated capacitor. In this embodiment, as with the integrated capacitor in the exemplary power management module 1300 shown in fig. 13, the top conductive layer of the integrated capacitor does not completely cover the back side of the power stage chip, but is formed as a ring structure surrounding the area 1408 on the back side of the power stage chip where the driver chip is disposed without the integrated capacitor.
In the exemplary power management module 1400, the driver chips are oriented downward and are arranged on the back side of the power chips in region 1408 such that the front side of the driver chips are facing the back side of the power chips. Connection structures (e.g., bond pads, etc.) formed on the front side of the driver chip (not explicitly shown but implied) are preferably aligned with corresponding conductive pads 1410 formed on the back side of the power level chip for providing electrical connection to the driver chip (e.g., between the driver chip and the power level chip and/or between the driver chip and the integrated capacitor), for example, by using bond pads, bond wires, TSVs, etc., not explicitly shown in fig. 14. The driver chip may be attached to the power level chip using various known connection means, such as a chip attach layer (e.g., epoxy, solder, etc.).
Fig. 15 is a top perspective view of at least a portion of a power management module 1500 showing an exemplary connection arrangement between a power chip, a driver chip, and an integrated capacitor in accordance with one or more embodiments of the present utility model. The power management module 1500 may be manufactured in a manner consistent with the exemplary power management module 900 shown in fig. 9A.
In particular, the power management module 1500 includes a carrier or substrate 1502 that can be formed of a rigid material (e.g., silicon, etc.) that includes a plurality of conductive pads 1504 disposed on an upper surface of the substrate. In this embodiment, the power chip is oriented downward such that connection structures (e.g., solder bumps, etc.) formed on the upper surface (not explicitly shown but implied) of the power chip are aligned with corresponding pads 1504 on the substrate 1502 to provide electrical connection to devices and/or circuits formed in the active layer of the power chip that are proximate to the upper surface of the power chip.
The integrated capacitors in the power management module 1500 are disposed on at least a portion of the back side of the power chip. The integrated capacitor may be formed in a manner consistent with the integrated capacitor shown in fig. 9A and 9B. The conductive pads 1506 formed on the back side of the power chip provide electrical connection to the top conductive layer of the integrated capacitor. In this embodiment, similar to the integrated capacitors in the exemplary power management module 900 shown in fig. 9A, the top conductive layer of the integrated capacitors completely covers the back side of the power stage chip, although in other embodiments, the integrated capacitors may be formed on only a portion of the back side of the power stage chip, resulting in an area on the back side of the power stage chip that is free of integrated capacitors (e.g., as shown in fig. 11-14).
In one or more embodiments, as shown in fig. 15, the driver chip faces upward and is arranged on the back side of the power stage chip such that the back side of the driver chip and the back side of the power stage chip face each other. The driver chip may be connected to the power level chip using various known connection means, such as a chip attach layer (e.g., epoxy, solder, etc.). The conductive pads 1508 formed on the upper surface of the driver chip provide electrical connections on the upper surface of the driver chip with devices and/or circuits formed in the active layer of the driver chip, between the driver chip and the power stage chip, and/or between the driver chip and the integrated capacitor, which may be formed using one or more TSVs 1510 formed through the substrate of the driver chip.
TSVs (e.g., 1510) are very important for many heterogeneous integrated (heterogeneous integration, i.e., HI) system enabling technologies, which have recently found widespread use in, for example, biomedical, optoelectronic, photonic, display technologies, and microelectromechanical systems (MEMS) because of the need for three-dimensional (3D) chip stacking in advanced microelectronic packaging approaches. TSVs allow direct signal vertical routing between chips rather than routing to the periphery and wire bonding to an interposer or printed circuit board. Such vertical routing may reduce signal path length, improving high frequency performance by reducing parasitic impedance and corresponding resistance-capacitance (RC) delay, among other benefits. Besides electrical improvements, TSVs can also provide more inputs and outputs, as they can be arranged over the entire area of the chip, rather than just using the periphery of the chip.
Similarly, one or more TSVs 1512 formed through the substrate of the power chip provide electrical connections between devices and/or circuits formed in the active layers of the power chip and the driver chip, and/or between the power chip and the integrated capacitor. The TSVs 1510, 1512 advantageously eliminate the need for bond wires or other connection means.
Fig. 16 is a top perspective view of at least a portion of a power management module 1600 of an exemplary connection arrangement between a power chip, a driver chip, and an integrated capacitor in accordance with one or more embodiments of the present utility model. The power management module 1600 may be manufactured in a similar manner as the illustrative power management module 1500 shown in fig. 15, except that the TSVs 1510, 1512 are replaced with bond wires.
More specifically, referring to fig. 16, a power management module 1600 includes a carrier or substrate 1602, preferably formed of a rigid material (e.g., silicon, etc.), having a plurality of conductive pads 1604 disposed on an upper surface of the substrate. In this embodiment, the power chip is oriented downward such that connection structures (e.g., solder bumps, etc.) formed on the upper surface (not explicitly shown but implied) of the power chip are aligned with corresponding pads 1604 on the substrate 1602 to provide electrical connection to devices and/or circuits formed in the active layer of the power chip, proximate the upper surface.
The integrated capacitors in the power management module 1600 are disposed on at least a portion of the back side of the power chip. The integrated capacitor may be formed in a manner consistent with the integrated capacitor shown in fig. 9A and 9B. Conductive pads 1606 formed on the back side of the power chip provide electrical connection to the top conductive layer of the integrated capacitor. In this embodiment, similar to the integrated capacitors in the illustrative power management module 1500 shown in fig. 15, the top conductive layer of the integrated capacitors covers the entire back side of the power stage chip, although in other embodiments, the integrated capacitors may be formed on only a portion of the back side of the power stage chip, such that there is an area on the back side of the power stage chip where the integrated capacitors are not.
In the exemplary embodiment shown in fig. 16, the driving chips face upward and are arranged on the back side of the power stage chip in a stacked manner such that the back side of the driving chips and the back side of the power stage chip face each other. The driver chip may be connected to the power level chip using various known connection means, such as a chip attach layer (e.g., epoxy, solder, etc.). One or more conductive pads 1608 formed on the upper surface of the driver chip provide electrical connection on the upper surface of the driver chip to devices and/or circuits formed in the active layer of the driver chip.
One or more connection lines 1610 connect the conductive pads 1606 of the integrated capacitor with corresponding conductive pads 1604 on the substrate 1602, or connect the conductive pads 1608 of the driver chip with corresponding conductive pads 1604, thereby providing electrical connection between the integrated capacitor and the power chip or between the driver chip and the power chip, respectively.
Fig. 17 is a top perspective view of at least a portion of a power management module 1700 of an exemplary connection arrangement between a power chip, a driver chip, and an integrated capacitor in accordance with one or more embodiments of the utility model. The power management module 1700 may be manufactured in a manner consistent with the illustrative power management module 1000 shown in fig. 10.
Referring to fig. 17, the power management module 1700 includes a carrier or substrate 1702, which carrier or substrate 1702 is preferably formed of a rigid material (e.g., silicon, etc.) that contains a plurality of conductive pads 1704 disposed on an upper surface thereof. In this embodiment, the power level chip is face down such that connection structures (e.g., solder bumps, etc.) formed on the upper surface (not explicitly shown but implied) of the power level chip are aligned with corresponding pads 1704 on the substrate 1702 to provide electrical connection to devices and/or circuits formed in the active layer of the power level chip, proximate to its upper surface.
The integrated capacitors in the power management module 1700, similar to the integrated capacitors in the power management module 1600 shown in fig. 16, are disposed on at least a portion of the back side of the power chip. The integrated capacitor may be formed in a manner consistent with the integrated capacitor shown in fig. 9A and 9B. The conductive pads 1706 formed on the back side of the power stage chip provide electrical connection to the top conductive layer of the integrated capacitor. In this embodiment, the top conductive layer of the integrated capacitor covers the entire back surface of the power stage chip, similar to the integrated capacitor in the illustrative power management module 1500 shown in fig. 15, although in other embodiments the integrated capacitor may be formed on only a portion of the back surface of the power stage chip.
The driver chips in the power management module 1700 are facing downward and are disposed on the back side of the power chips in a stacked arrangement such that the upper portions of the driver chips face the back side of the power chips. Connection structures (e.g., pads, etc.) formed on the upper surface of the driver chip (not explicitly shown but implied) are preferably aligned with corresponding conductive pads 1708 formed on the back side of the power chip for providing electrical connection to the driver chip (e.g., between the driver chip and the power chip and/or between the driver chip and the integrated capacitor). The driver chip may be connected to the power level chip using various known connection means, such as a chip connection layer (e.g., epoxy, solder, etc.).
The electrical connections between the power chip and the integrated capacitor, and between the power chip and the driver chip, are provided through one or more TSVs 1710 formed by the substrate of the power chip. Each TSV 1710 is aligned with a corresponding conductive pad 1704 and 1708 formed on the back side of the substrate 1702 and the power chip, respectively.
Fig. 18 is a top perspective view of at least a portion of a power management module 1800 illustrating an exemplary connection arrangement between a power chip, a driver chip, and an integrated capacitor in accordance with one or more embodiments of the present utility model. The power management module 1800 may be manufactured in a manner consistent with the illustrative power management module 1700 shown in fig. 17, except that the TSVs 1710 are replaced with bond wires.
In particular, referring to fig. 18, the power management module 1800 includes a carrier or substrate 1802, preferably formed of a rigid material (e.g., silicon, etc.), that contains a plurality of conductive pads 1804 disposed on an upper surface thereof. The power stage chip faces downward such that connection structures (e.g., solder bumps, etc.) formed on an upper surface (not explicitly shown but implied) of the power stage chip are aligned with corresponding conductive pads 1804 on the substrate 1802 to provide electrical connection with devices and/or circuits formed in the active layer of the power stage chip, proximate to its upper surface.
The integrated capacitors in the power management module 1800, similar to the integrated capacitors in the power management module 1700 shown in fig. 17, are disposed on at least a portion of the back side of the power chips. The integrated capacitor may be formed in a manner consistent with the integrated capacitor shown in fig. 9A and 9B. Conductive pads 1806 formed on the back side of the power chip provide electrical connection to the top conductive layer of the integrated capacitor. In this embodiment, as with the integrated capacitor in the illustrative power management module 1700 shown in FIG. 17, the top conductive layer of the integrated capacitor covers the entire back side of the power chip, although in other embodiments the integrated capacitor may be formed on only a portion of the back side of the power chip.
The driver chips in the power management module 1800 are oriented downward and are disposed on the back side of the power chips in a stacked arrangement such that the upper portions of the driver chips are oriented toward the back side of the power chips. Connection structures (e.g., solder bumps, etc.) formed on the upper surface of the driver chip (not explicitly shown but implied) are preferably aligned with corresponding conductive pads 1808 formed on the back side of the power chip for providing electrical connection to the driver chip (e.g., between the driver chip and the power chip and/or between the driver chip and the integrated capacitor). The driver chip may be connected to the power level chip using various known connection means, such as a die attach layer (e.g., epoxy, solder, etc.).
Unlike the illustrative power management module 1700 shown in FIG. 17, the driver chips in the power management module 1800 of FIG. 18 face downward, eliminating the need for TSVs in the driver chips; instead, electrical connection to devices and/or circuits in the driver chip may be accomplished, for example, using direct chip connection (e.g., flip chip bonding, ball grid array, etc.) or the like. As for the power chips in the power management module 1800, electrical connections between the power chips and the integrated capacitors, and between the power chips and the driver chips, are provided by one or more bond wires 1810. That is, electrical connections between conductive pad 1806 (associated with the integrated capacitor) and the power chip, and between conductive pad 1808 (associated with the driver chip) and the power chip, are provided by respective bond wires 1810.
As previously described in connection with fig. 1, the principles of the present utility model are well suited for use in DC-DC converter applications, as well as other beneficial applications, as illustrated by one or more embodiments of the present utility model. FIG. 19A is a schematic diagram illustrating at least a portion of an exemplary multi-phase power management circuit 1900 in which one or more aspects of the present utility model may be employed. The multiphase power management circuit 1900 includes a plurality of drive circuits including a first drive circuit (driver 1) 1902, a second drive circuit (driver 2) 1904, and an nth drive circuit (driver n) 1906, where n is an integer. Each drive circuit 1902, 1904, 1906 is configured to receive one or more control signals generated by the controller 1908 for driving a respective power MOSFET device coupled to the drive circuit.
More specifically, each drive circuit 1902, 1904, 1906 is configured to generate a bias signal based on at least one control signal generated by the controller 1908To activate the high side MOSFET device HS and/or the low side MOSFET device LS. The first bias signal generated by each of the driver circuits 1902, 1904, 1906 is provided to the gate (G) of the high-side MOSFET device and the second bias signal generated by the driver circuit is provided to the gate of the low-side MOSFET device. In the corresponding drive circuit 1902, 1904, or 1906, the source (S) of the high-side MOSFET device is connected to the drain (D) of the low-side MOSFET device at a switching node SW1, SW2, or SWn, respectively. The drains of the high-side MOSFET devices in each drive circuit 1902, 1904, 1906 are connected to the input voltage terminals V of the respective phases of the multiphase power management circuit 1900 IN The source of the low-side MOSFET device is coupled to a voltage return, preferably Ground (GND).
The drive circuits and corresponding high-side and low-side MOSFET devices form a given phase circuit (1, 2, …, n) of the multi-phase power management circuit 1900. Fig. 19B is a top perspective view of at least a portion of the exemplary multi-phase power management circuit 1900 shown in fig. 19A. Referring to fig. 19B, a first phase circuit (phase-1) 1952 includes a first drive circuit 1902 and corresponding high-side and low-side MOSFET devices, a second phase circuit (phase-2) 1954 includes a second drive circuit 1904 and corresponding high-side and low-side MOSFET devices, and an nth phase circuit (nth phase) 1956 includes an nth drive circuit 1906 and corresponding high-side and low-side MOSFET devices. Each of the phase circuits 1952, 1954, 1956 and the controller 1908 is fabricated as a separate chip.
As shown in fig. 19A and 19B, an external input capacitor C IN1 、C IN2 、C INn Is typically placed at the input voltage terminal V of each phase circuit of the multi-phase power management circuit 1900 IN And ground to reduce voltage spikes at the input voltage terminals of the power management circuit. Each input capacitor C IN1 、C IN2 、C INn Is typically located outside of the power management circuit 1900 because the capacitance required to reduce voltage spikes is typically too large to be fabricated on-chip without consuming a significant amount of chip area. However, due to the input capacitor C associated with each phase circuit 1952, 1954, 1956, respectively IN1 、C IN2 、C INn Located in power managementOutside of circuit 1900, it cannot be tightly connected to power MOSFET devices HS and LS. Thus, in the corresponding input capacitor C IN1 、C IN2 、C INn And the power MOSFET devices HS and LS associated with each phase circuit 1952, 1954, 1956 will introduce a significant amount of stray (i.e., parasitic) inductance L in series between them STRAY And resistance R STRAY . As previously mentioned, this stray impedance (L STRAY And R is STRAY ) Undesirable ringing of the switching node will result.
In one or more embodiments of the utility model, the multi-phase power management circuit may be fabricated as a multi-phase power module on a common die, and the shared input capacitor may be formed by back-side integration, consistent with the formation of the illustrative integrated capacitor described herein in connection with any of fig. 3-18. By way of example only and not limitation, the schematic diagram of fig. 20A illustrates at least a portion of an exemplary multi-phase power management circuit 2000 having a shared integrated input capacitor in accordance with one or more embodiments of the present utility model. Similar to the power management circuit 1900 shown in fig. 19A, the exemplary power management circuit 2000 includes a plurality of drive circuits including a first drive circuit (driver 1) 2002, a second drive circuit (driver 2) 2004, and an nth drive circuit (driver n) 2006, where n is an integer. Each drive circuit 2002, 2004, 2006 is configured to receive one or more control signals generated by a controller 2008 for driving a respective power MOSFET device coupled to the drive circuit.
Specifically, each drive circuit 2002, 2004, 2006 is configured to generate a bias signal for activating the high-side MOSFET device HS and the low-side MOSFET device LS in accordance with at least one control signal generated by the controller 2008. The first bias signal generated by each driver circuit 2002, 2004, 2006 is provided to the gate (G) of the high side MOSFET device and the second bias signal generated by the driver circuit is provided to the gate of the low side MOSFET device. In the drive circuit 2002, 2004 or 2006, the source (S) of the high-side MOSFET device is connected to the drain (D) of the low-side MOSFET device at a corresponding switching node SW1, SW2 or SWn, respectively. High-side MOSFET device in each drive circuit 2002, 2004, 2006Drain of component and input voltage terminal V of multiphase power management circuit 2000 IN Connected, while the source of the low-side MOSFET device is coupled to the voltage return of the circuit, preferably Ground (GND); that is, the drains of the individual high side MOSFET devices are connected together to form a common input voltage terminal V IN 。
The drive circuits 2002, 2004, 2006 and the corresponding high-side and low-side MOSFET devices form a given phase circuit (1, 2, …, n) of the multiphase power management circuit 2000. Fig. 20B is a top perspective view of at least a portion of the exemplary multi-phase power management circuit 2000 shown in fig. 20A in accordance with one or more embodiments of the present utility model. Referring to fig. 20B, a first phase circuit (phase-1) 2052 includes a first driver circuit 2002 and corresponding high and low side MOSFET devices, a second phase circuit (phase-2) 2054 includes a second driver circuit 2004 and corresponding high and low side MOSFET devices, and an nth phase circuit (n-phase) 2056 includes an nth driver circuit 2006 and corresponding high and low side MOSFET devices. The phase circuits 2052, 2054, and 2056 are all fabricated on a common die 2060. The phase circuits 2052, 2054, and 2056 may also be implemented as n separate chips stacked on the back of a common power stage chip. Although shown as a separate chip, in one or more embodiments, the controller 2008 may also be fabricated on the same chip as the phase circuits 2052, 2054, 2056.
In contrast to the multi-phase power management circuit 1900 shown in fig. 19A and 19B, the exemplary multi-phase power management circuit 2000 shown in fig. 20A and 20B includes a shared input capacitor 2062, i.e., C, integrated with the phase circuits 2052, 2054, 2056 IN . In one or more embodiments, the input capacitor 2062 includes first and second conductive layers (e.g., metal, doped polysilicon, etc.) separated by an insulating layer disposed therebetween in a manner consistent with the illustrative integrated capacitor shown in fig. 4D. Although depicted in fig. 20B as a single integrated capacitor, it should be appreciated that in other embodiments, integrated input capacitor 2062 may comprise multiple back side capacitors, similar to integrated capacitor structure 800 depicted in fig. 8.
Referring to fig. 20A and 20B, a capacitor C is input IN Is arranged on the conveying beltVoltage input terminal V IN And ground to reduce voltage spikes at the input voltage terminals of the power management circuit 2000. In the power management circuit 2000, due to the input capacitor C IN Integrated with the phase circuits 2052, 2054, 2056, preferably in close proximity to the power MOSFET devices, thereby eliminating stray inductance (L STRAY ) And resistance (R) STRAY ) Or at least significantly reduced, thereby advantageously improving high frequency performance in power management device 2000.
At least some of the techniques of this utility model may be implemented in an integrated circuit. In forming integrated circuits, identical dies are typically fabricated in a repeated pattern on a semiconductor wafer surface. Each die includes the devices described herein, and may also include other structures and/or circuits. Individual die are singulated from the wafer and then packaged as integrated circuits. Those skilled in the art will know how to dice and package die from a wafer to form integrated circuits. Any of the exemplary structures or circuits shown in the figures, or a portion thereof, may be part of an integrated circuit. Such integrated circuit fabrication methods are also considered part of the present utility model.
Those skilled in the art will appreciate that the above-described exemplary structures of high density semiconductor devices incorporating capacitors in one or more embodiments of the present utility model may be applied in a variety of products, such as DC-DC converters, radio Frequency (RF) power amplifiers, etc., in raw form (i.e., a single wafer with multiple unpackaged chips), bare chips, or in packaged form, or as an intermediate product or as part of an end product.
Integrated circuits consistent with the present disclosure may be used in any high frequency, high power application and/or electronic system. Systems suitable for implementing embodiments of the present utility model may include, but are not limited to, DC-DC converters/voltage regulators. Systems incorporating such integrated circuits are considered to be part of the present utility model. Other implementations and applications of embodiments of the present utility model will occur to those of ordinary skill in the art in view of the teachings of the utility model as provided herein.
The illustrations of embodiments of the utility model herein are intended to provide a general understanding of many of the embodiments and are not a complete description of all of the elements and features of apparatus and systems that may use the circuits and techniques of the utility model. Many other embodiments will be apparent to, or can be derived from, the teaching herein, such that structural and logical substitutions and changes can be made without departing from the scope of the disclosure. The figures are also merely representational and are not drawn to scale. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
The various embodiments of the utility model recited herein, individually and/or collectively, reference the term "embodiment" merely for convenience and without intending to limit the scope of this utility model to any single or several embodiments or inventive concepts. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that an arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown; that is, the utility model is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will also be apparent to those of skill in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The article "a" or "an" as used herein may also include plural referents unless the context clearly dictates otherwise. Further, as used in the specification, the terms "comprises" and/or "comprising," and/or "including," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. And terms such as "above," "below," "upper" and "lower" are used to indicate relative positional relationships between elements or structures, rather than absolute positions.
The corresponding structures, materials, acts, and equivalents of all means or function plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the utility model. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, and to enable others of ordinary skill in the art to understand the utility model for various embodiments and with various modifications as are suited to the particular use contemplated.
The purpose of the Abstract is to enable the reader to quickly ascertain the nature of the technical disclosure. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single embodiment. Thus, the claims are hereby incorporated into the specification, with each claim standing on its own as a separate claimed subject matter.
Other implementations and applications of the techniques of embodiments of the present utility model will be apparent to those of ordinary skill in the art in view of the teachings of the embodiments of the present utility model. Although illustrative embodiments of the present utility model have been described herein with reference to the accompanying drawings, it is to be understood that embodiments of the utility model are not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope of the claims.

Claims (19)

1. A semiconductor structure, comprising:
at least one first chip including a semiconductor substrate and an active layer formed on an upper surface of the substrate, one or more lateral metal oxide semiconductor devices being formed in the active layer of the first chip; and
at least one first integrated capacitor disposed on a back surface of the semiconductor substrate of the first chip, the first integrated capacitor including a first conductive layer electrically connected to the back surface of the substrate, an insulating layer formed on at least a portion of an upper surface of the first conductive layer, and a second conductive layer formed on at least a portion of an upper surface of the insulating layer.
2. The semiconductor structure of claim 1, wherein the first conductive layer of the first integrated capacitor comprises a doped region formed on the back side of the semiconductor substrate of the first chip.
3. The semiconductor structure of claim 1, wherein the first conductive layer of the first integrated capacitor comprises a backside portion of the semiconductor substrate doped with n-type or p-type impurities at a predetermined doping concentration level, thereby reducing a resistivity of the backside portion of the semiconductor substrate of the first chip.
4. The semiconductor structure of claim 1, wherein the first conductive layer of the first integrated capacitor comprises a metal layer formed on the back side of the semiconductor substrate of the first chip.
5. The semiconductor structure of claim 1, wherein the first and second conductive layers of the first integrated capacitor are formed of different materials.
6. The semiconductor structure of claim 1, further comprising at least a second integrated capacitor disposed on an upper surface of the first integrated capacitor, the second integrated capacitor comprising a first conductive layer shared with the second conductive layer of the first integrated capacitor, an insulating layer formed on at least a portion of an upper surface of the first conductive layer of the second integrated capacitor, and a second conductive layer formed on at least a portion of an upper surface of the insulating layer of the second integrated capacitor.
7. The semiconductor structure of claim 6, wherein a width of the insulating layer and second conductive layer of the second integrated capacitor is less than a width of the second conductive layer of the first integrated capacitor to provide an electrical connection path with the second conductive layer of the first integrated capacitor.
8. The semiconductor structure of claim 1, further comprising a second chip arranged in a stack with respect to the first chip, the at least one first integrated capacitor being arranged between the first and second chips.
9. The semiconductor structure of claim 8, wherein the second chip comprises a drive circuit and the first chip comprises at least one power MOS transistor, the at least one first integrated capacitor being electrically coupled to at least one of the drive circuit and the at least one power MOS transistor.
10. The semiconductor structure of claim 9, further comprising at least one second integrated capacitor disposed on an upper surface of the first integrated capacitor and between the first and second chips, the first integrated capacitor electrically coupled with at least one power MOS transistor and the second integrated capacitor electrically coupled with the drive circuit.
11. The semiconductor structure of claim 8, further comprising a die attach layer formed between at least a first integrated capacitor and the second chip for attaching the first and second chips.
12. The semiconductor structure of claim 11, wherein the die attach layer comprises at least one of a conductive material and a non-conductive material.
13. The semiconductor structure of claim 8, wherein the first and second chips are stacked such that back surfaces of the first and second chips face each other.
14. The semiconductor structure of claim 8, wherein the first and second chips are stacked such that a back side of the first chip faces a front side of the second chip.
15. The semiconductor structure of claim 8, further comprising at least one of (i) one or more through silicon vias formed through at least one of the first and second chips and (ii) a wire connection, wherein the electrical connection between the first and second chips and at least the first integrated capacitor is achieved using at least one of TSVs and a wire connection.
16. The semiconductor structure of claim 8, wherein the second chip comprises a semiconductor substrate and an active layer formed on a substrate upper surface of the second chip, one or more lateral MOS devices formed in the active layer of the second chip, wherein the second conductive layer of at least the first integrated capacitor comprises a backside portion of the semiconductor substrate of the second chip doped with n-type or p-type impurities at a prescribed doping concentration level to reduce the resistivity of the backside portion of the semiconductor substrate of the second chip.
17. The semiconductor structure of claim 1, further comprising a second chip disposed in a stacked arrangement relative to the first chip, the at least one first integrated capacitor disposed between the first and second chips, wherein the first chip is a power-level chip and the second chip is a drive chip, wherein the at least one first integrated capacitor is at least one input capacitance connected between ground and a power supply of the power-level chip, or a bootstrap capacitor connected between a switching node of the power-level chip and a drive circuit node in the drive chip.
18. A semiconductor multiphase power management module, comprising:
a multiphase power stage chip comprising a semiconductor substrate and an active layer formed on an upper surface of the substrate, a plurality of lateral metal oxide semiconductor devices being formed in the active layer of the multiphase power stage chip;
a plurality of driver chips arranged in a stacked manner on a back side of the multi-phase power stage chip, each driver chip including a driver circuit for controlling one of respective lateral MOS devices formed in the multi-phase power stage chip; and
At least a first integrated capacitor disposed between the plurality of driver chips and the multi-phase power stage chip, the at least a first integrated capacitor including a first conductive layer electrically connected to a back surface of a substrate of the multi-phase power stage chip, an insulating layer formed on at least a portion of an upper surface of the first conductive layer, and a second conductive layer formed on at least a portion of an upper surface of the insulating layer.
19. The semiconductor multiphase power management module of claim 18, wherein the plurality of driver chips are formed on a common semiconductor substrate, the common semiconductor substrate of the driver chips being disposed in a stacked manner on the at least one first integrated capacitor.
CN202220800166.1U 2022-03-31 2022-03-31 Semiconductor structure and semiconductor multiphase power management module Active CN219066824U (en)

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