CN219039646U - Ramp voltage generation circuit, motor control device and microprocessor chip - Google Patents

Abstract

The present utility model relates to the field of electronic technology, and in particular, to a ramp voltage generating circuit, a motor control device, and a microprocessor chip. The ramp voltage generation circuit includes: the first current source, the first current mirror branch, the second current mirror branch, the capacitor and the operational amplifier; the output end of the first current source is connected with a first branch of the current mirror, the other end of the first branch of the current mirror is grounded, and the output end of the first current source is also connected with a second branch of the current mirror; the capacitor is arranged between the second branch of the current mirror and the ground; the positive input interface of the operational amplifier is connected with the second branch of the current mirror, the negative input interface of the operational amplifier is connected with the first branch of the current mirror, and the output interface of the operational amplifier is connected with the first branch of the current mirror. By setting the operational amplifier in the ramp voltage generating circuit, the output voltage maintains good linearity.

Description

Ramp voltage generation circuit, motor control device and microprocessor chip

Technical Field

The present utility model relates to the field of electronic technology, and in particular, to a ramp voltage generating circuit, a motor control device, and a microprocessor chip.

Background

In the existing capacitor charging type slope circuit, a current source charges a capacitor to form a slope voltage, the current is determined by an MOS tube, and linearity often encounters a problem during actual operation. Taking an NMOS transistor as an example, when the difference between the gate voltage and the source voltage and the turn-on voltage is greater than the difference between the drain voltage and the source voltage, the NMOS transistor can operate in the linear region. Along with the increase of the source voltage, the voltage difference between the grid electrode and the source electrode is reduced, the NMOS tube works in a saturation region, and the voltage and the current are not in linear relation any more, so that the operation of the circuit is affected.

Disclosure of Invention

The embodiment of the utility model provides a ramp voltage generating circuit, a motor control device and a micro-processing chip, wherein an operational amplifier is arranged in the ramp voltage generating circuit, so that the output voltage keeps good linearity.

In a first aspect, an embodiment of the present utility model provides a ramp voltage generating circuit, including: the first current source, the first current mirror branch, the second current mirror branch, the capacitor and the operational amplifier;

the output end of the first current source is connected with the first branch of the current mirror, the other end of the first branch of the current mirror is grounded, and the output end of the first current source is also connected with the second branch of the current mirror;

the capacitor is arranged between the second branch of the current mirror and the ground;

the positive electrode input interface of the operational amplifier is connected with the second branch of the current mirror, the negative electrode input interface of the operational amplifier is connected with the first branch of the current mirror, and the output interface of the operational amplifier is connected with the first branch of the current mirror.

In one embodiment, at least one MOS transistor is respectively disposed on the first branch and the second branch of the current mirror, and a gate of one MOS transistor of the first branch of the current mirror is connected to a gate of one MOS transistor of the second branch of the current mirror.

In one embodiment, the first branch of the current mirror is provided with a first NMOS transistor, the output end of the first current source is connected with the drain electrode of the first NMOS transistor, and the grid electrode and the drain electrode of the first NMOS transistor are in short circuit through wires;

the second branch of the current mirror is provided with a second NMOS transistor, the source electrode of the second NMOS transistor is connected with the capacitor, and the grid electrode of the second NMOS transistor is connected with the grid electrode of the first NMOS transistor.

In one embodiment, the first branch of the current mirror is further provided with a third NMOS transistor, a drain of the third NMOS transistor is connected to a source of the first NMOS transistor, and a source of the third NMOS transistor is grounded.

In one embodiment, an input interface of the positive electrode of the operational amplifier is connected between the source electrode of the second NMOS tube and the capacitor, an input interface of the negative electrode of the operational amplifier is connected between the source electrode of the first NMOS tube and the drain electrode of the third NMOS tube, and an output interface of the operational amplifier is connected with the gate electrode of the third NMOS tube.

In one embodiment, the operational amplifier is internally provided with a second current source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor;

the output end of the second current source is connected with the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor, the drain electrode of the first PMOS transistor is connected with the drain electrode of the fourth NMOS transistor, the source electrode of the fourth NMOS transistor is grounded, the drain electrode of the second PMOS transistor is connected with the drain electrode of the fifth NMOS transistor, and the source electrode of the fifth NMOS transistor is grounded;

the source electrode of the third PMOS transistor is connected with the source electrode of the fourth PMOS transistor, the grid electrode of the third PMOS transistor is connected with the grid electrode of the fourth PMOS transistor, the drain electrode of the third PMOS transistor is connected with the drain electrode of the sixth NMOS transistor, the source electrode of the sixth NMOS transistor is grounded, the drain electrode of the fourth PMOS transistor is connected with the drain electrode of the seventh NMOS transistor, and the source electrode of the seventh NMOS transistor is grounded.

In one embodiment, the gate of the first PMOS transistor is a negative input interface of the operational amplifier, the gate of the second PMOS transistor is a positive input interface of the operational amplifier, and a lead is led out between the drain of the fourth PMOS transistor and the drain of the seventh NMOS transistor as an output interface of the operational amplifier.

In one embodiment, the drain and the gate of the fourth NMOS transistor are shorted by a wire, and the drain and the gate of the third PMOS transistor are shorted by a wire;

a lead is led out between the drain electrode of the second PMOS transistor and the drain electrode of the fifth NMOS transistor, and the other end of the lead is connected with the grid electrode of the sixth NMOS transistor;

the gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor, the gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, and the gate of the sixth NMOS transistor is connected to the gate of the seventh NMOS transistor, so that the gate voltage of NMOS is raised along with the rise of the output voltage by using a simple operational amplifier, particularly when the output voltage is low, so that the output voltage maintains good linearity.

In a second aspect, an embodiment of the present utility model provides a motor control apparatus, including: the ramp voltage generating circuit, the third current source, the counter, the edge detecting circuit, the clock divider, the oscillator, the sensor, the comparator, the first switch, and the second switch as provided in the first aspect;

the ramp voltage generating circuit is connected with the third current source, and the other end of the third current source is connected with the counter;

the oscillator is connected with the clock frequency divider, and the other end of the clock frequency divider is connected with the counter;

the counter is also connected with the edge detection circuit; the edge detection circuit is connected with the sensor, and the edge detection circuit receives a sensor level signal and controls the counter to work;

the output of the slope voltage generating circuit is connected with the comparator and used for controlling the switching of the first switch and the second switch.

In a third aspect, an embodiment of the present utility model provides a micro-processing chip including the ramp voltage generating circuit as provided in the first aspect.

In an embodiment of the present utility model, a ramp voltage generating circuit includes: the first current source, the first current mirror branch, the second current mirror branch, the capacitor and the operational amplifier; the output end of the first current source is connected with a first branch of the current mirror, the other end of the first branch of the current mirror is grounded, and the output end of the first current source is also connected with a second branch of the current mirror; the capacitor is arranged between the second branch of the current mirror and the ground; the positive input interface of the operational amplifier is connected with the second branch of the current mirror, the negative input interface of the operational amplifier is connected with the first branch of the current mirror, and the output interface of the operational amplifier is connected with the first branch of the current mirror. By setting the operational amplifier in the ramp voltage generating circuit, the output voltage maintains good linearity.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present utility model, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a ramp voltage generating circuit according to an embodiment of the present utility model;

fig. 2 is a schematic diagram of another ramp voltage generating circuit according to an embodiment of the present utility model;

fig. 3 is a schematic structural diagram of a motor control device according to an embodiment of the present utility model;

fig. 4 is a schematic structural diagram of a micro-processing chip according to an embodiment of the present utility model.

Detailed Description

For a better understanding of the technical solutions of the present specification, the following detailed description of the embodiments of the present utility model refers to the accompanying drawings.

It should be understood that the described embodiments are only some, but not all, of the embodiments of the present description. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present disclosure.

The terminology used in the embodiments of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

In the embodiment of the utility model, the ramp voltage generating circuit comprises a first current source, a first current mirror branch, a second current mirror branch, a capacitor and an operational amplifier. The output end of the first current source is connected with the first branch of the current mirror, the other end of the first branch of the current mirror is grounded, and the output end of the first current source is also connected with the second branch of the current mirror. The capacitor is arranged between the second branch of the current mirror and the ground. The positive input interface of the operational amplifier is connected with the second branch of the current mirror, the negative input interface of the operational amplifier is connected with the first branch of the current mirror, and the output interface of the operational amplifier is connected with the first branch of the current mirror.

In one embodiment, at least one MOS transistor is respectively disposed on the first branch and the second branch of the current mirror, and a gate of one MOS transistor of the first branch of the current mirror is connected to a gate of one MOS transistor of the second branch of the current mirror.

Fig. 1 is a schematic diagram of a ramp voltage generating circuit according to an embodiment of the present utility model. As shown in fig. 1, the ramp voltage generating circuit includes a current source 101, a first NMOS transistor 102, a second NMOS transistor 103, a third NMOS transistor 104, and an operational amplifier 105. The first branch of the current mirror is provided with a first NMOS transistor 102 and a third NMOS transistor 104, and the second branch of the current mirror is provided with a second NMOS transistor 103. The output end of the first current source 101 is connected with the drain electrode of the first NMOS transistor 102, and the gate electrode and the drain electrode of the first NMOS transistor 102 are shorted by a wire. The source of the second NMOS transistor 103 is connected to the capacitor 106, and the gate of the second NMOS transistor 103 is connected to the gate of the first NMOS transistor 102. The drain of the third NMOS transistor 104 is connected to the source of the first NMOS transistor 102, and the source of the third NMOS transistor 104 is grounded.

The positive input interface of the operational amplifier 105 is connected between the source of the second NMOS 103 and the capacitor 106, the negative input interface of the operational amplifier 105 is connected between the source of the first NMOS 102 and the drain of the third NMOS 104, and the output interface of the operational amplifier is connected with the gate of the third NMOS 104.

The first current source 101 charges the overall circuit and the voltage of the capacitor 106 increases, i.e. the voltage at point a increases. With the rise of the voltage at the point a, the rise of the voltage at the point B and the rise of the voltage at the point F, with the rise of the voltage at the point F, a larger voltage difference is maintained between the gate and the drain of the second NMOS transistor 103, and when the voltage difference between the gate and the drain of the second NMOS transistor 103 is larger than the turn-on voltage of the MOS transistor and the voltage difference between the drain and the source, the second NMOS transistor 103 can operate in a varistor region, and the output voltage and the current of the drain of the second NMOS transistor 103 maintain a linear relationship.

Fig. 2 is a schematic diagram of another ramp voltage generating circuit according to an embodiment of the present utility model. As shown in fig. 2, the ramp voltage generating circuit includes: a first current source 201, a second current source 202, a first NMOS transistor 203, a second NMOS transistor 209, a third NMOS transistor 204, a fourth NMOS transistor 207, a fifth NMOS transistor 208, a sixth NMOS transistor 213, a seventh NMOS transistor 214, a first PMOS transistor 205, a second PMOS transistor 206, a third PMOS transistor 211, a fourth PMOS transistor 212, and a capacitor 210. The second current source 202, the fourth NMOS transistor 207, the fifth NMOS transistor 208, the sixth NMOS transistor 213, the seventh NMOS transistor 214, the first PMOS transistor 205, the second PMOS transistor 206, the third PMOS transistor 211, and the fourth PMOS transistor 212 may constitute an operational amplifier of the ramp voltage generating circuit.

The output terminal of the second current source 202 is connected to the source of the first PMOS transistor 205 and the source of the second PMOS transistor 206, the drain of the first PMOS transistor 205 is connected to the drain of the fourth NMOS transistor 207, the source of the fourth NMOS transistor 207 is grounded, the drain of the second PMOS transistor 206 is connected to the drain of the fifth NMOS transistor 208, and the source of the fifth NMOS transistor 208 is grounded. The source of the third PMOS transistor 211 is connected to the source of the fourth PMOS transistor 212, the gate of the third PMOS transistor 211 is connected to the gate of the fourth PMOS transistor 212, the drain of the third PMOS transistor 211 is connected to the drain of the sixth NMOS transistor 213, the source of the sixth NMOS transistor 213 is grounded, the drain of the fourth PMOS transistor 212 is connected to the drain of the seventh NMOS transistor 214, and the source of the seventh NMOS transistor 214 is grounded. The gate of the first PMOS transistor 205 is the negative input interface of the operational amplifier, the gate of the second PMOS transistor 206 is the positive input interface of the operational amplifier, and the lead is led out between the drain of the fourth PMOS transistor 212 and the drain of the seventh NMOS transistor 214 as the output interface of the operational amplifier. The drain and gate of the fourth NMOS transistor 207 are shorted by a wire, and the drain and gate of the third PMOS transistor 211 are shorted by a wire. A lead is led out between the drain of the second PMOS transistor 206 and the drain of the fifth NMOS transistor 208, and the other end of the lead is connected to the gate of the sixth NMOS transistor 213. The gate of the fourth NMOS transistor 207 is connected to the gate of the fifth NMOS transistor 208, the gate of the third PMOS transistor 211 is connected to the gate of the fourth PMOS transistor 212, and the gate of the sixth NMOS transistor 213 is connected to the gate of the seventh NMOS transistor 214.

During charging, the voltage at the point a increases, the voltage at the point D decreases, the voltage at the point E increases, the voltage at the point C decreases, the voltage at the point B increases, the voltage at the point F increases, the voltage difference between the gate and the source of the second NMOS transistor 209 ensures a larger value as the voltage at the point F increases, the second NMOS transistor 209 operates in the variable resistance region, and the output voltage and the current ensure a linear relationship.

Fig. 3 is a schematic structural diagram of a motor control device according to an embodiment of the present utility model. As shown in fig. 3, the motor control device includes: a ramp voltage generating circuit 301, a third current source 302, a counter 303, an edge detection circuit 304, a clock divider 305, an oscillator 306, a first switch 307, a second switch 308, a comparator 309, and a sensor 310. The ramp voltage generating circuit 301 is connected to a third current source 302, the other end of the third current source 302 is connected to a counter 303, an oscillator 306 is connected to a clock divider 305, the other end of the clock divider 305 is connected to the counter 303, and the counter 303 is also connected to an edge detecting circuit 304. The edge detection circuit 304 is connected to the sensor 310, and the edge detection circuit 304 receives a level signal of the sensor 310 and controls the counter 303 to operate. The output of the ramp voltage generating circuit 301 is connected to a comparator 310 for controlling the switching of the first switch 307 and the second switch 308.

A brushless dc motor (Brushless Direct Current Motor, BLDCM) has a rotor disposed in a vertical stator pole and a horizontal stator pole. The apparatus for controlling the speed of the BLDC motor includes a sensor 310, a first switch 307, and a second switch 308. The sensor 310 detects the magnetic rotor portion of the rotor and the first switch 307 creates magnetic north on the vertical stator poles of the BLDC motor and magnetic south on the horizontal stator poles. The second switch 308 generates magnetic south on the vertical stator poles of the BLDC motor 800 and magnetic north on the horizontal stator poles. The voltage ramp generation circuit 301 and the comparator 309 are used to produce a reduction in on-time after each output transition of the sensor 310. The voltage ramp generation circuit 301 is triggered to generate a ramp voltage (Vramp) by each output of the sensor 310 transitioning from a low logic level to a high logic level or from a high logic level to a low logic level. The non-inverting input of the comparator 309 is electrically connected to a ramp voltage (Vramp), and the inverting input of the comparator 309 is electrically connected to a reference voltage (TDSET). When the ramp voltage (Vramp) exceeds the reference voltage (TDSET), the comparator 309 generates a decrease in the on-time for alternately switching the first switch 307 and the second switch 308. Further, the sensor 310 outputs a high logic level when the sensor 310 detects that the magnetic north rotor portion (N) is close, and outputs a low logic level when the sensor 310 detects that the magnetic south rotor portion (S) is close. When the output of the sensor 310 transitions from a low logic level to a high logic level, the first switch 307 is turned on with a turn-on delay (Ton delay) of a turn-on time; and the output of the sensor 310 transitions from a high logic level to a low logic level, the second switch 308 turns on with a turn-on delay of the turn-on time. Further, in the preferred embodiment, the first switch 307 and the second switch 308 are MOS transistors, respectively.

More specifically, oscillator 306 generates a 1.0MHz (1.0 musec) pulse. The 1MHz pulse is divided by clock divider 305 to become a 2kHz clock (0.5 msec pulse). The counter 303 controlling the array of third current sources 302 (1 μa, 2 μa, etc. to 64 μa) is driven by a 2kHz clock. The counter 303 is also reset and begins counting each time the edge detection circuit 304 receives a rising or falling edge from the sensor 310. When the counter 303 counts up, more current is applied to the ramp voltage generating circuit, thereby generating the voltage ramp Vramp.

The voltage and current of the ramp voltage generating circuit 301 can maintain a good linear relationship, so that the motor control circuit works stably.

Fig. 4 is a schematic structural diagram of a micro-processing chip according to an embodiment of the present utility model. As shown in fig. 4, a ramp voltage generating circuit 420 is provided inside the micro processing chip 410. Alternatively, the ramp voltage generating circuit 420 is the ramp voltage generating circuit in fig. 1 or fig. 2. The voltage and current of the ramp voltage generating circuit 420 can maintain a good linear relationship, which facilitates more stable operation of the microprocessor chip 410.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present utility model, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the utility model.

Claims (10)

1. A ramp voltage generation circuit, comprising: the first current source, the first current mirror branch, the second current mirror branch, the capacitor and the operational amplifier;

the output end of the first current source is connected with the first branch of the current mirror, the other end of the first branch of the current mirror is grounded, and the output end of the first current source is also connected with the second branch of the current mirror;

the capacitor is arranged between the second branch of the current mirror and the ground;

the positive electrode input interface of the operational amplifier is connected with the second branch of the current mirror, the negative electrode input interface of the operational amplifier is connected with the first branch of the current mirror, and the output interface of the operational amplifier is connected with the first branch of the current mirror.

2. The circuit of claim 1, wherein at least one MOS transistor is disposed on each of the first branch of the current mirror and the second branch of the current mirror, and a gate of one MOS transistor of the first branch of the current mirror is connected to a gate of one MOS transistor of the second branch of the current mirror.

3. The circuit according to claim 1, wherein the first branch of the current mirror is provided with a first NMOS transistor, the output terminal of the first current source is connected to the drain of the first NMOS transistor, and the gate and drain of the first NMOS transistor are shorted by a wire;

the second branch of the current mirror is provided with a second NMOS transistor, the source electrode of the second NMOS transistor is connected with the capacitor, and the grid electrode of the second NMOS transistor is connected with the grid electrode of the first NMOS transistor.

4. A circuit according to claim 3, wherein the first branch of the current mirror is further provided with a third NMOS transistor, the drain of which is connected to the source of the first NMOS transistor, the source of which is grounded.

5. The circuit of claim 4, wherein a positive input interface of the operational amplifier is connected between a source of the second NMOS transistor and the capacitor, a negative input interface of the operational amplifier is connected between a source of the first NMOS transistor and a drain of the third NMOS transistor, and an output interface of the operational amplifier is connected with a gate of the third NMOS transistor.

6. The circuit of claim 1, wherein the operational amplifier is internally provided with a second current source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor;

the output end of the second current source is connected with the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor, the drain electrode of the first PMOS transistor is connected with the drain electrode of the fourth NMOS transistor, the source electrode of the fourth NMOS transistor is grounded, the drain electrode of the second PMOS transistor is connected with the drain electrode of the fifth NMOS transistor, and the source electrode of the fifth NMOS transistor is grounded;

the source electrode of the third PMOS transistor is connected with the source electrode of the fourth PMOS transistor, the grid electrode of the third PMOS transistor is connected with the grid electrode of the fourth PMOS transistor, the drain electrode of the third PMOS transistor is connected with the drain electrode of the sixth NMOS transistor, the source electrode of the sixth NMOS transistor is grounded, the drain electrode of the fourth PMOS transistor is connected with the drain electrode of the seventh NMOS transistor, and the source electrode of the seventh NMOS transistor is grounded.

7. The circuit of claim 6, wherein the gate of the first PMOS transistor is the negative input interface of the operational amplifier, the gate of the second PMOS transistor is the positive input interface of the operational amplifier, and a lead is led out between the drain of the fourth PMOS transistor and the drain of the seventh NMOS transistor as the output interface of the operational amplifier.

8. The circuit of claim 6, wherein the drain and gate of the fourth NMOS transistor are shorted by a wire and the drain and gate of the third PMOS transistor are shorted by a wire;

a lead is led out between the drain electrode of the second PMOS transistor and the drain electrode of the fifth NMOS transistor, and the other end of the lead is connected with the grid electrode of the sixth NMOS transistor;

the gate of the fourth NMOS transistor is connected with the gate of the fifth NMOS transistor, the gate of the third PMOS transistor is connected with the gate of the fourth PMOS transistor, and the gate of the sixth NMOS transistor is connected with the gate of the seventh NMOS transistor.

9. A motor control apparatus, characterized by comprising: the ramp voltage generating circuit of any one of claims 1-8, a third current source, a counter, an edge detection circuit, a clock divider, an oscillator, a sensor, a comparator, a first switch, and a second switch;

the ramp voltage generating circuit is connected with the third current source, and the other end of the third current source is connected with the counter;

the oscillator is connected with the clock frequency divider, and the other end of the clock frequency divider is connected with the counter;

the counter is also connected with the edge detection circuit; the edge detection circuit is connected with the sensor, receives a sensor level signal and controls the counter to work;

the output of the slope voltage generating circuit is connected with the comparator and used for controlling the switching of the first switch and the second switch.

10. A microprocessor chip comprising the ramp voltage generating circuit according to any one of claims 1-8.

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