CN219039606U

CN219039606U - Analog switch array

Info

Publication number: CN219039606U
Application number: CN202223486472.1U
Authority: CN
Inventors: 孙至侃; 张晓丹; 李杭
Original assignee: Goldcard Smart Group Co Ltd
Current assignee: Goldcard Smart Group Co Ltd
Priority date: 2022-12-26
Filing date: 2022-12-26
Publication date: 2023-05-16
Anticipated expiration: 2032-12-26

Abstract

An embodiment of the present application provides an analog switch array, including: a plurality of switching units including at least a first switching unit and a second switching unit, and a plurality of transducers including at least a first transducer and a second transducer; the first switch unit is used for switching forward and backward flow detection and isolating the receiving and transmitting signals of the first transducer and the second transducer; the second switch unit is used for receiving the forward and backward flow receiving signals, isolating the forward and backward flow receiving signals and selecting the forward and backward flow receiving signals. The analog switch array provided by the embodiment can reduce flow errors while overcoming the defect that the switching of the forward and reverse flow detection cannot be realized in the prior art, and further improves the measurement accuracy of the flowmeter.

Description

Analog switch array

Technical Field

The embodiment of the application relates to the technical field of switches, in particular to an analog switch array.

Background

With the popularization of ultrasonic technology in flowmeter measurement, the performance requirements for ultrasonic metering are also continuously increasing. The basic principle of ultrasonic measurement is that the flow data is obtained by converting the time difference of flight of sound waves in the forward and backward directions to obtain the fluid velocity. This principle determines that one measurement process requires two transmissions and receptions to measure the forward and reverse flow sound velocity, respectively. Meanwhile, the problems of cost, volume, consistency of devices and the like are limited, and the switching of the forward and backward flow detection is realized by adopting a pair of transducers and matching with a switch.

At present, a common switching mode is as follows: the two transducers are connected to either the excitation or the receiving link by two single pole double throw switches, respectively. However, in actual ultrasonic metrology, the excitation signal and the echo signal often differ by several orders of magnitude. Meanwhile, due to the limitation of factors such as cost, space, flow field and the like, the transducer driving circuit is mostly in a small and precise design, so that the transceiving circuit is difficult to thoroughly isolate, and therefore, the high-voltage excitation signal easily pollutes the mV or uV-level echo signal, thereby generating false waves, and causing the problems of large flow error and the like.

Therefore, the prior art can not realize the switching of the forward and backward flow detection, and simultaneously reduces the flow error, thereby improving the measurement accuracy of the flowmeter.

Disclosure of Invention

The embodiment of the application provides an analog switch array to solve the problem that in the prior art, flow errors are reduced and then the measurement accuracy of a flowmeter is improved when switching of forward and backward flow detection cannot be realized.

In a first aspect, embodiments of the present application provide an analog switch array, including: a plurality of switching units including at least a first switching unit and a second switching unit, and a plurality of transducers including at least a first transducer and a second transducer;

The first end of the first switch unit and the second end of the first switch unit are grounded, the third end of the first switch unit and the fourth end of the first switch unit are connected and are respectively connected with the excitation generation unit, the fifth end of the first switch unit is connected with the second end of the second switch unit, the sixth end of the first switch unit is connected with one end of the first transducer, the seventh end of the first switch unit is connected with the first end of the second switch unit, and the eighth end of the first switch unit is connected with one end of the second transducer; the other end of the first energy converter and the other end of the second energy converter are grounded;

the third end of the second switch unit and the fourth end of the second switch unit are grounded, and the fifth end of the second switch unit is connected with the signal conditioning unit;

the first switch unit is used for switching forward and backward flow detection and isolating the receiving and transmitting signals of the first transducer and the second transducer;

the second switch unit is used for receiving the forward and backward flow receiving signals, isolating the forward and backward flow receiving signals and selecting the forward and backward flow receiving signals.

In one possible design, the first switching unit includes a first switching chip and a second switching chip, and the second switching unit includes a third switching chip, a fourth switching chip, and a fifth switching chip;

the first end of the first switch chip is the third end of the first switch unit, the second end of the first switch chip is the first end of the first switch unit, the third end of the first switch chip is the sixth end of the first switch unit, and the fourth end of the first switch chip is the fifth end of the first switch unit; the first end of the second switch chip is the second end of the first switch unit, the second end of the second switch chip is the fourth end of the first switch unit, the third end of the second switch chip is the eighth end of the first switch unit, and the fourth end of the second switch chip is the seventh end of the first switch unit; the first end of the third switch chip is a third end of the second switch unit, and the second end of the third switch chip is a second end of the second switch unit; the first end of the fourth switch chip is the first end of the second switch unit, and the second end of the fourth switch chip is the fourth end of the second switch unit; the third end of the fifth switch chip is a fifth end of the second switch unit;

The third end of the third switch chip is connected with the second end of the fifth switch chip; the third end of the fourth switch chip is connected with the first end of the fifth switch chip;

the first switch chip and the second switch chip are used for switching forward and backward flow detection and isolating the receiving and transmitting signals of the first transducer and the second transducer;

the third switch chip and the fourth switch chip are used for receiving the forward and backward flow receiving signals and isolating the forward and backward flow receiving signals;

the fifth switch chip is used for selecting forward and backward flow receiving signals.

In one possible design, the first and second switch chips are two-way single-pole double-throw switch chips, and the first switch chip includes a first single-pole double-throw switch and a second single-pole double-throw switch, and the second switch chip includes a third single-pole double-throw switch and a fourth single-pole double-throw switch;

a first channel selection port of the first single-pole double-throw switch is used as a third end of the first switch chip, a second channel selection port of the first single-pole double-throw switch is used as a second end of the first switch chip, a public port of the first single-pole double-throw switch is connected with the first channel selection port of a second single-pole double-throw switch, the second channel selection port of the second single-pole double-throw switch is used as a fourth end of the first switch chip, and a public port of the second single-pole double-throw switch is used as the third end of the first switch chip;

The first channel selection port of the third single-pole double-throw switch is used as the first end of the second switch chip, the second channel selection port of the third single-pole double-throw switch is used as the second end of the second switch chip, the common port of the third single-pole double-throw switch is connected with the second channel selection port of the fourth single-pole double-throw switch, the first channel selection port of the fourth single-pole double-throw switch is used as the fourth end of the second switch chip, and the common port of the fourth single-pole double-throw switch is used as the third end of the second switch chip;

the first single-pole double-throw switch and the third single-pole double-throw switch are respectively used as a receiving-transmitting isolating switch of the first energy converter and the second energy converter; the second single-pole double-throw switch and the fourth single-pole double-throw switch are respectively used as a receiving-transmitting change-over switch of the first energy converter and the second energy converter.

In one possible design, the third switch chip includes a fifth single pole double throw switch; a first channel selection port of the fifth single-pole double-throw switch is used as a first end of the third switch chip, a second channel selection port of the fifth single-pole double-throw switch is used as a second end of the third switch chip, and a common port of the fifth single-pole double-throw switch is used as a third end of the third switch chip;

The fifth single-pole double-throw switch is used as a switch for receiving the forward and backward flow receiving signals and isolating the forward and backward flow receiving signals. In one possible design, the fourth switch chip includes a sixth single pole double throw switch; a first channel selection port of the sixth single-pole double-throw switch is used as a first end of the fourth switch chip, a second channel selection port of the sixth single-pole double-throw switch is used as a second end of the fourth switch chip, and a common port of the sixth single-pole double-throw switch is used as a third end of the fourth switch chip;

the sixth single-pole double-throw switch is used as a switch for receiving the forward and backward flow receiving signals and isolating the forward and backward flow receiving signals.

In one possible design, the fifth switch chip includes a seventh single pole double throw switch; a first channel selection port of the seventh single-pole double-throw switch is used as a first end of the fifth switch chip, a second channel selection port of the seventh single-pole double-throw switch is used as a second end of the fifth switch chip, and a common port of the seventh single-pole double-throw switch is used as a third end of the fifth switch chip;

the seventh single-pole double-throw switch is used as a forward and reverse current receiving signal selection switch.

In a second aspect, embodiments of the present application provide an analog switch array, including: a plurality of switching units including at least a first switching unit, a second switching unit, and a third switching unit, and a plurality of transducers including at least a first transducer and a second transducer;

the first end of the first switch unit, the third end of the first switch unit and the fifth end of the first switch unit are all grounded, the second end of the first switch unit and the second end of the second switch unit are connected with the differential excitation generation unit respectively, the fourth end of the first switch unit is connected with one end of the first transducer, the sixth end of the first switch unit is connected with the sixth end of the second switch unit and is connected with the differential excitation generation unit respectively, the seventh end of the first switch unit is connected with the first end of the third switch unit, and the eighth end of the first switch unit is connected with the other end of the first transducer;

the first end of the second switch unit, the third end of the second switch unit and the fifth end of the second switch unit are all grounded, the fourth end of the second switch unit is connected with one end of the second transducer, the seventh end of the second switch unit is connected with the fourth end of the third switch unit, and the eighth end of the second switch unit is connected with the other end of the second transducer;

The second end of the third switch unit and the third end of the third switch unit are grounded, and the fifth end of the third switch unit is connected with the signal conditioning unit;

the first switch unit and the second switch unit are used for switching forward and backward flow detection and isolating the receiving and transmitting signals of the first transducer and the second transducer;

the third switch unit is used for receiving the forward and backward flow receiving signals, isolating the forward and backward flow receiving signals and selecting the forward and backward flow receiving signals.

In one possible design, the first switching unit includes a first switching chip and a second switching chip, the second switching unit includes a third switching chip and a fourth switching chip, and the third switching unit includes a fifth switching chip, a sixth switching chip, and a seventh switching chip;

the first end of the first switch chip is the second end of the first switch unit, the second end of the first switch chip is the first end of the first switch unit, the third end of the first switch chip is the third end of the first switch unit, and the fourth end of the first switch chip is the fourth end of the first switch unit; the first end of the second switch chip is the sixth end of the first switch unit, the second end of the second switch chip is the fifth end of the first switch unit, the third end of the second switch chip is the eighth end of the first switch unit, and the fourth end of the second switch chip is the seventh end of the first switch unit; the first end of the third switch chip is the second end of the second switch unit, the second end of the third switch chip is the first end of the second switch unit, the third end of the third switch chip is the third end of the second switch unit, and the fourth end of the third switch chip is the fourth end of the second switch unit; the first end of the fourth switch chip is the sixth end of the second switch unit, the second end of the fourth switch chip is the fifth end of the second switch unit, the third end of the fourth switch chip is the eighth end of the second switch unit, and the fourth end of the fourth switch chip is the seventh end of the second switch unit; the first end of the fifth switch chip is the second end of the third switch unit, and the second end of the fifth switch chip is the first end of the third switch unit; the first end of the sixth switch chip is a fourth end of the third switch unit, and the second end of the sixth switch chip is a third end of the third switch unit; the third end of the seventh switch chip is a fifth end of the third switch unit;

The third end of the fifth switch chip is connected with the second end of the seventh switch chip; the third end of the sixth switch chip is connected with the first end of the seventh switch chip;

the first switch chip, the second switch chip, the third switch chip and the fourth switch chip are all used for switching forward and backward flow detection and isolating the receiving and transmitting signals of the first transducer and the second transducer;

the fifth switch chip and the sixth switch chip are used for receiving the forward and backward flow receiving signals and isolating the forward and backward flow receiving signals;

the seventh switch chip is used for selecting forward and backward flow receiving signals.

In one possible design, the first switch chip includes a first single-pole double-throw switch and a second single-pole double-throw switch, the second switch chip includes a third single-pole double-throw switch and a fourth single-pole double-throw switch, the third switch chip includes a fifth single-pole double-throw switch and a sixth single-pole double-throw switch, and the fourth switch chip includes a seventh single-pole double-throw switch and an eighth single-pole double-throw switch;

a first channel selection port of the first single-pole double-throw switch is used as a first end of the first switch chip, a second channel selection port of the first single-pole double-throw switch is used as a second end of the first switch chip, a public port of the first single-pole double-throw switch is connected with the first channel selection port of a second single-pole double-throw switch, the second channel selection port of the second single-pole double-throw switch is used as a third end of the first switch chip, and a public port of the second single-pole double-throw switch is used as a fourth end of the first switch chip;

The first channel selection port of the third single-pole double-throw switch is used as the first end of the second switch chip, the second channel selection port of the third single-pole double-throw switch is used as the second end of the second switch chip, the common port of the third single-pole double-throw switch is connected with the first channel selection port of the fourth single-pole double-throw switch, the second channel selection port of the fourth single-pole double-throw switch is used as the fourth end of the second switch chip, and the common port of the fourth single-pole double-throw switch is used as the third end of the second switch chip;

a first channel selection port of the fifth single-pole double-throw switch is used as a first end of the third switch chip, a second channel selection port of the fifth single-pole double-throw switch is used as a second end of the third switch chip, a common port of the fifth single-pole double-throw switch is connected with a second channel selection port of a sixth single-pole double-throw switch, the first channel selection port of the sixth single-pole double-throw switch is used as a third end of the third switch chip, and a common port of the sixth single-pole double-throw switch is used as a fourth end of the third switch chip;

a first channel selection port of the seventh single-pole double-throw switch is used as a first end of the fourth switch chip, a second channel selection port of the seventh single-pole double-throw switch is used as a second end of the fourth switch chip, a common port of the seventh single-pole double-throw switch is connected with a second channel selection port of an eighth single-pole double-throw switch, the first channel selection port of the eighth single-pole double-throw switch is used as a fourth end of the fourth switch chip, and a common port of the eighth single-pole double-throw switch is used as a third end of the fourth switch chip;

The first single-pole double-throw switch and the third single-pole double-throw switch are respectively used as a receiving and transmitting isolating switch of the first energy converter; the fifth single-pole double-throw switch and the seventh single-pole double-throw switch are respectively used as a receiving and transmitting isolating switch of the second energy converter; the second single-pole double-throw switch and the fourth single-pole double-throw switch are respectively used as a receiving-transmitting change-over switch of the second energy converter; the sixth single-pole double-throw switch and the eighth single-pole double-throw switch are respectively used as a receiving and transmitting change-over switch of the second transducer.

In one possible design, the fifth switch chip includes a ninth single pole double throw switch; a first channel selection port of the ninth single-pole double-throw switch is used as a first end of the fifth switch chip, a second channel selection port of the ninth single-pole double-throw switch is used as a second end of the fifth switch chip, and a common port of the ninth single-pole double-throw switch is used as a third end of the fifth switch chip;

the ninth single-pole double-throw switch is used as a switch for receiving the forward and backward flow receiving signals and isolating the forward and backward flow receiving signals.

In one possible design, the sixth switch chip includes a tenth single pole double throw switch; a first channel selection port of the tenth single-pole double-throw switch is used as a first end of the sixth switch chip, a second channel selection port of the tenth single-pole double-throw switch is used as a second end of the sixth switch chip, and a common port of the tenth single-pole double-throw switch is used as a third end of the sixth switch chip;

The tenth single-pole double-throw switch is used as a switch for receiving the forward and backward flow receiving signals and isolating the forward and backward flow receiving signals.

In one possible design, the seventh switch chip includes an eleventh single pole double throw switch; a first channel selection port of the eleventh single-pole double-throw switch is used as a first end of the seventh switch chip, a second channel selection port of the eleventh single-pole double-throw switch is used as a second end of the seventh switch chip, and a common port of the eleventh single-pole double-throw switch is used as a third end of the seventh switch chip;

the eleventh single-pole double-throw switch is used as a forward and reverse current receiving signal selection switch.

According to the analog switch array, the plurality of switch units and the plurality of transducers are arranged, the plurality of switch units at least comprise a first switch unit and a second switch unit, and the plurality of transducers at least comprise a first transducer and a second transducer; the first end of the first switch unit and the second end of the first switch unit are grounded, the third end of the first switch unit and the fourth end of the first switch unit are connected and are respectively connected with the excitation generation unit, the fifth end of the first switch unit is connected with the second end of the second switch unit, the sixth end of the first switch unit is connected with one end of the first transducer, the seventh end of the first switch unit is connected with the first end of the second switch unit, and the eighth end of the first switch unit is connected with one end of the second transducer; the other end of the first energy converter and the other end of the second energy converter are grounded; the third end of the second switch unit and the fourth end of the second switch unit are grounded, and the fifth end of the second switch unit is connected with the signal conditioning unit; the first switch unit is used for switching forward and backward flow detection and isolating the receiving and transmitting signals of the first transducer and the second transducer; the second switch unit is used for receiving the forward and backward flow receiving signals, isolating the forward and backward flow receiving signals and selecting the forward and backward flow receiving signals. Therefore, the switching selection of the forward and backward flow detection is completed through a plurality of multiplexers, such as a plurality of switch chips, and the characteristics of channel multiplexing, receiving and transmitting isolation and energy release are provided for improving the signal to noise ratio of signals, optimizing the metering performance and further improving the measuring precision of the flowmeter.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief description will be given below of the drawings that are needed in the embodiments or the prior art descriptions, it being obvious that the drawings in the following description are some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.

FIG. 1 is a schematic diagram of an analog switch array provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of an analog switch array according to another embodiment of the present application;

FIG. 3 is a schematic diagram of an analog switch array according to another embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a comparison of the use of an analog switch array according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of an analog switch array according to another embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims of this application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be capable of operation in sequences other than those illustrated or described herein, for example. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In practical ultrasonic metrology, the excitation signal and the echo signal often differ by several orders of magnitude. Meanwhile, due to the limitation of factors such as cost, space, flow field and the like, the transducer driving circuit is mostly in a small and precise design, so that the transceiving circuit is difficult to thoroughly isolate, and therefore, the high-voltage excitation signal easily pollutes the mV or uV-level echo signal, thereby generating false waves, and causing the problems of large flow error and the like.

In order to solve the above problems, the technical concept of the present application is to complete switching selection of forward and backward flow detection by arranging a plurality of multiplexers, such as a plurality of switch chips, and the present application has the characteristics of channel multiplexing, transmit-receive isolation and energy release, so as to improve signal-to-noise ratio of signals, optimize metering performance, and further improve measurement accuracy of a flowmeter.

The technical scheme of the present application is described in detail below with specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.

Fig. 1 is a schematic diagram of an analog switch array provided in an embodiment of the present application, as shown in fig. 1, the analog switch array may include: a plurality of switching units including at least a first switching unit and a second switching unit, and a plurality of transducers including at least a first transducer and a second transducer;

the first end of the first switch chip is the third end of the first switch unit, the second end of the first switch chip is the first end of the first switch unit, the third end of the first switch chip is the sixth end of the first switch unit, and the fourth end of the first switch chip is the fifth end of the first switch unit; the first end of the second switch chip is the second end of the first switch unit, the second end of the second switch chip is the fourth end of the first switch unit, the third end of the second switch chip is the eighth end of the first switch unit, and the fourth end of the second switch chip is the seventh end of the first switch unit; the first end of the third switch chip is a third end of the second switch unit, and the second end of the third switch chip is a second end of the second switch unit; the first end of the fourth switch chip is the first end of the second switch unit, and the second end of the fourth switch chip is the fourth end of the second switch unit; the third end of the fifth switch chip is the fifth end of the second switch unit. The third end of the third switch chip is connected with the second end of the fifth switch chip; and the third end of the fourth switch chip is connected with the first end of the fifth switch chip.

In particular, the method comprises the steps of,

the first end of the first switch chip is connected with the second end of the second switch chip, the second end of the first switch chip is grounded, the third end of the first switch chip is connected with one end of the first transducer, and the fourth end of the first switch chip is connected with the second end of the third switch chip;

the other end of the first transducer is grounded; the first end of the second switch chip is grounded, the third end of the second switch chip is connected with one end of the second transducer, and the fourth end of the second switch chip is connected with the first end of the fourth switch chip; the other end of the second transducer is grounded;

the first end of the third switch chip is grounded, and the third end of the third switch chip is connected with the second end of the fifth switch chip; the second end of the fourth switch chip is grounded, and the third end of the fourth switch chip is connected with the first end of the fifth switch chip; the third end of the fifth switch chip is connected with the signal conditioning unit; the first end of the first switch chip and the second end of the second switch chip are respectively connected with the excitation generation unit;

In this embodiment, the analog switch array is applied to an ultrasonic flowmeter, and in the process of alternating measurement of forward and reverse flow of ultrasonic metering, the high-voltage excitation part and the small-signal receiving part are thoroughly isolated, and the receiving links of forward and reverse flow are also isolated through the connection relationship between the switch chips and the transducers and signal transmission; and the residual charge in the circuit after the last measurement is discharged, so that the stability of the initial state of the circuit is ensured. Meanwhile, multiplexing of the signal conditioning unit of the excitation generation unit in the forward and backward flow detection can be realized through the analog switch array, the consistency of the receiving and transmitting links is ensured, and the offset of the measurement zero point is further reduced.

According to the embodiment of the application, the plurality of switch chips and the plurality of transducers are arranged, the plurality of switch chips at least comprise a first switch chip, a second switch chip, a third switch chip, a fourth switch chip and a fifth switch chip, and the plurality of transducers at least comprise a first transducer and a second transducer; the first end of the first switch chip is connected with the second end of the second switch chip, the second end of the first switch chip is grounded, the third end of the first switch chip is connected with one end of the first transducer, and the fourth end of the first switch chip is connected with the second end of the third switch chip; the other end of the first transducer is grounded; the first end of the second switch chip is grounded, the third end of the second switch chip is connected with one end of the second transducer, and the fourth end of the second switch chip is connected with the first end of the fourth switch chip; the other end of the second transducer is grounded; the first end of the third switch chip is grounded, and the third end of the third switch chip is connected with the second end of the fifth switch chip; the second end of the fourth switch chip is grounded, and the third end of the fourth switch chip is connected with the first end of the fifth switch chip; the third end of the fifth switch chip is connected with the signal conditioning unit; the first end of the first switch chip and the second end of the second switch chip are respectively connected with the excitation generation unit; the first switch chip and the second switch chip are used for switching forward and backward flow detection and isolating the receiving and transmitting signals of the first transducer and the second transducer; the third switch chip and the fourth switch chip are used for receiving the forward and backward flow receiving signals and isolating the forward and backward flow receiving signals; the fifth switch chip is used for selecting forward and backward flow receiving signals. Therefore, the switching selection of the forward and backward flow detection is completed through a plurality of multiplexers, such as a plurality of switch chips, and the characteristics of channel multiplexing, receiving and transmitting isolation and energy release are provided for improving the signal to noise ratio of signals, optimizing the metering performance and further improving the measuring precision of the flowmeter.

In this embodiment, referring to fig. 2, fig. 2 is a schematic diagram of an analog switch array according to another embodiment of the present application. The first switch chip and the second switch chip are two-way single-pole double-throw switches, and the analog switch array in fig. 2 uses 7 groups of single-pole double-throw (Single Pole Double Throw, SPDT) switches, wherein the 1 end and the 2 end of the single-pole double-throw switch are defined as channel selection ports, and the port 3 is a common port, so that the forward and backward detection switching is realized.

Specifically, the first switch chip comprises a first single-pole double-throw switch SPDT1 and a second single-pole double-throw switch SPDT2, and the second switch chip comprises a third single-pole double-throw switch SPDT3 and a fourth single-pole double-throw switch SPDT4; wherein, SPDT1, SPDT2, SPDT3, SPDT4 and the excitation generating unit form a high-voltage excitation side.

Illustratively, port 1 of SPDT1 (here, the first channel selection port of SPDT 1) is connected to port 2 of SPDT3 (here, the second channel selection port of SPDT 3), port 2 of SPDT1 (here, the second channel selection port of SPDT 1) and port 1 of SPDT3 (here, the first channel selection port of SPDT 3) are grounded, port 3 of SPDT1 (here, the common port of SPDT 1) is connected to port 1 of SPDT2 (here, the first channel selection port of SPDT 2), port 2 of SPDT2 (here, the second channel selection port of SPDT 2) is connected to the second end of the third switch chip, port 3 of SPDT2 (here, the common port of SPDT 2) is connected to one end of transducer 1 (here, the first transducer), and the other end of transducer 1 is grounded; port 3 of SPDT3 (here, the common port of SPDT 3) is connected to port 2 of SPDT4 (here, the second channel selection port of SPDT 4), port 1 of SPDT4 (here, the first channel selection port of SPDT 4) is connected to the first end of the fourth switch chip, port 3 of SPDT4 (here, the common port of SPDT 4) is connected to one end of transducer 2 (here, the second transducer), and the other end of transducer 2 is grounded. The

ports

1 and 2 of SPDT1 and SPDT3 are connected to the excitation generating unit, respectively.

The SPDT1 and the SPDT3 are respectively used as a receiving and transmitting isolating switch of the transducer 1 and the transducer 2; SPDT2 and SPDT4 serve as the transmit/receive switching switches of transducer 1 and transducer 2, respectively.

the fifth single-pole double-throw switch is used as a switch for receiving the forward and backward flow receiving signals and isolating the forward and backward flow receiving signals.

In this embodiment, as shown in connection with fig. 2, the third switch chip includes a fifth single pole double throw switch SPDT5, where a port 1 of the SPDT5 (here, a first channel selection port of the SPDT 5) is grounded, a port 2 of the SPDT5 (here, a second channel selection port of the SPDT 5) is connected to the port 2 of the SPDT2, and a port 3 of the SPDT5 (here, a common port of the SPDT 5) is connected to the second terminal of the fifth switch chip.

In one possible design, the fourth switch chip includes a sixth single pole double throw switch; a first channel selection port of the sixth single-pole double-throw switch is used as a first end of the fourth switch chip, a second channel selection port of the sixth single-pole double-throw switch is used as a second end of the fourth switch chip, and a common port of the sixth single-pole double-throw switch is used as a third end of the fourth switch chip;

In this embodiment, as shown in connection with fig. 2, the fourth switch chip includes a sixth single pole double throw switch SPDT6, the port 2 of the SPDT6 (here, the second channel selection port of the SPDT 6) is grounded, the port 1 of the SPDT6 (here, the first channel selection port of the SPDT 6) is connected to the port 2 of the SPDT4, and the port 3 of the SPDT6 (here, the common port of the SPDT 6) is connected to the first terminal of the fifth switch chip.

The SPDT5 and the SPDT6 are used as forward and backward receiving signals and isolating switches.

In this embodiment, as shown in connection with fig. 2, the fifth switch chip includes a seventh single pole double throw switch SPDT7, where a port 1 of the SPDT7 (here, a first channel selection port of the SPDT 7) is connected to a port 3 of the SPDT6, a port 2 of the SPDT7 (here, a second channel selection port of the SPDT 7) is connected to a port 3 of the SPDT5, and a port 3 of the SPDT7 (here, a common port of the SPDT 7) is connected to the signal conditioning unit.

Wherein, SPDT7 is as a forward and backward flow received signal selector switch. The SPDT5, SPDT6, SPDT7 and the signal conditioning unit constitute a pressure receiving side.

Specifically, as shown in fig. 2, taking the transducer 1 as a transmitting end and the transducer 2 as a receiving end as an example. SPDT1 and SPDT2 communicate the excitation link through control signals, i.e. port 3 is connected to port 1, such that the excitation signals drive transducer 1. The port 3 of the SPDT3 is connected with the grounded port 1, and residual charges excited in the last measuring period in the SPDT4 are discharged; at the same time, because port 1 of SPDT3 is forced to ground, cross-talk of the excitation signal on port 2 of SPDT3 is prevented from entering SPDT4. Port 3 of SPDT4 is connected to port 1, gating the receive chain. The SPDT5 port 3 is connected with the port 1, and meanwhile, the port 1 is forcedly grounded, so that the isolation of a high-voltage excitation side and a receiving link of the transducer 1 is realized; while the residual charge received during the last measurement period in SPDT7 is discharged. SPDT6, SPDT7 will gate the respective port 3 and port 1 simultaneously, introducing the received signal into the signal conditioning unit.

It should be noted that, the design of the analog switch array is symmetrical, and when the transducer 2 is used as the transmitting end and the transducer 1 is used as the receiving end, the switch gating direction is opposite, so that the function can be realized.

Therefore, by the design of fig. 2, in the process of alternating forward and backward flow measurement of ultrasonic metering, the high-voltage excitation part and the small signal receiving part are thoroughly isolated, and the forward and backward flow receiving link is also isolated; and the residual charge in the circuit after the last measurement is discharged, so that the stability of the initial state of the circuit is ensured. Meanwhile, multiplexing of the signal conditioning unit of the excitation generation unit in the forward and backward flow detection can be realized through the analog switch array, the consistency of the receiving and transmitting links is ensured, and the offset of the measurement zero point is further reduced.

For example, see fig. 3, where U1 (here, the first switch chip) and U2 (here, the second switch chip) are a dual-path SPDT chip. Referring to fig. 2, U1 corresponds to SPDT1 and SPDT2, U2 corresponds to SPDT3 and SPDT4, U3 (here, third switching chip) corresponds to SPDT5, U4 (here, fourth switching chip) corresponds to SPDT6, U5 (here, fifth switching chip) corresponds to SPDT7, fire represents the input of the excitation unit, and ECHO represents the output signal to the signal conditioning unit. And C1, C2, C3, C4 and C5 are filter capacitors of the power supplies of the chips and are used for reducing the influence of the power supplies on signals. The CTL1 is a control signal of a switch in U1, U2, U3, U4 and U5, multiplexing of the control signal can be realized through connection design of the SPDT array, namely, the detection time sequence of the forward flow and the backward flow corresponds to the level state of the CTL, and the forward flow and the backward flow can be alternately detected through the change of the CTL, so that logic control can be realized through only 1I/O port.

The analog switch chip selected in the circuit shown in fig. 3 has the following characteristics: 1. both switch chips accord with the low-power consumption design, and the working current is only uA level. 2. The on-resistance of the two switch chips is required to be as small as possible, and meanwhile, the on-resistance has smaller temperature drift, so that the stability of a link is ensured. 3. The parasitic parameters of the ports of the two switch chips are as small as possible, so that the influence on the input and output impedance is reduced. 4. The switch isolation requirements of the two switch chips are as high as possible, so that the interference between signals can be further reduced. 5. U1 and U2 have wide applicable voltage ranges and can meet the weak voltage range from the high voltage of the excitation signal to the receiving signal.

Therefore, the switching selection of the forward and backward flow detection is completed through the multiplexers, such as the switch chips, and the device has the characteristics of channel multiplexing, receiving and transmitting isolation and energy release, so that the signal to noise ratio of signals is improved, the metering performance is optimized, and the measuring precision of the flowmeter is improved.

Specifically, referring to fig. 4, fig. 4 is a schematic diagram of a comparison between the front and rear of the analog switch array according to the embodiment of the present application. The receiving link is isolated, so that the influence of the excitation signal on the receiving link is greatly reduced, and the signal-to-noise ratio is improved; the isolation of the forward and backward flow receiving channels reduces the mutual influence of the two receiving channels, and is beneficial to improving the signal to noise ratio; during each measurement, the residual charges in the link are released, so that the initial state of the link is ensured, the multiplexing of the excitation unit and the receiving unit is realized, the symmetry of the forward and backward flow detection link is ensured, and the zero point offset is reduced; through designing the connection gating mode of the SPDT, the connection ports of the downstream and the countercurrent are symmetrical, multiplexing of the switch control I/O ports is realized, and design resources are saved.

Referring to fig. 5, fig. 5 is a schematic diagram of an analog switch array according to another embodiment of the present application; the analog switch array is applied to an ultrasonic flowmeter of differential excitation signals. The analog switch array includes: a plurality of switching units including at least a first switching unit, a second switching unit, and a third switching unit, and a plurality of transducers including at least a first transducer and a second transducer;

the first end of the first switch chip is the second end of the first switch unit, the second end of the first switch chip is the first end of the first switch unit, the third end of the first switch chip is the third end of the first switch unit, and the fourth end of the first switch chip is the fourth end of the first switch unit; the first end of the second switch chip is the sixth end of the first switch unit, the second end of the second switch chip is the fifth end of the first switch unit, the third end of the second switch chip is the eighth end of the first switch unit, and the fourth end of the second switch chip is the seventh end of the first switch unit; the first end of the third switch chip is the second end of the second switch unit, the second end of the third switch chip is the first end of the second switch unit, the third

The third end of the switch chip is the third end of the second switch unit, and the fourth 5 end of the third switch chip is the fourth end of the second switch unit; the first end of the fourth switch chip is the second switch

A sixth end of the switch unit, wherein the second end of the fourth switch chip is a fifth end of the second switch unit, the third end of the fourth switch chip is an eighth end of the second switch unit, and the fourth end of the fourth switch chip is a seventh end of the second switch unit; the first end of the fifth switch chip is

The second end of the third switch unit, the second end of the fifth switch chip is the first end of the third switch unit 0; the first end of the sixth switch chip is the fourth end of the third switch unit, the

The second end of the sixth switch chip is a third end of the third switch unit; the third end of the seventh switch chip is a fifth end of the third switch unit. The third end of the fifth switch chip is connected with the second end of the seventh switch chip; the third end of the sixth switch chip is connected with the first end of the seventh switch chip.

5 in particular, the first end of the first switching chip is connected to the first end of the third switching chip,

the second end of the first switch chip and the third end of the first switch chip are grounded, and the fourth end of the first switch chip is connected with one end of the first transducer; the first end of the second switch chip is connected with the first end of the fourth switch chip, the second end of the second switch chip is grounded, the second end of the second switch chip is connected with the first end of the fourth switch chip

The third end of the second switch chip is connected with the other end of the first transducer, and the fourth end of the second switch chip 0 sheet is connected with the second end of the fifth switch chip; the second end of the third switch chip

The third end of the third switch chip is grounded, and the fourth end of the third switch chip is connected with one end of the second transducer; the second end of the fourth switch chip is grounded, the third end of the fourth switch chip is connected with the other end of the second transducer, and the fourth end of the fourth switch chip is connected with the second transducer

The first end of the sixth switch chip is connected;

5 the first end of the fifth switch chip is grounded, and the third end of the fifth switch chip is grounded to the first end

The second ends of the seven switch chips are connected; the second end of the sixth switch chip is grounded, the third end of the sixth switch chip is connected with the first end of the seventh switch chip, the third end of the seventh switch chip is connected with the signal conditioning unit, and the first end of the first switch chip, the first end of the second switch chip, the first end of the third switch chip and the first end of the fourth switch chip are all connected with the differential 0 excitation generating unit;

In this embodiment, since the differential excitation generating unit inputs two paths of excitation signals, two paths of switches are added to isolate interference between the differential excitation signals based on the design principle of fig. 2. The switching selection of the forward and backward flow detection is completed through a plurality of multiplexers, such as a plurality of switch chips, and the forward and backward flow detection device has the characteristics of channel multiplexing, receiving and transmitting isolation and energy release, is used for improving the signal to noise ratio of signals, optimizing the metering performance and further improving the measuring precision of the flowmeter.

Illustratively, as shown in connection with fig. 5, the first switch chip includes a first single pole double throw switch SPDT1 and a second single pole double throw switch SPDT2, the second switch chip includes a third single pole double throw switch SPDT3 and a fourth single pole double throw switch SPDT4, the third switch chip includes a fifth single pole double throw switch SPDT5 and a sixth single pole double throw switch SPDT6, and the fourth switch chip includes a seventh single pole double throw switch SPDT7 and an eighth single pole double throw switch SPDT8.

Specifically, port 1 of SPDT1 (here, the first channel selection port of SPDT 1) is connected to port 1 of SPDT5 (here, the first channel selection port of SPDT 5), port 2 of SPDT1 (here, the second channel selection port of SPDT 1) is grounded, port 3 of SPDT1 (here, the common port of SPDT 1) is connected to port 1 of SPDT2 (here, the first channel selection port of SPDT 2), port 2 of SPDT2 (here, the second channel selection port of SPDT 2) is grounded, port 3 of SPDT2 is connected to one end of transducer 1 (here, the first transducer); port 1 of SPDT3 (here, the first channel selection port of SPDT 3) is connected to port 1 of SPDT7 (here, the first channel selection port of SPDT 7), port 2 of SPDT3 (here, the second channel selection port of SPDT 3) is grounded, port 3 of SPDT3 (here, the common port of SPDT 3) is connected to port 1 of SPDT4 (here, the first channel selection port of SPDT 4), port 3 of SPDT4 (here, the common port of SPDT 4) is connected to the other end of transducer 1, and port 2 of SPDT4 (here, the common port of SPDT 4) is connected to the second end of the fifth switch chip.

Port 2 of SPDT5 (here, the second channel selection port of SPDT 5) is grounded, port 3 of SPDT5 (here, the common port of SPDT 5) is connected to port 2 of SPDT6 (here, the second channel selection port of SPDT 6), port 3 of SPDT6 (here, the common port of SPDT 6) is connected to transducer 2 (here, the second transducer); port 2 of SPDT7 (here, the second channel selection port of SPDT 7) is grounded, port 3 of SPDT7 (here, the common port of SPDT 7) is connected to port 2 of SPDT8 (here, the second channel selection port of SPDT 8), port 3 of SPDT8 is connected to the other end of transducer 2, and port 1 of SPDT8 (here, the first channel selection port of SPDT 8) is connected to the first end of the sixth switching chip. Wherein, 1 port of SPDT1, 1 port of SPDT3, 1 port of SPDT5, 1 port of SPDT7 are respectively connected with the differential excitation generating unit.

Wherein, SPDT1, SPDT3, SPDT5, SPDT7 are respectively used as the receiving and transmitting isolating switch of the transducer 1 and the transducer 2; SPDT2, SPDT4, SPDT6, and SPDT8 are used as the transmission/reception switching switches of the transducer 1 and the transducer 2, respectively.

In this embodiment, as shown in fig. 5, the fifth switch chip includes a ninth single pole double throw switch SPDT9; port 1 of SPDT9 (here, the first channel selection port of SPDT 9) is grounded, port 2 of SPDT9 (here, the second channel selection port of SPDT 9) is connected to port 2 of SPDT4, and port 3 of SPDT9 (here, the common port of SPDT 9) is connected to the second terminal of the seventh switch chip.

In this embodiment, as shown in connection with fig. 5, the sixth switch chip includes a tenth single pole double throw switch SPDT10, the port 2 of the SPDT10 (here, the second channel selection port of the SPDT 10) is grounded, the port 1 of the SPDT10 (here, the first channel selection port of the SPDT 10) is connected to the port 1 of the SPDT8, and the port 3 of the SPDT10 (here, the common port of the SPDT 10) is connected to the first terminal of the seventh switch chip.

The SPDT9 and the SPDT10 are used as forward and backward flow receiving signals and isolating switches.

In this embodiment, as shown in connection with fig. 5, the seventh switch chip includes an eleventh single pole double throw switch SPDT11, the port 1 of the SPDT11 (here, the first channel selection port of the SPDT 11) is connected to the port 3 of the SPDT10, the port 2 of the SPDT11 (here, the second channel selection port of the SPDT 11) is connected to the port 3 of the SPDT9, and the port 3 of the SPDT11 (here, the common port of the SPDT 11) is connected to the signal conditioning unit.

Wherein, SPDT11 is as a forward and backward flow received signal selector switch.

The embodiment can be used for a transducer differential excitation form, and the isolation degree between excitation signals is improved. The implementation principle is similar to that of fig. 2, and will not be described here again. Note that the reference numerals of the single pole double throw switch are merely exemplary, and are not particularly limited.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An analog switch array, comprising: a plurality of switching units including at least a first switching unit and a second switching unit, and a plurality of transducers including at least a first transducer and a second transducer;

2. The analog switch array of claim 1, wherein the first switch unit comprises a first switch chip and a second switch chip, the second switch unit comprises a third switch chip, a fourth switch chip, and a fifth switch chip;

3. The analog switch array of claim 2, wherein the first and second switch chips are two-way single pole double throw switch chips, and the first switch chip comprises a first single pole double throw switch and a second single pole double throw switch, and the second switch chip comprises a third single pole double throw switch and a fourth single pole double throw switch;

a first channel selection port of the first single-pole double-throw switch is used as a first end of the first switch chip, a second channel selection port of the first single-pole double-throw switch is used as a second end of the first switch chip, a public port of the first single-pole double-throw switch is connected with the first channel selection port of a second single-pole double-throw switch, the second channel selection port of the second single-pole double-throw switch is used as a fourth end of the first switch chip, and a public port of the second single-pole double-throw switch is used as a third end of the first switch chip;

4. An analog switch array according to claim 2 or 3, wherein the third switch chip comprises a fifth single pole double throw switch; a first channel selection port of the fifth single-pole double-throw switch is used as a first end of the third switch chip, a second channel selection port of the fifth single-pole double-throw switch is used as a second end of the third switch chip, and a common port of the fifth single-pole double-throw switch is used as a third end of the third switch chip;

5. The analog switch array of claim 4, wherein the fourth switch chip comprises a sixth single pole double throw switch; a first channel selection port of the sixth single-pole double-throw switch is used as a first end of the fourth switch chip, a second channel selection port of the sixth single-pole double-throw switch is used as a second end of the fourth switch chip, and a common port of the sixth single-pole double-throw switch is used as a third end of the fourth switch chip;

6. The analog switch array of claim 5, wherein the fifth switch chip comprises a seventh single pole double throw switch; a first channel selection port of the seventh single-pole double-throw switch is used as a first end of the fifth switch chip, a second channel selection port of the seventh single-pole double-throw switch is used as a second end of the fifth switch chip, and a common port of the seventh single-pole double-throw switch is used as a third end of the fifth switch chip;

7. An analog switch array, comprising: a plurality of switching units including at least a first switching unit, a second switching unit, and a third switching unit, and a plurality of transducers including at least a first transducer and a second transducer;

8. The analog switch array of claim 7, wherein the first switch unit comprises a first switch chip and a second switch chip, the second switch unit comprises a third switch chip and a fourth switch chip, and the third switch unit comprises a fifth switch chip, a sixth switch chip, and a seventh switch chip;

9. The analog switch array of claim 8, wherein the first switch chip comprises a first single-pole double-throw switch and a second single-pole double-throw switch, the second switch chip comprises a third single-pole double-throw switch and a fourth single-pole double-throw switch, the third switch chip comprises a fifth single-pole double-throw switch and a sixth single-pole double-throw switch, and the fourth switch chip comprises a seventh single-pole double-throw switch and an eighth single-pole double-throw switch;

10. The analog switch array of claim 8 or 9, wherein the fifth switch chip comprises a ninth single pole double throw switch; a first channel selection port of the ninth single-pole double-throw switch is used as a first end of the fifth switch chip, a second channel selection port of the ninth single-pole double-throw switch is used as a second end of the fifth switch chip, and a common port of the ninth single-pole double-throw switch is used as a third end of the fifth switch chip;

11. The analog switch array of claim 10, wherein the sixth switch chip comprises a tenth single pole double throw switch; a first channel selection port of the tenth single-pole double-throw switch is used as a first end of the sixth switch chip, a second channel selection port of the tenth single-pole double-throw switch is used as a second end of the sixth switch chip, and a common port of the tenth single-pole double-throw switch is used as a third end of the sixth switch chip;

12. The analog switch array of claim 11, wherein the seventh switch chip comprises an eleventh single pole double throw switch; a first channel selection port of the eleventh single-pole double-throw switch is used as a first end of the seventh switch chip, a second channel selection port of the eleventh single-pole double-throw switch is used as a second end of the seventh switch chip, and a common port of the eleventh single-pole double-throw switch is used as a third end of the seventh switch chip;