CN219018780U - Amplifying circuit with selectable amplifying rate - Google Patents
Amplifying circuit with selectable amplifying rate Download PDFInfo
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- CN219018780U CN219018780U CN202223575635.3U CN202223575635U CN219018780U CN 219018780 U CN219018780 U CN 219018780U CN 202223575635 U CN202223575635 U CN 202223575635U CN 219018780 U CN219018780 U CN 219018780U
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Abstract
The utility model discloses an amplifying circuit with selectable amplifying power, wherein the input end of a multiplexer in the amplifying circuit is connected with the inverting input end of a first operational amplifier, the first path output end of an analog multiplexer is respectively connected with the output end of the first operational amplifier, the non-inverting input end of a second operational amplifier and the first end of a first gain resistor, the second path output end of the analog multiplexer is respectively connected with the second end of the first gain resistor and the first end of the second gain resistor, the second end of the second gain resistor is connected with a reference voltage end, the non-inverting input end of the first operational amplifier is an analog signal input end, and the output end of the second operational amplifier is an amplified signal output end. The utility model controls the conduction of the first path of output end or the second path of output end through the analog multiplexer, changes the gain resistance in the feedback loop, realizes the selection of different amplification factors, and has simple circuit structure, easy preparation and low cost.
Description
Technical Field
The utility model relates to the technical field of signal amplification, in particular to an amplifying circuit with selectable amplification factors.
Background
At present, operational amplifiers play an important role in circuits, and their application has been extended to various fields of automotive electronics, communications, consumption, etc., and will play an important role in supporting future technologies, and the types of operational amplifiers at present are many, but the amplification factors are generally fixed and not selectable. For example, if a single amplification factor is used to collect data, the collection accuracy of other level values will be affected due to the existence of multiple level values; if a narrower range is used, the acquisition accuracy can be improved, but the applicability to the range problem can be correspondingly reduced. On the premise of ensuring applicability, if the higher acquisition precision is required to be kept, different amplification factors are required to be set for different test channels so as to improve the acquisition precision. At present, an output circuit with single amplification factor is designed for different test channels, and when the test channels are more, the size and the complexity of the amplifier circuit are overlarge, so that the use requirement is difficult to meet.
Disclosure of Invention
In order to solve the technical problem that the amplification factor of the existing amplifying circuit is not selectable, from the aspect of controlling the analog multiplexer to switch and select different amplification factors, the utility model innovatively provides the amplifying circuit with the selectable amplification factors, and the analog multiplexer is used for controlling the conduction of the first path of output end or the second path of output end, so that the gain resistance in the feedback loop is changed, the selection of different amplification factors is realized, and the amplifying circuit has the advantages of simple circuit structure, small volume, easiness in preparation and low cost.
In order to achieve the technical purpose, the utility model discloses an amplifying circuit with selectable amplifying power, which comprises an analog multiplexer, a first operational amplifier, a second operational amplifier, a first gain resistor and a second gain resistor, wherein the input end of the analog multiplexer is connected with the inverting input end of the first operational amplifier, the first path output end of the analog multiplexer is respectively connected with the output end of the first operational amplifier, the non-inverting input end of the second operational amplifier and the first end of the first gain resistor, the second path output end of the analog multiplexer is respectively connected with the second end of the first gain resistor and the first end of the second gain resistor, the second end of the second gain resistor is connected with a reference voltage end, the non-inverting input end of the first operational amplifier is an analog signal input end, and the output end of the second operational amplifier is an amplified signal output end.
Further, the utility model provides an amplifying circuit with selectable amplification factors, wherein the inverting input end and the output end of the second operational amplifier are connected with a low-pass filter.
Furthermore, the amplifying circuit with the selectable amplifying power comprises an ADG409BRZ chip, wherein a DA pin and a DB pin of the ADG409BRZ chip are connected with an inverting input end of a first operational amplifier, an S3A pin and an S3B pin of the ADG409BRZ chip are connected in parallel to form a first path of output end, an S4A pin and an S4B pin of the ADG409BRZ chip are connected in parallel to form a second path of output end, and an A1 pin, an EN pin and a VDD pin of the ADG409BRZ chip are connected with 5V voltage and are grounded through a first capacitor C8 and a second capacitor C9 which are connected in parallel.
Further, the amplifying circuit with the selectable amplifying power is characterized in that the negative voltage power supply end of the first operational amplifier is grounded, and the positive voltage power supply end of the first operational amplifier is connected with 5V voltage and grounded through the third capacitor C15.
Further, the utility model relates to an amplifying circuit with selectable amplifying power, wherein the low-pass filter comprises a fourth capacitor C10, a fifth capacitor C11, a first resistor R10 and a second resistor R11, wherein a first end of the fourth capacitor C10 is respectively connected with an output end of the second operational amplifier and a first end of the first resistor R10, a second end of the fourth capacitor C10 is respectively connected with an inverting input end of the second operational amplifier and a first end of the second resistor R11, a second end of the first resistor R10 is respectively connected with a second end of the second resistor R11, a first end of the fifth capacitor C11 and a signal output end, and a second end of the fifth capacitor C11 is grounded.
Further, the utility model provides an amplifying circuit with selectable amplifying power, wherein the first operational amplifier and the second operational amplifier are replaced by an integrated double operational amplifier with the model of RS 8552.
The beneficial effects of the utility model are as follows: according to the utility model, the input end of the multiplexer is connected with the inverting input end of the first operational amplifier by arranging the analog multiplexer, the first operational amplifier and the second operational amplifier, the first path output end of the analog multiplexer is respectively connected with the output end of the first operational amplifier, the non-inverting input end of the second operational amplifier and the first end of the first gain resistor, the second path output end of the analog multiplexer is respectively connected with the second end of the first gain resistor and the first end of the second gain resistor, the second end of the second gain resistor is connected with the reference voltage end, the non-inverting input end of the first operational amplifier is an analog signal input end, and the output end of the second operational amplifier is an amplified signal output end, so that the amplifying circuit with selectable amplifying multiplying power, simple circuit structure, easy preparation and low cost is formed. When in actual use, the first path of output end is conducted through the analog multiplexer, so that the corresponding magnification is realized; the second path of output end is conducted through the analog multiplexer, the first gain resistor and the second gain resistor are connected into a feedback loop formed by the first operational amplifier, corresponding amplification factors are achieved, and then selection of two different amplification factors is achieved, so that the method is suitable for application scenes with different amplification factors. The application of the analog multiplexer does not affect the overall performance and the service life of the circuit, and has the advantages of fewer component parts, simple connection structure and small volume.
Drawings
Fig. 1 is a schematic diagram of an amplifying circuit with an optional amplifying power according to the present utility model.
Detailed Description
An amplification circuit of an alternative magnification of the present utility model is explained and illustrated in detail below with reference to the drawings.
As shown in fig. 1, the utility model discloses an amplifying circuit with selectable amplifying power, which comprises an analog multiplexer 1, a first operational amplifier 2, a second operational amplifier 3, a first gain resistor 4 (i.e. R4) and a second gain resistor 5 (i.e. R9), wherein an input end of the analog multiplexer 1 is connected with an inverting input end of the first operational amplifier 2, a first path output end of the analog multiplexer 1 is respectively connected with an output end of the first operational amplifier 2, a non-inverting input end of the second operational amplifier 3 and a first end of the first gain resistor 4, a second path output end of the analog multiplexer 1 is respectively connected with a second end of the first gain resistor 4 and a first end of the second gain resistor 5, a second end of the second gain resistor 5 is connected with a reference voltage end, a non-inverting input end of the first operational amplifier 2 is an analog signal input end, and an output end of the second operational amplifier 3 is an amplified signal output end.
In actual use, the second operational amplifier 3 performs impedance transformation by performing voltage follow-up on the first operational amplifier 2, so that the influence of the input characteristic of the rear load on the output voltage waveform can be prevented. The first path of output end is conducted through the analog multiplexer 1, and the second operational amplifier 3 is used as a follower to realize corresponding amplification factor; the second path of output end is conducted through the analog multiplexer 1, the first gain resistor 4 and the second gain resistor 5 are connected into a feedback loop formed by the first operational amplifier 2, corresponding amplification factors are realized, and then selection of two different amplification factors is realized, so that the method is suitable for application scenes with different amplification factors. The application of the analog multiplexer does not affect the overall performance and the service life of the circuit, and has the advantages of fewer component parts, simple connection structure and small volume.
In an embodiment of the utility model, the inverting input and output of the second operational amplifier 3 are connected with a low pass filter. The low-pass filter can be used for preliminarily removing the alternating current component with higher frequency introduced by the measuring end, and the ADC overflow caused by the condition that the input end is overvoltage due to the alternating current component is prevented from being input at the rear end. More specifically, the low-pass filter includes a fourth capacitor C10, a fifth capacitor C11, a first resistor R10 and a second resistor R11, where a first end of the fourth capacitor C10 is connected to an output end of the second operational amplifier 3 and a first end of the first resistor R10, a second end of the fourth capacitor C10 is connected to an inverting input end of the second operational amplifier 3 and a first end of the second resistor R11, a second end of the first resistor R10 is connected to a second end of the second resistor R11, a first end of the fifth capacitor C11 and a signal output end, and a second end of the fifth capacitor C11 is grounded. The capacitance value of the four capacitors C10 is 10nF, the capacitance value of the fifth capacitor C11 is 100nF, the resistance value of the first resistor R10 is 100 omega, the resistance value of the second resistor R11 is 5.1KΩ, and the RC low-pass filter with the cutoff frequency of 1KHz is formed through the connection relation.
In an embodiment of the present utility model, the analog multiplexer 1 preferably uses an ADG409BRZ chip, the DA pin and the DB pin of the ADG409BRZ chip are connected to the inverting input terminal of the first operational amplifier 2, the S3A pin and the S3B pin of the ADG409BRZ chip are connected in parallel to form a first output terminal, the S4A pin and the S4B pin of the ADG409BRZ chip are connected in parallel to form a second output terminal, and the A1 pin, the EN pin and the VDD pin of the ADG409BRZ chip are connected to 5V voltage and are grounded through a first capacitor C8 and a second capacitor C9 connected in parallel. More specifically, the first gain resistor R4 is set to 18kΩ, the second gain resistor R9 is set to 2kΩ, and the voltage value at the reference voltage terminal to which the second gain resistor R9 is connected is set to 2.5V. The DA pin and the DB pin of the ADG409BRZ chip are output ends, and the two output ends are connected in parallel, so that the influence of the internal resistance of the analog switch is reduced; the EN pin of the ADG409BRZ chip is an enabling end and is equivalent to a main switch; the S3A pin and the S3B pin of the ADG409BRZ chip form a path of switch unit, and the S4A pin and the S4B pin of the AD G409BRZ chip form a path of switch unit. As shown in fig. 1, the ADG409BRZ chip has four-way switches, and the novel embodiment only uses two ways; the A0 pin and the A1 pin of the ADG409BR Z chip are used as selection ends, the first path of output end or the second path of output end is selected to be conducted by controlling the level of the A0 pin of the ADG409BRZ chip, and the gain resistor is connected into the feedback loop of the first operational amplifier 2. When the first path of output end is conducted, the output end of the first operational amplifier 2 is in short circuit with the inverting input end, and the second operational amplifier 3 is used as a follower, so that the analog signal can be amplified by 1 time; when the second output end is conducted, the first gain resistor R4 and the second gain resistor R9 are connected into the feedback loop, the voltage division point of the first gain resistor R4 and the second gain resistor R9 is stabilized to be the same as the voltage value of the output point, so that the output is required to reach 10 times of the input value, and further the analog signal is amplified by 10 times.
In an embodiment of the present utility model, the negative voltage supply terminal of the first operational amplifier 2 is grounded, the positive voltage supply terminal of the first operational amplifier 2 is connected to 5V voltage and grounded through the third capacitor C15, the capacitance value of the third capacitor C15 is 4.7uF, and the third capacitor C15 acts as a coupling capacitor to perform a voltage stabilizing filtering function, so as to ensure the stability of the supply voltage of the first operational amplifier 2.
In order to further reduce the overall size of the amplifying circuit and reduce the occupied space, the first operational amplifier 2 and the second operational amplifier 3 are replaced with integrated dual operational amplifiers which are RS 8552.
In the present utility model, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present specification, a description referring to the terms "present embodiment," "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present utility model, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
The above description is only of the preferred embodiments of the present utility model, and is not intended to limit the utility model, but any modifications, equivalents, and simple improvements made within the spirit of the present utility model should be included in the scope of the present utility model.
Claims (6)
1. An amplification circuit with selectable amplification factors, which is characterized in that: the analog multiplexer is characterized by comprising an analog multiplexer, a first operational amplifier, a second operational amplifier, a first gain resistor and a second gain resistor, wherein the input end of the analog multiplexer is connected with the inverting input end of the first operational amplifier, the first path output end of the analog multiplexer is respectively connected with the output end of the first operational amplifier, the non-inverting input end of the second operational amplifier and the first end of the first gain resistor, the second path output end of the analog multiplexer is respectively connected with the second end of the first gain resistor and the first end of the second gain resistor, the second end of the second gain resistor is connected with a reference voltage end, the non-inverting input end of the first operational amplifier is an analog signal input end, and the output end of the second operational amplifier is an amplified signal output end.
2. The selectable magnification amplifying circuit according to claim 1, wherein: and the inverting input end and the output end of the second operational amplifier are connected with a low-pass filter.
3. The selectable magnification amplifying circuit according to claim 2, wherein: the analog multiplexer comprises an ADG409BRZ chip, wherein a DA pin and a DB pin of the ADG409BRZ chip are connected with an inverting input end of a first operational amplifier, an S3A pin and an S3B pin of the ADG409BRZ chip are connected in parallel to form a first path of output end, an S4A pin and an S4B pin of the ADG409BRZ chip are connected in parallel to form a second path of output end, and an A1 pin, an EN pin and a VDD pin of the ADG409BRZ chip are connected into 5V voltage and are grounded through a first capacitor C8 and a second capacitor C9 which are connected in parallel.
4. A selectable magnification amplifying circuit according to claim 3 and wherein: the negative voltage power supply end of the first operational amplifier is grounded, and the positive voltage power supply end of the first operational amplifier is connected with 5V voltage and grounded through a third capacitor C15.
5. The selectable magnification amplifying circuit according to claim 2, wherein: the low-pass filter comprises a fourth capacitor C10, a fifth capacitor C11, a first resistor R10 and a second resistor R11, wherein the first end of the fourth capacitor C10 is respectively connected with the output end of the second operational amplifier and the first end of the first resistor R10, the second end of the fourth capacitor C10 is respectively connected with the inverting input end of the second operational amplifier and the first end of the second resistor R11, the second end of the first resistor R10 is respectively connected with the second end of the second resistor R11 and the first end of the fifth capacitor C11 and the signal output end, and the second end of the fifth capacitor C11 is grounded.
6. The selectable magnification amplifying circuit according to claim 1, wherein: the first operational amplifier and the second operational amplifier are replaced by an integrated dual operational amplifier with the model of RS 8552.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223575635.3U CN219018780U (en) | 2022-12-30 | 2022-12-30 | Amplifying circuit with selectable amplifying rate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223575635.3U CN219018780U (en) | 2022-12-30 | 2022-12-30 | Amplifying circuit with selectable amplifying rate |
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| Publication Number | Publication Date |
|---|---|
| CN219018780U true CN219018780U (en) | 2023-05-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223575635.3U Active CN219018780U (en) | 2022-12-30 | 2022-12-30 | Amplifying circuit with selectable amplifying rate |
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| CN (1) | CN219018780U (en) |
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2022
- 2022-12-30 CN CN202223575635.3U patent/CN219018780U/en active Active
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