CN218976582U - Novel nine-level inverter device - Google Patents

Novel nine-level inverter device Download PDF

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Publication number
CN218976582U
CN218976582U CN202222689974.8U CN202222689974U CN218976582U CN 218976582 U CN218976582 U CN 218976582U CN 202222689974 U CN202222689974 U CN 202222689974U CN 218976582 U CN218976582 U CN 218976582U
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capacitor
switching tube
tube
emitter
collector
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CN202222689974.8U
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李文娟
梁树威
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Harbin University of Science and Technology
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Harbin University of Science and Technology
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The utility model discloses a novel nine-level inverter device which comprises a direct current power supply, ten insulated gate bipolar transistors, eight diodes, three capacitors and a load, wherein the capacitors are connected in parallel with the direct current power supply, so that the problem of continuous offset of capacitor voltage in the traditional inverter is solved, and the control difficulty is reduced. Because the capacitor is connected with the load in series in the circuit, the problems of lower output level number and larger output waveform distortion rate of the inverter in the traditional circuit can be solved. Since the discharge time of the capacitor is short, the voltage ripple is small. The circuit ensures that the inverter can normally and stably output nine levels, so that the inverter system device has higher reliability and safety.

Description

Novel nine-level inverter device
Technical Field
The utility model relates to the field of inverters, in particular to a novel nine-level inverter device.
Background
At present, due to the shortage of fossil fuels in the world, the utilization rate of energy sources has become an important link of energy source use, and due to the lower output level number of the traditional inverter, the output waveform distortion rate of the traditional inverter is larger. Therefore, the multi-level inverter generates a plurality of levels during normal operation by virtue of the unique advantages thereof, thereby reducing the distortion rate of the harmonic waves. The multi-level inverter has the advantages of low harmonic distortion rate of output voltage, high output electric energy quality and smaller output filter requirement, and obviously better development future exists at present in the absence of energy sources.
Disclosure of Invention
The utility model aims to overcome the defects of the prior art, and provides a novel nine-level inverter device which realizes the output of nine different voltages.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
the circuit provided by the utility model comprises a direct-current power supply and a first capacitor C 1 A second capacitor C 2 Third capacitor C 3 Eight diodes, a first switch tube S 1 Second switch tube S 2 Third switch tube S 3 Fourth switching tube S 4 Fifth switch tube S 5 Sixth switching tube S 6 Seventh switching tube S 7 Eighth switching tube S 8 Ninth switch tube S 9 Tenth switch tube S 10 Load.
Seventh switching tube S 7 Eighth switching tube S 8 Ninth switch tube S 9 Tenth switch tube S 10 The H bridge inverter connection mode is formed.
Positive electrode of DC power supply output side and anode of diode D, first switch tube S 1 Collector of (a), third switching tube S 3 Collector of (a) and fifth switching tube S 5 Is connected with the collector of the capacitor; negative pole of DC power supply output side and second switch tube S 2 Emitter, fourth switching tube S 4 Emitter, sixth switching tube S 6 Emitter of (a) and eighth switching tube S 8 Emitter of (d) and tenth switching tube S 10 Is connected to the emitter of (c).
First capacitor C 1 Cathode of diode D, and seventh switching tube S 7 Is connected with the collector and the ninth switching tube S 9 Is connected to the collector of the (c).
The positive electrode of the second capacitor C2 and the first capacitor C 1 Is connected with the negative electrode of the first switch tube S 1 Emitter of (a) and second switching tube S 2 Is connected with the collector of the capacitor; the cathode of the second capacitor C2 and the third capacitor C 3 Positive electrode of (a), third switch tube S 3 Emitter of (a) and fourth switching tube S 4 Is connected to the collector of the (c).
Third capacitor C 3 Is connected with the negative pole of the fifth switch tube S 5 Emitter of (d) and sixth switching tube S 6 Is connected to the collector of the (c).
Further, a first capacitor C 1 A value of (2), a second capacitor C 2 Is of the value of (and) and a third capacitor C 3 Is equal in value.
Further, the switch transistors are all insulated gate bipolar transistors.
Further, a first switching tube S 1 Fourth switching tube S 4 Sixth switching tube S 6 The reverse voltage blocking capability is provided because no anti-parallel diode is provided.
Further, the DC power supply can be connected with the second switch tube S through the diode D 2 To the first capacitor C 1 And (5) charging.
Further, the DC power supply can pass through the first switching tube S 1 And a fourth switching tube S 4 To the second capacitor C 2 And (5) charging.
Further, the DC power supply can pass through the third switching tube S 3 And a sixth switching tube S 6 To the third capacitor C 3 And (5) charging. Compared with the prior art, the practical circuit has the advantages that: the inverter topology has the advantages of being capable of outputting nine levels, low in output voltage harmonic content, high in output electric energy quality and capable of needing smaller output filters, and the efficiency of the inverter can be improved.
Drawings
Fig. 1 shows a circuit structure of the utility model.
Fig. 2-11 are mode diagrams of operation of the nine-level inverter during positive and negative half cycles.
Detailed Description
The utility model is further described below with reference to the accompanying drawings. Other details that are not germane to the present utility model have been omitted for clarity and conciseness. It is further understood that the following processes or symbols, unless otherwise indicated, are all understood or effected by those skilled in the art in view of the prior art.
The circuit structure of the utility model is shown in fig. 1, and for the convenience of analysis of the circuit, the devices in the circuit structure are all regarded as ideal devices.
Fig. 2-11 are schematic diagrams of the nine-level inverter circuit in a time period, in which the circuit components and connection lines, which are not shown in fig. 1, are turned off for better clarity of circuit representation.
The inverter output voltage is divided into positive and negative half periods.
During the positive half cycle.
Modality 1: in this state, the seventh switching tube S 7 Ninth switch tube S 9 Conducting, outputting voltage V ac =0. At the same time, a second switching tube S 2 Conducting with diode D to make first capacitor C 1 In parallel with the DC source, a first capacitor C 1 Charging about V dc 。
Modality 2: in this state, the seventh switching tube S 7 Tenth switch tube S 10 On, the output voltage is provided by a DC power supply, and the output voltage V ac ＝V dc . At the same time, a second switching tube S 2 Conduction and diode D conduction cause the first capacitor C 1 In parallel with the DC source, a first capacitor C 1 Charging about V dc 。
Modality 3: in this state, the first switching tube S 1 Seventh switching tube S 7 Tenth switch tube S 10 Conducting, the output voltage is formed by a DC power supply and a first capacitor C 1 Commonly provide, output voltage V ac ＝2V dc . At the same time, fourth switching tube S 4 Is conducted to a first switch tube S 1 A second capacitor C 2 And a DC source forming a loop, a second capacitor C 2 Charging about V dc 。
Modality 4: in this state, the third switching tube S 3 Seventh switching tube S 7 Tenth switch tube S 10 Turned on, the output voltage is controlled by a DC power supply, a first capacitor C 1 Second capacitor C 2 Commonly provide, output voltage V ac ＝3V dc . At the same time, a sixth switching tube S 6 Is conducted to a third switch tube S 3 Third capacitor C 3 And a DC source form a loop, a third capacitor C 3 Charging about V dc 。
Modality 5: in this state, the fifth switching tube S 5 Seventh switching tube S 7 Tenth switch tube S 10 Turned on, the output voltage is controlled by a DC power supply, a first capacitor C 1 A second capacitor C 2 Third capacitor C 3 Commonly provide, output voltage V ac ＝4V dc 。
During the negative half cycle.
Modality 6: in this state, the eighth switching tube S 8 Tenth switch tube S 10 Conducting, outputting voltage V ac =0. At the same time, a second switching tube S 2 Conducting with diode D to make first capacitor C 1 In parallel with the DC source, a first capacitor C 1 Charging about V dc 。
Modality 7: in this state, the eighth switching tube S 8 Ninth switch tube S 9 On, the output voltage is provided by a DC power supply, and the output voltage V ac ＝-V dc . At the same time, a second switching tube S 2 Conduction and diode D conduction cause the first capacitor C 1 In parallel with the DC source, a first capacitor C 1 Charging about V dc 。
Modality 8: in this state, the first switching tube S1 and the eighth switching tube S 8 Ninth switch tube S 9 Conducting, the output voltage is formed by a DC power supply and a first capacitor C 1 Commonly provide, output voltage V ac ＝-2V dc . At the same time, fourth switching tube S 4 Is conducted to a first switch tube S 1 A second capacitor C 2 And a DC source forming a loop, a second capacitor C 2 Charging about V dc 。
Modality 9: in this state, the third switching tube S 3 Eighth switching tube S 8 Ninth switch tube S 9 Turned on, the output voltage is controlled by a DC power supply, a first capacitor C 1 Second capacitor C 2 Commonly provide, output voltage V ac ＝-3V dc . At the same time, a sixth switching tube S 6 Is conducted to a third switch tube S 3 Third capacitor C 3 And a DC source form a loop, a third capacitor C 3 Charging about V dc 。
Modality 10: in this state, the fifth switching tube S 5 Eighth switching tube S 8 Ninth switch tube S 9 Turned on, the output voltage is controlled by a DC power supply, a first capacitor C 1 A second capacitor C 2 Third capacitor C 3 Commonly provide, output voltage V ac ＝-4V dc 。

Claims (5)

1. A novel nine-level inverter device is characterized by comprising a direct current power supply, ten insulated gate bipolar transistors, eight diodes, three capacitors and a load, wherein a seventh switching tube S 7 Eighth switching tube S 8 Ninth switch tube S 9 Tenth switch tube S 10 Forming an H-bridge inverter connection mode; positive electrode of DC power supply output side and anode of diode D, first switch tube S 1 Collector of (a), third switching tube S 3 Collector of (a) and fifth switching tube S 5 Is connected with the collector of the capacitor; negative pole of DC power supply output side and second switch tube S 2 Emitter, fourth switching tube S 4 Emitter, sixth switching tube S 6 Emitter of (a) and eighth switching tube S 8 Emitter of (d) and tenth switching tube S 10 Emitter of the first capacitor C 1 Cathode of diode D, and seventh switching tube S 7 Is connected with the collector and the ninth switching tube S 9 Is connected with the collector of the capacitor; second capacitor C 2 Positive electrode of (C) and first capacitor C 1 Is connected with the negative electrode of the first switch tube S 1 Emitter of (a) and second switching tube S 2 Is connected with the collector of the capacitor; second capacitor C 2 Negative electrode of (C) and third capacitor C 3 Is of (3)Pole, third switching tube S 3 Emitter of (a) and fourth switching tube S 4 Is connected with the collector of the capacitor; third capacitor C 3 Is connected with the negative pole of the fifth switch tube S 5 Emitter of (d) and sixth switching tube S 6 Is connected to the collector of the (c).
2. A novel nine-level inverter device according to claim 1, wherein the capacitor is charged in parallel with the dc power source and then connected in series when connected to the load.
3. A novel nine-level inverter apparatus according to claim 1, wherein said first capacitor C 1 A value of (2), a second capacitor C 2 And a third capacitor C 3 Is equal in value.
4. A novel nine-level inverter apparatus according to claim 1, wherein said first capacitor C 1 A second capacitor C 2 Third capacitor C 3 Is maintained at the voltage of the dc power supply.
5. The novel nine-level inverter device according to claim 1, wherein the switching transistors are all insulated gate bipolar transistors.
CN202222689974.8U 2022-10-13 2022-10-13 Novel nine-level inverter device Active CN218976582U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202222689974.8U CN218976582U (en) 2022-10-13 2022-10-13 Novel nine-level inverter device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202222689974.8U CN218976582U (en) 2022-10-13 2022-10-13 Novel nine-level inverter device

Publications (1)

Publication Number Publication Date
CN218976582U true CN218976582U (en) 2023-05-05

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Application Number Title Priority Date Filing Date
CN202222689974.8U Active CN218976582U (en) 2022-10-13 2022-10-13 Novel nine-level inverter device

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CN (1) CN218976582U (en)

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