CN2189757Y

CN2189757Y - Automatic bell controllor for school

Info

Publication number: CN2189757Y
Application number: CN 93223838
Authority: CN
Inventors: 黄旭晶
Original assignee: Individual
Current assignee: Individual
Priority date: 1993-01-15
Filing date: 1993-08-29
Publication date: 1995-02-15
Anticipated expiration: 2003-08-29

Abstract

The utility model provides an automatic bell controller for schools, which is suitable for the use of schools. The controller can simultaneously store 4 pieces of work schedule and can output more than seven ringing signals; the utility model is also provided with the bell stopping function on Sundays, particularly on the evening of Saturdays to the afternoon of Sundays; a build-in cell for electricity breaking use maintains the operation of the time and protect the storing data; the electric consumption is 1 to 2 MA, after the electricity supplying is restored, the utility model can automatically entering normal working without the adjustment of people; the utility model is mainly composed of the circuits of anoscillation frequency division, a time counting decode display, work schedule storage, a work schedule change, an alarm clock signal generating, a Sunday ring stopping, etc.

Description

Automatic bell controllor for school

The utility model relates to the bell clock self-actuated controller, the particularly self-actuated controller of school's bell clock of a kind of daily schedule.Belong to electronic technology field.

Present automatic bell clock controller is mainly by vibration, frequency dividing circuit, time counting, decoding display circuit, and daily schedule coding storage circuit, bell clock signal generation circuit and output circuit constitute.Disclosed as patent documentation: CN2092774U, CN2031117U, 91 years 11 phases of CN2039859U and " CYBERSPACE ", 27 pages of various bell clock controllers that reach " radio " 92 years 7 phases, 33 pages of introductions all had following weak point:

1, school custom the daylong daily schedule list in announcement in the form and by execution.Present various bell clock controller can only store the content (hereinafter to be referred as timetable) of a daily schedule.Because the variation of time length round the clock in each season, general school all needs for each issue to change the daily schedule twice or thrice, this will change timetable twice or thrice, will be when changing timetable after memory Central Plains waiting time table is wiped the daily schedule, could enroll new timetable again.

2, school's bell clock signal should divide: " giving a lesson ", step down, " preparation ", " gymnastics ", " classes are over ", " getting up " reach " going to bed " totally seven kinds.Present various bell clock controller has only two or three kind of bell clock signal, is not suitable for school and uses.

3, can not stop bell automatically Sun., bothering others has a rest or work, particularly part school shifts Sun. evening for the treatment student goes home to come and go the road weekend onto reviewing one's lessons by oneself evening on Saturday, it is loud that this just requires the bell clock not review one's lessons by oneself in evening on Saturday, do not ring daytime on Sun., and review one's lessons by oneself sound in evening, present various bell clock controllers do not have this kind function.

The purpose of this utility model is to provide a kind of automatic bell clock controller with following three new functions.

1, can store 4 timetables simultaneously, and can change timetable by automatic or manual.

2, can export bell clock signal more than 7 kinds or 7 kinds.

3, have four kinds of working methods for selecting for use.(four kinds of working methods are meant the bell clock:

(1) when all ring, when (2) do not ring, and (3) whole day on Sunday is not rung, and review one's lessons by oneself (4) evening on Saturday to daytime on Sun. and do not ring.

Daily schedule provided by the utility model, automatic bell clock controller was realized by following scheme:

1, described daily schedule memory except that 11 address wires of joining with time counting circuit, also has two address wires to open address wire (opening address wire and page address line same meaning) as 4 timetables.Open address wire for these two and link to each other, constitute the replacing system of timetable with timetable replacing circuit.

2, described daily schedule memory has three or four data lines to link to each other with bell clock signal generation circuit, constitutes the bell clock signal system more than 7 kinds or 7 kinds.

3, the chip select pin of described daily schedule memory links to each other with four kinds of working methods, constitutes four kinds of working method systems.

Daily schedule bell clock controller provided by the utility model can store a timetable simultaneously, needn't wipe old writing newly when changing timetable.More rich bell clock signal is arranged.Automatically stop bell Sun., can not bother others.Programming is directly perceived, and is easy to use.

The explanation of accompanying drawing drawing:

Fig. 1, the utility model theory diagram.

Fig. 2, timetable are changed circuit theory diagrams.

Fig. 3, be linked to be timetable with switch and change circuit theory diagrams.

Fig. 4, bell clock signal generation circuit theory diagrams.

Fig. 5, replace bell clock signal generation circuit theory diagrams with musical film or language sheet.

Fig. 6, four kinds of working method circuit theory diagrams.

The contrast accompanying drawing is described in further detail embodiment of the present utility model below.

Fig. 1, theory diagram of the present utility model, the utility model are mainly counted by second, branch, time, the decoding display circuit, and daily schedule coding storage circuit, timetable is changed circuit, bell clock signal generation circuit, four kinds of formations such as working method circuit.Wherein daily schedule coding storage circuit comprises coding circuit, decoding display circuit and daily schedule memory, the address code of daily schedule memory by minute, the time counting circuit provide.

Timetable is changed circuit and is seen Fig. 2.Be by week counting circuit CC4017, frequency dividing circuit CC4017, reversible counting circuit, 2-4 line decoding scheme and K switch 1K2 form.The course of work is as follows: the Q of week on Sun. counting circuit CC4017 weekly ₀The output high level is counted to frequency dividing circuit, if the resetting pin R and the Q of frequency dividing circuit ₇Join, when frequency dividing circuit count down to for the 8th week, frequency dividing circuit resetted, its Q ₀The output high level is given the input pin CP of reversible counting circuit, reciprocal circuit counting, its Q ₀Q ₁The numerical value or the variation that added deduct formed, two numerical value of opening address wire (A) of daily schedule memory also change thereupon, and this has just realized the automatic replacing of timetable.Per 7 weeks are changed once.Change the contact of frequency dividing circuit R pin, can change the replacement cycle.K ₁Be manually to change button, click K ₁, make the reversible counting circuit count equally, thereby realize manually changing.K ₂Be elongated by weak point, and the fall semester is established by long this regurgitation phenomenon that shortens for adapting to the Lent term time on daytime.For example Lent term connects positive supply to the UD pin of reversible counting circuit and makes plus coujnt, the fall semester then connects the negative counting that subtracts, to guarantee that the timetable of changing is adapted to season at that time, performed at that time is which timetable is shown by luminotron by the decoding of 2--4 line decoding scheme.

The replacing of daily schedule also can be thrown two knife-like switches by four and is formed by connecting, see Fig. 3, when work and rest two of the time memory open addresses (A) respectively with (1), (2) of two knife-like switches, (3), when (4) each contact joins respectively, the the the 1st, the 2nd, the 3rd, the 4th timetable can more swap out respectively.

Bell clock signal generation circuit is seen Fig. 4, is made up of bell clock signal memory counting circuit second, and bell clock signal memory can be RAM and ROM, the Q of 6 address wires of bell clock signal memory and second counting circuit ₀To Q ₅Link to each other respectively, utilize second counting circuit to make the generator of bell clock signal memory address; Bell clock signal memory also has 3 address wires (A) to link to each other respectively with 3 data lines (I/O) of daily schedule memory, sector address (with the page address same meaning) line as bell clock signal, the storage capability of bell clock signal is divided into 8 sections, every section can be stored a kind of bell clock signal, can store 8 kinds of bell clock signals like this, wherein one section is empty, in fact can store 7 kinds of bell clock signals.Bell clock signal is to take place like this: bell clock signal memory is read with the speed of a unit of per second, relay adhesive when data pin (D) is 1, bell ring, then opposite when (D) is 0, if (D) be three 1 continuously, bell ring three seconds, become a long sound, if (D) be one 1, bell ring one second, become a short sound, the long sound of the tinkle of bells, short sound come to this and form.The bell clock signal of for example " giving a lesson " is two long weak points, class period then, 3 data lines (I/O) of daily schedule memory are exported 001 address code to 3 sector address lines of bell clock signal memory, chosen the bell clock signal of giving a lesson, the data pin (D) of memory is the 1st, 2, export three 13 seconds continuously, bell rang three seconds continuously, one 0 of output in the 4th second, and bell stopped one second, the 5th, 6, exported three 1 again continuously in 7 seconds, bell rang three seconds again continuously, exported one 0 again on the 8th second, and bell stopped one second, one 1 of output in the 9th second, bell ring one second, the 10th second to 59 seconds (D) exports 0 always, and bell has not rung.Bell clock signal comes to this and takes place.Enroll in the corresponding memory cell of daily schedule memory with the sector address sign indicating number of 8 lines-3 line coding circuit, show with luminotron by the decoding of 3 lines-8 line decoding scheme simultaneously bell clock signal.

Bell clock signal generation circuit also can replace with musical film or language sheet, and the circuit theory sketch is seen Fig. 5.Form by musical film or language sheet and note amplifier.A head who is selected in 8 songs by 3 data lines (I/O) of daily schedule memory is fixed as certain bell clock signal.The daily schedule memory also has a data line (I/O) to link to each other with the trigger end of musical film, triggers the musical film starting.The music of musical film output is broadcasted with loudspeaker after note amplifier amplifies.

The circuit theory diagrams of four kinds of working methods are seen Fig. 6, are by four throw switches, week counting circuit, the time counting circuit and two Sheffer stroke gates and not gate form.As seen from the figure: be with four throw switches change the daily schedule memory chip select pin (

) contact realize, chip select pin (

) if connect power-, then selected, which day all rings bell, if just connecing power supply, then which day bell does not ring, if meet (the Q of week counting circuit ₀), then Sun., bell did not ring, if connect the output terminal of door 4, then after 18 o'clock Saturday to 18 o'clock Sun. bell do not ring.The course of work of logic gates is as follows: 18 o'clock every days, (A), (B) pin at back door 1 just were high level 1 simultaneously, thereby 18 o'clock every days Qianmen 2 (B) pin be low level 0, (A) pin of door 3 is a high level 1, (B) pin at 18 o'clock back doors 2 is a high level 1, and (A) pin of door 3 is a low level 0.Following table is the logical table of door 2, door 3, door 4.

Door

Door 2

Door 3

Door 4

The time pin

A

B

A

B

A

B

Q

Between number

Monday is to Friday

0

X

0

1

0

Before 18 o'clock Saturday	1	0	1	0	1	1	0
								After 18 o'clock Saturday	1	1	0	0	0	1	1
Before 18 o'clock Sun.	0	0	1	1	1	0	1
								After 18 o'clock Sun.	0	1	0	1	1	1	0

It can be seen from the table only after 18 o'clock Saturday and Sun. 18 o'clock Qianmens 4 output terminal just be high level (1), thereby during this period of time the daily schedule memory is not selected, bell is loud.

Four kinds of working methods are for the bell clock, be to realize by the chip select pin of the circuit of four kinds of working methods control daily schedule memory, if control the chip select pin of bell clock signal memory with four kinds of working method circuit, has this kind function too, if, no longer be subjected to the restriction of this circuit with daily schedule during other timing controlled of memory double as.

Four kinds of working methods also can only be established a kind of or two or three kind in a machine, to reduce cost.

Claims

1, a kind of mainly by vibration, frequency dividing circuit, time counting, decoding, display circuit, the automatic bell clock controller of school's daily schedule that the daily schedule storage circuit is formed is characterized in that:

(1) the daily schedule memory also has two addresses to be connected with the replacing circuit of daily schedule;

(2) the daily schedule memory has three to four data lines (I/O) and bell clock signal generation circuit to join;

The chip select pin (CS) of (3) four kinds of working method circuit and daily schedule memory joins.

2, automatic bell clock controller according to claim 1, it is characterized in that daily schedule change circuit by week counting, frequency dividing circuit and counting circuit and switch form.

3, automatic bell clock controller according to claim 1 is characterized in that daily schedule changes circuit and also can throw two knife-like switches with four and form.

4, automatic bell clock controller according to claim 1 is characterized in that bell clock signal generation circuit, is made up of ram memory or ROM and counting circuit.

5, automatic bell clock controller according to claim 1 is characterized in that bell clock signal generation circuit, it is characterized in that also can being made up of musical film or language sheet.

6, automatic bell clock controller according to claim 1 is characterized in that four kinds of working method circuit, by week counting circuit, timing circuit, two Sheffer stroke gates and NOT gate logic circuit form.

7, automatic bell clock controller according to claim 1 is characterized in that four kinds of working method circuit, also can be connected with the chip select pin of bell clock memory.

8, automatic bell clock controller according to claim 1 is characterized in that four kinds of working method circuit, can have only wherein a kind of or two or three kind.