CN218958916U

CN218958916U - DVB signal maximum value tracking receiving plate

Info

Publication number: CN218958916U
Application number: CN202221863600.7U
Authority: CN
Inventors: 张诚玮
Original assignee: Chengdu Tianmao Technology Co ltd
Current assignee: Chengdu Tianmao Technology Co ltd
Priority date: 2022-07-19
Filing date: 2022-07-19
Publication date: 2023-05-02
Anticipated expiration: 2032-07-19

Abstract

The utility model discloses a DVB signal maximum tracking receiving plate, which comprises a receiving unit and a monitoring processing unit; the receiving unit comprises a band-pass filter, an AGC intermediate frequency amplifier, an A/D converter and an FPGA, wherein a signal input end of the band-pass filter is externally connected with a downlink signal, a signal output end of the band-pass filter is connected with a first signal input end of the AGC intermediate frequency amplifier, a signal output end of the AGC intermediate frequency amplifier is connected with a signal input end of the A/D converter, a signal output end of the A/D converter is connected with a signal input end of the FPGA, a signal output end of the FPGA is connected with a signal input end of the monitoring processing unit through a serial interface, and the receiving unit further comprises a DSP, and a data bus of the DSP is connected with an address bus and the FPGA.

Description

DVB signal maximum value tracking receiving plate

Technical Field

The utility model relates to the technical field of communication, in particular to a DVB signal maximum tracking receiving plate.

Background

In the signals transmitted by the satellites, whether the tracking system is aligned with the satellites can be judged through the intensity of communication signals, and the satellites can adopt the DVB modulation mode for signal transmission at present, namely whether the satellites are aligned with the satellites is judged through the DVB demodulation signal intensity, so that the maximum value of the DVB signals is required to be tracked and received for ensuring the signal tracking effect, and therefore, the maximum value tracking receiving plate of the DVB signals has very important practical significance.

Disclosure of Invention

The utility model aims to provide a DVB signal maximum tracking receiving plate, which is used for carrying out AGC amplification, correlated and uncorrelated AGC, frequency guidance, sideband error locking prevention, carrier capturing and tracking on a received 70MHz signal, normalizing and detecting a downlink channel tracking signal to output an AGC voltage signal, respectively communicating with a monitoring extension set and a servo extension set through a serial port circuit, and sending information such as AGC voltage, locking indication, state indication and the like to the monitoring extension set and the servo extension set.

In order to solve the technical problems, the utility model adopts the following scheme:

a DVB signal maximum value tracking receiving board comprises a receiving unit and a monitoring processing unit; the receiving unit comprises a band-pass filter, an AGC intermediate frequency amplifier, an A/D converter and an FPGA, wherein a signal input end of the band-pass filter is externally connected with a downlink signal, a signal output end of the band-pass filter is connected with a first signal input end of the AGC intermediate frequency amplifier, a signal output end of the AGC intermediate frequency amplifier is connected with a signal input end of the A/D converter, a signal output end of the A/D converter is connected with a signal input end of the FPGA, a signal output end of the FPGA is connected with a signal input end of the monitoring processing unit through a serial interface, and the receiving unit further comprises a DSP, and a data bus of the DSP is connected with an address bus and the FPGA.

Further, a first mixer, a second mixer, a phase shifter and an NCO control unit are arranged in the FPGA, a first filter, a second filter and an error detector are arranged, a first signal input end of the first mixer and a first signal input end of the second mixer are connected with a signal output end of the a/D converter, a signal output end of the first mixer is connected with a signal input end of the first filter, a signal output end of the first filter is connected with a signal input end of the NCO control unit, a first signal output end of the NCO control unit is connected with a second signal input end of the first mixer, a second signal output end of the NCO control unit is connected with a signal input end of the phase shifter, a signal output end of the phase shifter is connected with a second signal input end of the second mixer, a signal output end of the second mixer is connected with a signal input end of the second filter, a signal output end of the second filter is connected with a signal input end of the error detector, and a signal output end of the NCO control unit is connected with a signal input end of the error detector through a serial interface.

Further, a crystal oscillator is connected to the FPGA.

Further, a memory is connected to the DSP.

Further, the first signal output end of the error detector is connected with the signal input ends of the monitoring extension and the servo extension respectively through serial interfaces.

Further, the receiving unit further comprises a D/a converter, wherein a signal input end of the D/a converter is connected with a second signal output end of the error detector, and a signal output end of the D/a converter is connected with a second signal input end of the AGC intermediate frequency amplifier.

Compared with the prior art, the utility model has the beneficial effects that:

1. the utility model carries out AGC amplification on the received 70MHz intermediate frequency signal, and realizes frequency guidance, sideband error locking prevention, carrier capturing and tracking by selecting coherent and incoherent AGC, so that the normalization of the downlink channel tracking signal is realized;

2. the utility model uses the 'incoherent' AGC and the 'coherent' AGC to make the selection signal of the 'incoherent' AGC and the 'coherent' AGC switching by using the locking indication signal, thereby carrying out effective tracking processing and ensuring the tracking effect.

Drawings

Fig. 1 is a schematic diagram of a DVB signal maximum tracking receiving plate according to the present utility model;

fig. 2 is a schematic diagram of an FPGA in a DVB signal maximum tracking receiving plate according to the present utility model.

Detailed Description

The present utility model will be described in further detail with reference to examples and drawings, but embodiments of the present utility model are not limited thereto.

In the description of the present utility model, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "longitudinal", "lateral", "horizontal", "inner", "outer", "front", "rear", "top", "bottom", etc., are directions or positional relationships based on those shown in the drawings, or are directions or positional relationships conventionally put in use of the inventive product, are merely for convenience of describing the present utility model and for simplifying the description, and are not indicative or implying that the apparatus or element to be referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be construed as limiting the present utility model.

In the description of the present utility model, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "configured," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.

Examples

As shown in fig. 1, a DVB signal maximum tracking receiving board includes a receiving unit and a monitoring processing unit; the receiving unit comprises a band-pass filter, an AGC intermediate frequency amplifier, an A/D converter and an FPGA, wherein a signal input end of the band-pass filter is externally connected with a downlink signal, a signal output end of the band-pass filter is connected with a first signal input end of the AGC intermediate frequency amplifier, a signal output end of the AGC intermediate frequency amplifier is connected with a signal input end of the A/D converter, a signal output end of the A/D converter is connected with a signal input end of the FPGA, a signal output end of the FPGA is connected with a signal input end of the monitoring processing unit through a serial interface, and the receiving unit further comprises a DSP, and a data bus of the DSP is connected with an address bus and the FPGA.

The tracking receiving system adopts a stepping tracking system, and radio frequency signals received by an antenna are converted into intermediate frequency suitable for processing by a tracking receiver through LNB and then sent to a tracking receiving board receiving unit. Because BPSK, QPSK broadband signal noise are stronger, the track receiving board utilizes the band-pass filter of certain bandwidth to draw partial signal, after the AD intermediate frequency is digitized, directly carries out amplitude detection, filters, carries out AGC operation in FPGA, sends the controlled variable to AGC variable frequency gain amplifier, accomplishes "incoherent" AGC monitoring and AGC loop control.

The method specifically comprises the steps of inputting a 70MHz downlink signal into a band-pass filter, carrying out filtering treatment on the input 70MHz downlink signal through the band-pass filter, inputting the filtered downlink signal into an AGC intermediate frequency amplifier, processing the downlink signal through the AGC intermediate frequency amplifier, converting the downlink analog signal into a digital signal through an A/D converter, inputting the digital signal into an FPGA, processing the signal in the FPGA, outputting AGC voltage and locking indication, wherein the DSP can give a reference value, comparing the actual value of the input signal with the reference value through the FPGA, if the reference value is larger than the reference value, locking indication is effective, otherwise judging that the locking indication is not locked, selecting a 'coherent' AGC loop when the output locking indication signal is effective, selecting a 'incoherent' AGC loop when the locking indication signal is judged to be unlocked, finally outputting the AGC voltage and the locking indication to a monitoring processing unit through a serial interface, and monitoring main working parameters of a tracking receiver by the monitoring processing unit.

In one embodiment, as shown in fig. 2, a first mixer, a second mixer, a phase shifter, and an NCO control unit are disposed in the FPGA, a first filter, a second filter, and an error detector are disposed in the FPGA, a first signal input end of the first mixer and a first signal input end of the second mixer are connected to a signal output end of the a/D converter, a signal output end of the first mixer is connected to a signal input end of the first filter, a signal output end of the first filter is connected to a signal input end of the NCO control unit, a first signal output end of the NCO control unit is connected to a second signal input end of the first mixer, a second signal output end of the NCO control unit is connected to a signal input end of the phase shifter, a signal output end of the second mixer is connected to a signal input end of the second mixer, a signal output end of the second mixer is connected to a signal input end of the second filter, and an error detector is connected to a signal input end of the signal detector, and the error detector is connected to a signal input end of the signal detector through a serial interface.

After the input signal is subjected to AGC amplifier and A/D sampling, the carrier phase-locked loop formed by NCO zero crossing branch circuit completes carrier extraction, the NCO quadrature branch circuit outputs a direct current signal reflecting the amplitude of the input signal after filtering, the direct current signal is output by an error detector, namely a digital AGC voltage signal, and the digital AGC voltage signal is converted into an analog AGC voltage by a D/A converter to control the AGC amplifier, so that the amplitude of the signal at the A/D input end is kept stable, and sufficient bit resolution is provided for a subsequent demodulation circuit.

In one embodiment, as shown in fig. 1 and fig. 2, the first signal output end of the error detector is connected to the signal input ends of the monitoring slave unit and the servo slave unit through serial interfaces, respectively. The tracking receiving board carries out tracking demodulation on the narrow-band signal and the broadband signal at the same time by filtering the input 70MHz signal and digitizing the 70MHz intermediate frequency, the tracking receiving board adopts a 1-level AGC structure, the AGC dynamic range of 50dB can be realized, and the locking indication and the AGC voltage are sent to the monitoring extension and the servo extension.

In one embodiment, as shown in fig. 1, a crystal oscillator is connected to the FPGA. The crystal oscillator is connected to the FPGA, the clock frequency of the FPGA is regulated according to the clock pulse signal generated by the crystal oscillator, so that the frequency stability of the FPGA is ensured, and the technical problems of asynchronous clock frequency and unstable signal in the prior art are solved.

In one embodiment, as shown in fig. 1, the DSP is connected with a memory, and the memory may be a flash memory or a memory, so as to store data, ensure that the data is not easy to be lost, and solve the technical problem that the data is easy to be lost in the prior art.

In one embodiment, as shown in fig. 1 and fig. 2, the receiving unit further includes a D/a converter, where a signal input end of the D/a converter is connected to the second signal output end of the error detector, and a signal output end of the D/a converter is connected to the second signal input end of the AGC intermediate frequency amplifier. The FPGA outputs signals to the D/A converter through the analog port, converts digital signals into analog signals, sends locking instructions, and timely feeds back AGC voltage, angle error voltage and the like to the AGC intermediate frequency amplifier, so that the technical problem that tracking inaccuracy is caused because signals are not fed back in time in the prior art is solved.

The foregoing description of the preferred embodiment of the utility model is not intended to limit the utility model in any way, but rather to cover all modifications, equivalents, improvements and alternatives falling within the spirit and principles of the utility model.

Claims

1. A DVB signal maxima tracking receiver plate, characterized by: comprises a receiving unit and a monitoring processing unit; the receiving unit comprises a band-pass filter, an AGC intermediate frequency amplifier, an A/D converter and an FPGA, wherein a signal input end of the band-pass filter is externally connected with a downlink signal, a signal output end of the band-pass filter is connected with a first signal input end of the AGC intermediate frequency amplifier, a signal output end of the AGC intermediate frequency amplifier is connected with a signal input end of the A/D converter, a signal output end of the A/D converter is connected with a signal input end of the FPGA, a signal output end of the FPGA is connected with a signal input end of the monitoring processing unit through a serial interface, and the receiving unit further comprises a DSP, and a data bus of the DSP is connected with an address bus and the FPGA.

2. A DVB signal maxima tracking receiving pad according to claim 1, wherein: the FPGA is internally provided with a first mixer, a second mixer, a phase shifter and an NCO control unit, wherein the first mixer, the second filter and an error detector are arranged, a first signal input end of the first mixer and a first signal input end of the second mixer are connected with a signal output end of the A/D converter, a signal output end of the first mixer is connected with a signal input end of the first filter, a signal output end of the first filter is connected with a signal input end of the NCO control unit, a first signal output end of the NCO control unit is connected with a second signal input end of the first mixer, a second signal output end of the NCO control unit is connected with a signal input end of the phase shifter, a signal output end of the phase shifter is connected with a second signal input end of the second mixer, a signal output end of the second mixer is connected with a signal input end of the second filter, a signal output end of the second filter is connected with an error detector, and the first signal output end of the NCO control unit is connected with an error detector through a serial signal input end of the phase shifter.

3. A DVB signal maxima tracking receiving pad according to claim 2, wherein: and the FPGA is connected with a crystal oscillator.

4. A DVB signal maxima tracking receiving pad according to claim 3 wherein: and the DSP is connected with a memory.

5. A DVB signal maxima tracking receiving pad according to claim 4 wherein: the first signal output end of the error detector is connected with the signal input ends of the monitoring extension and the servo extension respectively through serial interfaces.

6. A DVB signal maxima tracking receiver plate according to claim 5 wherein: the receiving unit further comprises a D/A converter, wherein the signal input end of the D/A converter is connected with the second signal output end of the error detector, and the signal output end of the D/A converter is connected with the second signal input end of the AGC intermediate frequency amplifier.