CN218896342U

CN218896342U - Power-on abnormal reset circuit and terminal equipment

Info

Publication number: CN218896342U
Application number: CN202222761158.3U
Authority: CN
Inventors: 丁永波; 李胜; 姚海望; 刘其海; 李�浩; 孙红敏
Original assignee: Shenzhen Weibu Information Co Ltd
Current assignee: Shenzhen Weibu Information Co Ltd
Priority date: 2022-10-20
Filing date: 2022-10-20
Publication date: 2023-04-21
Anticipated expiration: 2032-10-20

Abstract

The embodiment of the utility model discloses a power-on abnormal reset circuit and terminal equipment, wherein the terminal equipment comprises a main board, and a power interface, a voltage conversion circuit, a PMIC chip and the power-on abnormal reset circuit are arranged on the main board; the system voltage output by the power adapter is transmitted to the voltage conversion circuit and the power-on abnormal reset circuit through the power interface; the voltage conversion circuit converts the system voltage into a first standby voltage and a second standby voltage, outputs the first standby voltage and the second standby voltage to the power-on abnormal reset circuit, and also outputs the second standby voltage to power the PMIC chip; and when the power-on abnormal reset circuit detects that the voltage value of any one of the second standby voltage and the system voltage is abnormal, outputting an enabling signal with a corresponding level to reset the PMIC chip. Therefore, the problem that the conventional PMIC chip control mode cannot reset the PMIC chip when the system voltage or the second standby voltage is abnormal is solved.

Description

Power-on abnormal reset circuit and terminal equipment

Technical Field

The present utility model relates to the field of electronic technologies, and in particular, to a power-on abnormal reset circuit and a terminal device.

Background

At present, SOC (System on Chip) chips of Intel Apollo and Gemini Lake platforms are powered by PMIC (Power Management IC, power management Chip) chips, for example, PMIC chips with model number ROHM BD2671 MWV; this is an integrated power management IC (Integrated Circuit ) dedicated to 5V input powered applications; providing 1 Buck controller, 5 Buck converters, 2 LDOs, and providing specific power requirements for Intel Apollo Lake and Gemini Lake platform. As shown in fig. 1, on the existing motherboard, a power interface is externally connected with a power adapter to provide 12V system voltage +vdc for the motherboard, and one path of the system voltage +vdc supplies power to a display screen (such as an LED display screen) through a direct current output interface; the other path is converted into a first standby voltage +3.3VSB and a second standby voltage +5VSB through a voltage conversion circuit to supply power to other modules, and the second standby voltage +5VSB supplies power to the PMIC chip and also supplies power to other devices through the USB interface.

In order to enhance the power supply capability of the main board to the display equipment and the USB interface, an energy storage filter circuit (LC (inductance capacitance) circuit) is added at the front end of the direct current output interface, and an energy storage filter capacitor with a large capacitance value is arranged at the power supply end of the USB interface, and the two power supplies are obtained by conversion after being input through a power adapter. This causes a problem that when the on power adapter is connected (i.e. the input end of the power adapter is connected to AC 220V), excessive Inrush current is generated on the system voltage +vdc input network and the USB power supply network at the moment of powering on the motherboard (if the motherboard is connected to the output end of the power adapter and the input end of the power adapter is connected to AC 220V, this abnormality does not occur), resulting in overload protection of the power adapter and stopping outputting the system voltage +vdc.

And the PMIC chip can detect whether the system voltage +VDC is stable or not in the power-on process and normal operation, and when detecting that the system voltage +VDC is lower than 5.4V, the PMIC chip can start a low-voltage output protection function, so that the main board is abnormal in power-on and cannot be started normally. At this time, the PMIC chip needs to be reset to be reinitialized, the pmic_en pin of the PMIC chip must be pulled down first, and the pmic_en pin is pulled up after the system voltage +vdc is recovered to be normal.

At present, the control modes of the PMIC chip mainly comprise 3 types: 1 is pulled up directly through +3v3sb, which cannot reflect the conditions of the system voltage +vdc and the second standby voltage +5vsb in real time, and cannot control the pmic_en pin in real time; 2, controlling the PMIC chip to reset by the second standby voltage +5VSB output by the voltage conversion circuit, wherein the mode can reflect the state of the second standby voltage +5VSB, but can not reflect the state of the system voltage +VDC, and can only realize the function of controlling the PMIC_EN pin in real time when the second standby voltage +5VSB is abnormal; 3 is a GPIO pin using other chips such as EC (embedded controller), CPLD (complex programmable logic device), SIO (super input output chip), etc., a pmic_en pin for controlling the PMIC chip by programming, but the pmic_en pin cannot be controlled in real time according to states of the system voltage +vdc and the second standby voltage +5vsb.

The existing control mode can not meet the requirement of controlling the PMIC_EN pin when the system voltage +VDC or the second standby voltage +5VSB is abnormal, and the reset action can not be completed in time.

Disclosure of Invention

Aiming at the technical problems, the embodiment of the utility model provides a power-on abnormal reset circuit and terminal equipment, which are used for solving the problem that the conventional PMIC chip control mode cannot reset the PMIC chip when the system voltage or the second standby voltage is abnormal.

The embodiment of the utility model provides a power-on abnormal reset circuit which is connected with a power interface, a voltage conversion circuit and a PMIC chip, and comprises a comparison module and a judgment module, wherein the comparison module is connected with the power interface, the voltage conversion circuit and the judgment module; the judging module is connected with the PMIC chip;

the comparison module compares the first standby voltage output by the voltage conversion circuit with the second standby voltage and outputs a first comparison voltage with a corresponding level, and also compares the system voltage output by the voltage conversion circuit with the first standby voltage and outputs a second comparison voltage with a corresponding level;

the judging module outputs a corresponding level enabling signal according to the high-low level of the first comparison voltage and the second comparison voltage.

Optionally, in the power-on abnormal reset circuit, the comparison module includes a dual-voltage comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor;

the IN < 2+ > pin of the dual-voltage comparator is connected with one end of the first resistor and one end of the fourth resistor, the other end of the first resistor inputs system voltage, and the other end of the fourth resistor is grounded; the IN 2-pin of the dual-voltage comparator is connected with one end of the second resistor, one end of the fifth resistor and the IN 1-pin of the dual-voltage comparator; the other end of the second resistor is input with a first standby voltage, the other end of the fifth resistor is grounded, the output B pin and the output A pin of the dual-voltage comparator are both connected with the judging module, the VCC pin of the dual-voltage comparator is input with a system voltage, the In1+ pin of the dual-voltage comparator is connected with one end of the third resistor and one end of the sixth resistor, the other end of the third resistor is input with a second standby voltage, the other end of the sixth resistor is grounded, and the GND pin of the dual-voltage comparator is grounded.

Optionally, IN the power-on abnormal reset circuit, the comparison module further includes a first capacitor and a second capacitor, the first capacitor is connected between the VCC pin of the dual-voltage comparator and ground, and the second capacitor is connected between the in1+ pin of the dual-voltage comparator and ground.

Optionally, in the power-on abnormal reset circuit, the judging module includes an and gate, a seventh resistor, an eighth resistor and a ninth resistor;

the 1 st pin of the AND gate is connected with one end of the eighth resistor, the 2 nd pin of the AND gate is connected with one end of the seventh resistor, the other end of the seventh resistor and the other end of the eighth resistor are both input with a first standby voltage, the 3 rd pin of the AND gate is grounded, the 4 th pin of the AND gate is connected with the PMIC_EN pin of the PMIC chip through the ninth resistor, and the 5 th pin of the AND gate is input with the first standby voltage.

Optionally, in the power-on abnormal reset circuit, the judging module further includes a third capacitor and a first diode, the third capacitor is connected between the 5 th pin of the and gate and the ground, the positive electrode of the first diode is connected with one end of the ninth resistor and the pmic_en pin of the PMIC chip, and the negative electrode of the first diode is connected with the 4 th pin of the and gate and the other end of the ninth resistor.

Optionally, in the power-on abnormal reset circuit, a model number of the dual-voltage comparator is LM393.

Optionally, in the power-on abnormal reset circuit, the resistance of the first resistor is 47kΩ, the resistance of the second resistor is 10kΩ, the resistance of the third resistor is 33kΩ, the resistance of the fourth resistor is 33kΩ, the resistance of the fifth resistor is 33kΩ, and the resistance of the sixth resistor is 47kΩ.

Optionally, in the power-on abnormal reset circuit, the resistance value of the seventh resistor and the eighth resistor is 100kΩ.

The second aspect of the embodiment of the utility model provides a terminal device, which comprises a main board, wherein a power interface, a voltage conversion circuit and a PMIC chip are arranged on the main board, the power-on abnormal reset circuit is also arranged on the main board, the power interface is externally connected with a power adapter, the voltage conversion circuit is connected with the power interface, the PMIC chip and the power-on abnormal reset circuit, and the power-on abnormal reset circuit is connected with the PMIC chip;

the system voltage output by the power adapter is transmitted to the voltage conversion circuit and the power-on abnormal reset circuit through the power interface;

the voltage conversion circuit converts the system voltage into a first standby voltage and a second standby voltage, outputs the first standby voltage and the second standby voltage to the power-on abnormal reset circuit, and also outputs the second standby voltage to power the PMIC chip;

and when the power-on abnormal reset circuit detects that the voltage value of any one of the second standby voltage and the system voltage is abnormal, outputting an enabling signal with a corresponding level to reset the PMIC chip.

Optionally, in the terminal device, the main board is further provided with an energy storage filter circuit, a direct current output interface, a display screen, a USB interface and a processor; the energy storage filter circuit is connected with the power interface and the direct current output interface, the direct current output is connected with the display screen, the USB interface is connected with the voltage conversion circuit, and the processor is connected with the PMIC chip;

the energy storage filter circuit performs energy storage and filtering on the system voltage, and then outputs the system voltage to a display screen from the direct current output interface to supply power; the USB interface outputs a second standby voltage to other modules for supplying power; the PMIC chip powers the processor.

In the technical scheme provided by the embodiment of the utility model, the terminal equipment comprises a main board, wherein a power interface, a voltage conversion circuit, a PMIC chip and a power-on abnormal reset circuit are arranged on the main board, the power interface is externally connected with a power adapter, the voltage conversion circuit is connected with the power interface, the PMIC chip and the power-on abnormal reset circuit, and the power-on abnormal reset circuit is connected with the PMIC chip; the system voltage output by the power adapter is transmitted to the voltage conversion circuit and the power-on abnormal reset circuit through the power interface; the voltage conversion circuit converts the system voltage into a first standby voltage and a second standby voltage, outputs the first standby voltage and the second standby voltage to the power-on abnormal reset circuit, and also outputs the second standby voltage to power the PMIC chip; and when the power-on abnormal reset circuit detects that the voltage value of any one of the second standby voltage and the system voltage is abnormal, outputting an enabling signal with a corresponding level to reset the PMIC chip. Therefore, the problem that the conventional PMIC chip control mode cannot reset the PMIC chip when the system voltage or the second standby voltage is abnormal is solved.

Drawings

Fig. 1 is a circuit schematic diagram of a conventional motherboard.

Fig. 2 is a block diagram of a terminal device according to an embodiment of the present utility model.

Fig. 3 is a schematic circuit diagram of a comparison module according to an embodiment of the utility model.

Fig. 4 is a circuit schematic diagram of a judging module in an embodiment of the utility model.

Fig. 5 is a circuit schematic of a PMIC chip according to an embodiment of the utility model.

Fig. 6 is a schematic circuit layout of a motherboard according to an embodiment of the utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. Embodiments of the present utility model are intended to be within the scope of the present utility model as defined by the appended claims.

Referring to fig. 2, the terminal device provided by the embodiment of the present utility model includes a main board, on which a power interface 2, a voltage conversion circuit 3, a PMIC chip 4 and a power-on abnormal reset circuit 1 are disposed; the power interface is externally connected with the power adapter, the voltage conversion circuit is connected with the power interface, the PMIC chip and the power-on abnormal reset circuit 1, and the power-on abnormal reset circuit 1 is connected with the PMIC chip; the system voltage +VDC output by the power adapter is transmitted to the voltage conversion circuit and the power-on abnormal reset circuit 1 through a power interface; the voltage conversion circuit converts the system voltage +VDC into a first standby voltage +3.3VSB and a second standby voltage +5VSB, outputs the first standby voltage +3.3VSB and the second standby voltage +5VSB to the power-on abnormal reset circuit 1, and also outputs the second standby voltage +5VSB to power the PMIC chip. When the power-on abnormal reset circuit 1 detects that the voltage value of any one of the second standby voltage +5vsb and the system voltage +vdc is abnormal, an enable signal pmic_en of a corresponding level is output to reset the PMIC chip.

Wherein the voltage value is abnormal, including the second standby voltage +5vsb falling below the second lower limit value and the system voltage +vdc falling below the third lower limit value. The enable signal PMIC_EN changes to a low level when the voltage value is abnormal, and automatically changes to a high level after the voltage value is normal, so that the PMIC chip can be reset by changing from the low level to the high level.

In specific implementation, the power-on abnormal reset circuit 1 is mainly applicable to various terminal devices provided with a PMIC chip, such as a notebook computer, a mobile phone, and the like. The main board is also provided with an energy storage filter circuit 5, a direct current output interface, a display screen, a USB interface and a processor 6, wherein the energy storage filter circuit is connected with the power interface and the direct current output interface, the direct current output is connected with the display screen, the USB interface is connected with the voltage conversion circuit, and the processor is connected with the PMIC chip. The connection and function of these devices is known in the art. The power interface is externally connected with the power adapter to provide 12V system voltage +VDC for the main board, and after one path of the system voltage +VDC is subjected to energy storage and filtration through the energy storage filter circuit, the system voltage +VDC is output from the direct current output interface to supply power to a display screen (such as an LED display screen). The other circuit of the system voltage +VDC is converted into a first standby voltage +3.3VSB and a second standby voltage +5VSB through a voltage conversion circuit (which can be composed of a chip with the model of RT6567D and peripheral circuits) to supply power to other modules. The first standby voltage +3.3vsb is mainly an SOC (system-on-a-chip), an m.2ssd (m.2 interface solid state disk), a LAN IC (network card chip), an LVDS interface display, a TPM (trusted platform module), a WiFi module, and the like. The second standby voltage +5vsb supplies power to other devices, such as USB devices, SATA Hard Disk, audio Codec, etc., through USB interfaces in addition to the PMIC chip. The voltage output by the PMIC chip includes 1.8V, 1.24V, 1.05V, VDDQ voltage and VCCGI voltage to power a processor (e.g., SOC).

Preferably, an overvoltage protection circuit 7 is further disposed on the motherboard, and is configured to stop outputting the system voltage +vdc to the power-on abnormal reset circuit 1 when the voltage value of the system voltage +vdc is greater than the upper limit value of the system, and perform overvoltage protection on the power-on abnormal reset circuit 1, so as to avoid the system voltage +vdc from being over-voltage and burning out the power-on abnormal reset circuit 1 when an abnormality occurs. The overvoltage protection circuit can be realized by adopting a controllable precise voltage stabilizing source with the model number TL431 and a peripheral circuit thereof.

It should be understood that the PMIC chip has other pins, which is the prior art, and only the pins related to this embodiment are shown in fig. 5 of this embodiment. FIG. 6 shows only the location of some of the important components on the motherboard, which is only an example, and may be laid out as desired when implemented in practice; only the elements related to this embodiment are shown here, and other existing elements are on the motherboard, which are not described in detail here.

The power-on abnormal reset circuit 1 comprises a comparison module 11 and a judgment module 12, wherein the comparison module 11 is connected with a power interface, a voltage conversion circuit and the judgment module 12; the judging module 12 is connected with the PMIC chip. The comparison module 11 compares the first standby voltage +3.3vsb with the second standby voltage +5vsb and outputs a first comparison voltage pmic_rst1 of a corresponding level, and also compares the system voltage +vdc with the first standby voltage +3.3vsb and outputs a second comparison voltage pmic_rst2 of a corresponding level; the judgment module 12 outputs the enable signal pmic_en of the corresponding level according to the high-low level of the first comparison voltage pmic_rst1 and the second comparison voltage pmic_rst2.

The method comprises the following steps: when the first standby voltage +3.3vsb is compared with the second standby voltage +5vsb, if the second standby voltage +5vsb is reduced to be less than the second lower limit value (i.e. an abnormality occurs), the comparison module 11 outputs the first comparison voltage pmic_rst1 with a low level; if the second standby voltage +5vsb is greater than the second lower limit value (i.e., the voltage is normal), the comparison module 11 outputs the first comparison voltage pmic_rst1 of the high level. When the system voltage +vdc is compared with the first standby voltage +3.3vsb, if the system voltage +vdc falls below the third lower limit value (i.e., an abnormality occurs), the comparison module 11 outputs a second comparison voltage pmic_rst2 of a low level; if the system voltage +vdc is greater than the third lower limit value (i.e., the voltage is normal), the comparison module 11 outputs the second comparison voltage pmic_rst2 of the high level.

When either one of the first comparison voltage pmic_rst1 and the second comparison voltage pmic_rst2 is at a low level, the determination module 12 outputs the enable signal pmic_en at a low level to turn off the PMIC chip. When the first comparison voltage pmic_rst1 and the second comparison voltage pmic_rst2 are both at the high level, the determination module 12 outputs the enable signal pmic_en at the high level to turn on the PMIC chip. The state transition of the enable signal pmic_en from the low level to the high level corresponds to a reset operation of the PMIC chip.

Referring to fig. 3, the comparing module 11 includes a dual-voltage comparator U1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6; the IN < 2+ > pin of the dual-voltage comparator U1 is connected with one end of a first resistor R1 and one end of a fourth resistor R4, the other end of the first resistor R1 is input with a system voltage +VDC, and the other end of the fourth resistor R4 is grounded; the IN 2-pin of the dual-voltage comparator U1 is connected with one end of the second resistor R2, one end of the fifth resistor R5 and the IN 1-pin of the dual-voltage comparator U1; the other end of the second resistor R2 is input with a first standby voltage +3.3VSB, the other end of the fifth resistor R5 is grounded, the output B pin and the output A pin of the dual-voltage comparator U1 are both connected with the judging module 12, the VCC pin of the dual-voltage comparator U1 is input with a system voltage +VDC, the In1+ pin of the dual-voltage comparator U1 is connected with one end of the third resistor R3 and one end of the sixth resistor R6, the other end of the third resistor R3 is input with a second standby voltage +5VSB, the other end of the sixth resistor R6 is grounded, and the GND pin of the dual-voltage comparator U1 is grounded.

The model of the dual-voltage comparator U1 is preferably LM393, which includes two independent voltage comparators therein; wherein, VCC pin is voltage pin, GND pin is ground pin; the IN 1-pin, the In1+ pin and the OutputA pin are all pins of the first path voltage comparator; the IN 2-pin, the In2+ pin, and the OutputB pin are the respective pins of the second-way voltage comparator.

After the first standby voltage +3.3vsb is divided by R2 and R5, a first divided voltage v2p53_ref (the voltage value of which is fixed and provides a fixed reference voltage for U1) is generated, the resistance value of the second resistor R2 is preferably 10kΩ, the resistance value of the fifth resistor R5 is preferably 33kΩ, and the calculation formula of the voltage value is: r5/(r2+r5) ×3.3v=2.53V, the voltage value of the first divided voltage v2p53_ref is fixed to 2.53V, and is input to the IN 2-pin and the IN 1-pin of U1. After the second standby voltage +5vsb is divided by R3 and R6, a second divided voltage 5v_drop is generated, and the voltage value is calculated according to the following formula: R6/(R3+R6). Times.5V, input to the In1+ pin of U1, the voltage on In1+ pin is compared with the voltage on IN 1-pin, i.e. the first divided voltage V2P53_REF is compared with the second divided voltage 5V_DROP. When the resistance values of R3 and R6 are set, the voltage value on the IN1+ pin of U1 is just smaller than the IN 1-pin (2.53V) when 5V is reduced to 4.4V; the resistance of the third resistor R3 is preferably 33kΩ and the resistance of the sixth resistor R6 is preferably 47kΩ.

When the second standby voltage +5vsb is normally stable, the voltage value of the second voltage division voltage 5v_drop is 2.93V, so the voltage value (2.93V) of the in1+ pin is greater than the voltage value (2.53V) of the IN 1-pin, and the OutputA pin outputs the first comparison voltage pmic_rst1 of the high level. When the second standby voltage +5vsb voltage drops, the second voltage division voltage 5v_drop will be caused to drop, and when the second standby voltage +5vsb is low to 4.3V, the voltage value of the second voltage division voltage 5v_drop is 2.52V, so the voltage value (2.52V) of in1+ pin is smaller than the voltage value (2.53V) of IN 1-pin, and at this time, the OutputA pin outputs the first comparison voltage pmic_rst1 of low level.

After the system voltage +VDC is divided by R1 and R4, a third divided voltage VDC_DROP is generated and is input to the In2+ pin of U1, and the In2+ pin is compared with the voltage on the IN 2-pin, namely the third divided voltage VDC_DROP is compared with the first divided voltage V2P53_REF. The resistance values of R1 and R4, when set, need to be such that the voltage division value on the In2+ pin of U1 is just less than the IN 2-pin (2.53V) before the system voltage +VDC drops to 5.4V (currently set to 6.1V). The resistance of the first resistor R1 is preferably 47kΩ and the resistance of the fourth resistor R4 is preferably 33kΩ. When the system voltage +vdc is normally stabilized, vdc_drop=r4/(r1+r4) ×vdc=4.95V, and thus the voltage value (4.95V) of in2+ pin is larger than the voltage value (2.53V) of IN 2-pin, and the OutputB pin outputs the second comparison voltage pmic_rst2 of high level. When the system voltage +vdc decreases, the third divided voltage vdcdrop is decreased, and when the system voltage +vdc is as low as 6.1V, the third divided voltage vdcdrop is equal to 2.51V, the voltage value (2.51V) of the in2+ pin is smaller than the voltage value (2.53V) of the IN 2-pin, and the OutputB pin outputs the second comparison voltage pmic_rst2 of a low level.

Preferably, the comparing module 11 further includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is connected between the VCC pin of the dual voltage comparator U1 and the ground, and the second capacitor C2 is connected between the in1+ pin of the dual voltage comparator U1 and the ground. The two capacitors are used for filtering, so that the voltage on the connected pins is more stable, and the working stability of the dual-voltage comparator U1 and the accuracy of a voltage comparison result are improved.

Referring to fig. 4, the judging module 12 includes an and gate U2, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9; the 1 st pin (i.e., an input pin) of the and gate U2 is connected to one end of the eighth resistor R8, the 2 nd pin (i.e., another input pin) of the and gate U2 is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 and the other end of the eighth resistor R8 are both input with the first standby voltage +3.3VSB, the 3 rd pin (i.e., a ground pin) of the and gate U2 is grounded, the 4 th pin (i.e., an output pin) of the and gate U2 is connected to the pmic_en pin (i.e., an enable pin) of the PMIC chip through the ninth resistor R9, and the 5 th pin (i.e., a power pin) of the and gate U2 is input with the first standby voltage +3.3VSB.

The resistance of the seventh resistor R7 and the eighth resistor R8 is preferably 100kΩ. The tenth resistor R10 preferably has a resistance value of 0Ω, which is used to distinguish the names of the front and rear signal lines.

Preferably, the judging module 12 further includes a third capacitor C3 and a first diode D1, where the third capacitor C3 is connected between the 5 th pin of the and gate U2 and ground, the positive electrode of the first diode D1 is connected to one end of the ninth resistor R9 and the pmic_en pin of the PMIC chip, and the negative electrode of the first diode D1 is connected to the 4 th pin of the and gate U2 and the other end of the ninth resistor R9. The third capacitor C3 is used for filtering the voltage on the 5 th pin of the and gate, and the first diode D1 is used for quickly pulling down the enable signal pmic_en for power-down control.

The principle that the PMIC chip enters and exits from a UVLO (low voltage locking) state is as follows: as shown in fig. 5, the VSYS pin of the PMIC chip is connected to a +vdc power supply network (i.e., input system voltage +vdc), and the voltage value of the system voltage +vdc is normally 12V. When the external adapter is unstable, the voltage value of the system voltage +VDC is reduced, the PMIC chip detects the voltage value of the VSYS pin, namely the voltage value of the system voltage +VDC, and when the voltage on the VSYS pin is reduced to be lower than 5.4V and the time exceeds 5us, the PMIC chip triggers UVLO and enters an abnormal protection state. When the voltage on the VSYS pin rises above 5.6V and the time exceeds 100us, if the PMIC_EN pin is detected to have state transition from L- > H (low level to high level), PMIC restarting can be realized and each path of voltage can be normally output.

In this embodiment, when the first comparison voltage pmic_rst1 and the second comparison voltage pmic_rst2 are both at high level (i.e., the second standby voltage +5vsb and the system voltage +vdc are both normally stable), or the first standby voltage +3.3vsb is normally output, the and gate U2 outputs a pmic_rst signal at high level, and outputs an enable signal pmic_en at high level after passing through the tenth resistor R10, at which time the PMIC chip normally operates.

On the contrary, when any one of the first comparison voltage pmic_rst1 and the second comparison voltage pmic_rst2 is at a low level (i.e., any one of the second standby voltage +5vsb and the system voltage +vdc is lowered to an abnormal state), the and gate U2 outputs a pmic_rst signal at a low level, and correspondingly outputs an enable signal pmic_en at a low level through the tenth resistor R10, so that the PMIC chip can be turned off to stop the operation. When the second standby voltage +5vsb and the system voltage +vdc are restored to normal, the enable signal pmic_en becomes high again, and the PMIC chip starts to operate again. From off to on, i.e., the pmic_en pin transitions from a low level to a high level, a PMIC restart is achieved, which is equivalent to a reset operation of the PMIC chip. Therefore, the high-low state of the enabling signal PMIC_EN can be controlled in real time according to whether the voltage values of the second standby voltage +5VSB and the system voltage +VDC are abnormal, so that the PMIC chip can be turned on and turned off and reset.

In summary, according to the power-on abnormal reset circuit and the terminal device provided by the utility model, by improving the enabling control mode of the PMIC chip, the system voltage and the second standby voltage are respectively compared with the first standby voltage by using the dual-voltage comparator in a resistor voltage division mode, when any one of the system voltage and the second standby voltage is abnormal, a low-level enabling signal is output to close the PMIC chip, and when the system voltage and the second standby voltage are normal, a high-level enabling signal is output to open the PMIC chip, so that the power-on is reinitialized; the problem that a main board is not started due to the fact that a power adapter in a starting state is connected to the main board, and system Voltage is unstable to enable a PMIC (programmable logic controller) chip to enter an render Voltage-LockOut state is solved; and the system voltage and the second standby voltage can be monitored simultaneously to judge whether the system voltage and the second standby voltage are abnormal or not, and the PMIC chip is automatically reset after the system voltage and the second standby voltage are abnormal and normal.

The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.

Claims

1. The power-on abnormal reset circuit is connected with the power interface, the voltage conversion circuit and the PMIC chip and is characterized by comprising a comparison module and a judgment module, wherein the comparison module is connected with the power interface, the voltage conversion circuit and the judgment module; the judging module is connected with the PMIC chip;

2. The power-on exception reset circuit of claim 1, wherein the comparison module comprises a dual voltage comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;

3. The power-on exception reset circuit of claim 2, wherein the comparison module further comprises a first capacitor and a second capacitor, the first capacitor is connected between the VCC pin of the dual voltage comparator and ground, and the second capacitor is connected between the in1+ pin of the dual voltage comparator and ground.

4. The power-on exception reset circuit of claim 2, wherein the determination module comprises an and gate, a seventh resistor, an eighth resistor, and a ninth resistor;

5. The power-on abnormal reset circuit according to claim 4, wherein the judging module further comprises a third capacitor and a first diode, the third capacitor is connected between the 5 th pin of the and gate and the ground, the positive electrode of the first diode is connected with one end of the ninth resistor and the pmic_en pin of the PMIC chip, and the negative electrode of the first diode is connected with the 4 th pin of the and gate and the other end of the ninth resistor.

6. The power-on exception reset circuit of claim 2, wherein the dual voltage comparator is model LM393.

7. The power-on abnormal reset circuit according to claim 2, wherein the first resistor has a resistance of 47kΩ, the second resistor has a resistance of 10kΩ, the third resistor has a resistance of 33kΩ, the fourth resistor has a resistance of 33kΩ, the fifth resistor has a resistance of 33kΩ, and the sixth resistor has a resistance of 47kΩ.

8. The power-on abnormal reset circuit according to claim 4, wherein the resistance values of the seventh resistor and the eighth resistor are 100kΩ.

9. A terminal device, comprising a main board, wherein a power interface, a voltage conversion circuit and a PMIC chip are arranged on the main board, and the terminal device is characterized in that a power-on abnormal reset circuit as claimed in any one of claims 1-8 is further arranged on the main board, the power interface is externally connected with a power adapter, the voltage conversion circuit is connected with the power interface, the PMIC chip and the power-on abnormal reset circuit, and the power-on abnormal reset circuit is connected with the PMIC chip;

10. The terminal device of claim 9, wherein the main board is further provided with a tank filter circuit, a dc output interface, a display screen, a USB interface, and a processor; the energy storage filter circuit is connected with the power interface and the direct current output interface, the direct current output is connected with the display screen, the USB interface is connected with the voltage conversion circuit, and the processor is connected with the PMIC chip;