CN218886548U - Power supply device for FPGA chip, FPGA accelerator card and electronic equipment - Google Patents

Power supply device for FPGA chip, FPGA accelerator card and electronic equipment Download PDF

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CN218886548U
CN218886548U CN202223039124.XU CN202223039124U CN218886548U CN 218886548 U CN218886548 U CN 218886548U CN 202223039124 U CN202223039124 U CN 202223039124U CN 218886548 U CN218886548 U CN 218886548U
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chip
pmic
unit
power
fpga
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胡浩
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Shenzhen Zhixing Technology Co Ltd
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Shenzhen Zhixing Technology Co Ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The application discloses power supply unit for FPGA chip, FPGA accelerator card and electronic equipment, wherein, power supply unit includes ARM chip and a plurality of PMIC unit that corresponds with the module of being supplied power in the FPGA chip, every PMIC unit is connected between the module of being supplied power rather than corresponding and ARM chip, PMIC unit is used for supplying power for the module of being supplied power rather than being connected, and obtain the output voltage and the output current of PMIC unit, the ARM chip is used for the output voltage and the output current that acquire according to every PMIC unit, calculate the consumption of FPGA chip. Because the ARM chip can calculate the power consumption of the FPGA chip according to the output voltage and the output current acquired by each PMIC unit, the power consumption of the FPGA chip can be obtained while the FPGA chip is powered, the performance of the FPGA chip is evaluated, and the performance of the power supply device is improved. The FPGA chip can perform privacy data recommendation when executing a privacy calculation task or a federal learning task.

Description

Power supply device for FPGA chip, FPGA accelerator card and electronic equipment
Technical Field
The application relates to the technical field of electronic circuits, in particular to a power supply device for an FPGA chip, an FPGA accelerator card and electronic equipment.
Background
In the related art, a privacy computing platform is usually implemented by taking an accelerator card as a carrier, and processing related to privacy data is carried out on the accelerator card, so that the privacy data is ensured not to be leaked, and the privacy computing is safer and more reliable.
In the running process of the FPGA chip in the accelerator card, the resource utilization rate can be dynamically changed, so that the power consumption at different moments can be greatly different. In the related art, a power supply mode of the FPGA chip generally adopts DC (Direct Current) -DC or LDO (Low Dropout Regulator), and power supply by using the DC-DC or LDO cannot obtain power consumption of the FPGA chip, so that performance of the FPGA chip cannot be evaluated.
SUMMERY OF THE UTILITY MODEL
The application provides a power supply unit, FPGA accelerator card and electronic equipment for the FPGA chip for solve the problem that when supplying power to the FPGA chip that exists among the prior art, can't carry out the aassessment to the performance of FPGA chip.
In a first aspect, a power supply device for an FPGA chip, the device comprising: the FPGA chip comprises an ARM chip and a plurality of PMIC units corresponding to a power supply module in the FPGA chip;
the ARM chip is electrically connected with the first end of each PMIC unit, and the second end of each PMIC unit is electrically connected with the corresponding powered module;
for each PMIC unit: the PMIC unit is used for supplying power to a power supply module connected with the PMIC unit and acquiring the output voltage and the output current of the PMIC unit;
and the ARM chip is used for calculating the power consumption of the FPGA chip according to the output voltage and the output current acquired by each PMIC unit.
In one possible implementation, the plurality of PMIC units includes some or all of:
the first PMIC unit is used for supplying power to a core unit in the FPGA chip;
a second PMIC unit for powering a memory in the FPGA chip;
a third PMIC unit for supplying power to an auxiliary power supply unit in the FPGA chip;
a fourth PMIC unit for powering a transceiver analog unit in the FPGA chip;
a fifth PMIC unit for powering a transceiver digital unit in the FPGA chip;
and the sixth PMIC unit is used for supplying power to the IO unit in the FPGA chip.
In one possible implementation, the first PMIC unit includes a first PWM controller and a plurality of first power chips;
the output end of the first PWM controller is electrically connected with the control end of each first power chip, and the first PWM controller is used for controlling each first power chip to supply power to the core unit;
for each of the first power chips: the power output end of the first power chip is electrically connected with the voltage acquisition end of the first power chip, the current acquisition end of the first power chip and the kernel unit, the control signal output end of the first power chip is electrically connected with the input end of the ARM chip, and the first power chip is used for supplying power to the kernel unit and acquiring the voltage and the current of the output end of the first power chip.
In one possible implementation, the second PMIC unit includes a second PWM controller and a second power chip;
the output end of the second PWM controller is electrically connected with the control end of the second power chip, and the second PWM controller is used for controlling the second power chip to supply power to the memory;
the power output end of the second power chip is electrically connected with the voltage acquisition end of the second power chip, the current acquisition end of the second power chip and the memory, the control signal output end of the second power chip is electrically connected with the input end of the ARM chip, and the second power chip is used for supplying power to the memory and acquiring the voltage and the current of the output end of the second power chip.
In one possible implementation, the third PMIC unit includes a first PMIC chip;
the power supply output end of the first PMIC chip is electrically connected with the current acquisition end of the first PMIC chip, the voltage acquisition end of the first PMIC chip and the auxiliary power supply unit, and the control signal output end of the first PMIC chip is electrically connected with the input end of the ARM chip;
the first PMIC chip is used for supplying power to the auxiliary power supply unit and collecting voltage and current of an output end of the first PMIC chip.
In one possible implementation, the fourth PMIC unit includes a second PMIC chip;
the power supply output end of the second PMIC chip is electrically connected with the current acquisition end of the second PMIC chip, the voltage acquisition end of the second PMIC chip and the transceiver simulation unit, and the control signal output end of the second PMIC chip is electrically connected with the input end of the ARM chip;
and the second PMIC chip is used for supplying power to the transceiver analog unit and collecting the voltage and the current of the output end of the second PMIC chip.
In one possible implementation, the fifth PMIC unit includes a third PMIC chip;
a power supply output end of the third PMIC chip is electrically connected with a current acquisition end of the third PMIC chip, a voltage acquisition end of the third PMIC chip and the transceiver digital unit, and a control signal output end of the third PMIC chip is electrically connected with an input end of the ARM chip;
and the third PMIC chip is used for supplying power to the transceiver digital unit and collecting the voltage and the current of the output end of the third PMIC chip.
In one possible implementation, the sixth PMIC unit includes a fourth PMIC chip;
a power supply output end of the fourth PMIC chip is electrically connected with a current acquisition end of the fourth PMIC chip, a voltage acquisition end of the fourth PMIC chip and the IO unit, and a control signal output end of the fourth PMIC chip is electrically connected with an input end of the ARM chip;
and the fourth PMIC chip is used for supplying power to the IO unit and collecting the voltage and the current of the output end of the fourth PMIC chip.
In one possible implementation, the method further comprises an address resistor corresponding to each PMIC unit;
for each address resistance: the address resistor is connected with the corresponding PMIC unit and used for setting the address of the PMIC unit;
the ARM chip is further used for determining the address of the PMIC unit corresponding to each address resistor according to the address of the PMIC unit set by each address resistor.
In a possible implementation manner, the ARM chip is specifically configured to:
for each set of output voltage and output current: performing product processing on the output voltage and the output current to obtain output power;
and adding the obtained output powers, and taking the obtained sum as the power consumption of the FPGA chip.
In a second aspect, an embodiment of the present application provides an FPGA accelerator card, which includes an FPGA chip and the power supply device for the FPGA chip according to any one of the first aspects.
In a third aspect, an embodiment of the present application provides an electronic device, including the power supply device for an FPGA chip as described in any one of the first aspects or including the FPGA accelerator card as described in the second aspect.
The beneficial effect of this application is as follows:
the power supply device provided by the embodiment of the application comprises an ARM chip and a plurality of PMIC units corresponding to power-supplied modules in the FPGA chip, wherein each PMIC unit is connected between the corresponding power-supplied module and the ARM chip, the PMIC units are used for supplying power to the power-supplied modules connected with the PMIC units, output voltage and output current of the PMIC units are obtained, and the ARM chip is used for calculating power consumption of the FPGA chip according to the output voltage and the output current obtained by each PMIC unit. Because the ARM chip can calculate the power consumption of the FPGA chip according to the output voltage and the output current acquired by each PMIC unit, the power consumption of the FPGA chip can be obtained while the FPGA chip is powered, the performance of the FPGA chip is evaluated, and the performance of the power supply device is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a power supply device for an FPGA chip according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a first PMIC unit according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a second PMIC unit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a third PMIC unit according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a fourth PMIC unit according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a fifth PMIC unit according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a sixth PMIC unit according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of another power supply device for an FPGA chip according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be described in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. As used in this application, the terms "first," "second," and the like do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
As shown in fig. 1, a power supply device for an FPGA chip provided for an embodiment of the present application includes: the FPGA chip comprises an ARM chip 11 and a plurality of PMIC units 12 corresponding to power supply modules in the FPGA chip;
the ARM chip 11 is electrically connected to a first terminal of each PMIC unit 12, and a second terminal of each PMIC unit 12 is electrically connected to a corresponding powered module;
for each PMIC unit 12: a PMIC unit 12 configured to supply power to a powered module connected to the PMIC unit 12, and obtain an output voltage and an output current of the PMIC unit 12;
and the ARM chip 11 is used for calculating the power consumption of the FPGA chip according to the output voltage and the output current acquired by each PMIC unit 12.
In the embodiment of the application, the power supply device comprises an ARM chip and a plurality of PMIC units corresponding to power-supplied modules in the FPGA chip, each PMIC unit is connected between the corresponding power-supplied module and the ARM chip, the PMIC units are used for supplying power to the power-supplied modules connected with the PMIC units and obtaining output voltage and output current of the PMIC units, and the ARM chip is used for calculating power consumption of the FPGA chip according to the output voltage and the output current obtained by each PMIC unit. Because the ARM chip can calculate the power consumption of the FPGA chip according to the output voltage and the output current acquired by each PMIC unit, the power consumption of the FPGA chip can be obtained while the FPGA chip is powered, the performance of the FPGA chip is evaluated, and the performance of the power supply device is improved.
As shown in fig. 1, the power supply device provided in the embodiment of the present application includes n PMIC units, where n is a positive integer.
In a specific implementation, as shown in fig. 2 to 7, the PMIC units 12 in the embodiment of the present application include some or all of the following:
a first PMIC unit 121 for powering a core unit in the FPGA chip;
a second PMIC unit 122 for powering a memory in the FPGA chip;
a third PMIC unit 123 for supplying power to an auxiliary power supply unit in the FPGA chip;
a fourth PMIC unit 124 for powering transceiver analog units in the FPGA chip;
a fifth PMIC unit 125 for powering transceiver digital units in the FPGA chip;
and a sixth PMIC unit 126 for powering IO units in the FPGA chip.
In the embodiment of the application, PMIC units included in the power supply device are arranged according to units (powered modules) needing power supply in an FPGA chip, usually, a core unit, a memory, units of an auxiliary power supply, a transceiver analog unit, a transceiver digital unit and an IO unit in the FPGA chip need to be powered, therefore, the power supply device provided by the application can set the PMIC units one by one for the core unit, the memory, the units of the auxiliary power supply, the transceiver analog unit, the transceiver digital unit and the IO unit in the FPGA chip, each PMIC unit can obtain output voltage and output current of the PMIC unit besides supplying power to the powered modules connected with the PMIC unit, and therefore, the ARM chip can calculate power consumption of the FPGA chip according to the output voltage and output current obtained by the PMIC unit.
Each PMIC unit is described in detail below.
Specifically, as shown in fig. 2, the first PMIC unit 121 includes a first PWM controller 1211 and a plurality of first power chips 1212;
the output end of the first PWM controller 1211 is electrically connected to the control end of each first power chip 1212, and the first PWM controller 1211 is configured to control each first power chip 1212 to supply power to the core unit;
for each first power chip 1212: the power output end of the first power chip 1212 is electrically connected to the voltage acquisition end of the first power chip 1212, the current acquisition end of the first power chip 1212 and the core unit, the control signal output end of the first power chip 1212 is electrically connected to the input end of the ARM chip 11, and the first power chip 1212 is configured to supply power to the core unit and acquire the voltage and the current at the output end of the first power chip 1212.
In the embodiment of the present application, the voltage at the output terminal is the output voltage, and the current at the output terminal is the output current.
In this embodiment of the application, each first power chip 1212 supplies power to the core under the control of the first PWM controller 1211, and the output voltage of the first power chip 1212 acquired by the voltage acquisition end of each first power chip 1212 and the acquired output voltage are sent to the ARM chip 11, the output current of the first power chip 1212 acquired by the current acquisition end of each first power chip 1212, according to the output voltage and the output current acquired by the received plurality of first power chips 1212, the ARM chip 11 multiplies the output voltage by the output current corresponding to the output voltage, and adds up the calculated products to obtain the first power value.
Specifically, as shown in fig. 3, the second PMIC unit 122 includes a second PWM controller 1221 and a second power chip 1222;
the output end of the second PWM controller 1221 is electrically connected to the control end of the second power chip 1222, and the second PWM controller 1221 is configured to control the second power chip 1222 to supply power to the memory;
the power output end of the second power chip 1222 is electrically connected to the voltage collecting end of the second power chip 1222, the current collecting end of the second power chip 1222 and the memory, the control signal output end of the second power chip 1222 is electrically connected to the input end of the ARM chip 11, and the second power chip 1222 is used for supplying power to the memory and collecting the voltage and the current of the output end of the second power chip 1222.
In this embodiment, the second power chip 1222 supplies power to the memory under the control of the second PWM controller 1221, and meanwhile, the second power chip 1222 may further collect the output current of the second power chip 1222 through the current collecting terminal of the second power chip 1222, collect the output voltage of the second power chip 1222 through the voltage collecting terminal of the second power chip 1222, and use the collected output voltage and the collected output current as the total value of the output voltage and the output current, which are collected by the second power chip 1222, and then use the product of the output voltage and the output current as the second power value after the ARM chip 11 receives the output voltage and the output current collected by the second power chip 1222.
Specifically, as shown in fig. 4, the third PMIC unit 123 includes a first PMIC chip 1231;
the power supply output end of the first PMIC chip 1231 is electrically connected with the current collecting end of the first PMIC chip 1231, the voltage collecting end of the first PMIC chip 1231 and the auxiliary power supply unit, and the control signal output end of the first PMIC chip 1231 is electrically connected with the input end of the ARM chip 11;
the first PMIC chip 1231 is configured to supply power to the auxiliary power unit and collect a voltage and a current at an output terminal of the first PMIC chip 1231.
In the embodiment of the application, the first PMIC chip can supply power to a power supply of an auxiliary power supply, meanwhile, the output current of the first PMIC chip can be collected through a current collection end of the first PMIC chip, the output voltage of the first PMIC chip can be collected through a voltage collection end of the first PMIC chip, the collected output current and the collected output voltage are sent to the ARM chip 11, and after the ARM chip 11 receives the output voltage and the output current collected by the first PMIC chip, the product of the output voltage and the output current is used as a third power value.
Specifically, as shown in fig. 5, the fourth PMIC unit 124 includes a second PMIC chip 1241;
a power supply output end of the second PMIC chip 124 is electrically connected with a current acquisition end of the second PMIC chip 1241, a voltage acquisition end of the second PMIC chip 1241 and the transceiver analog unit, and a control signal output end of the second PMIC chip 1241 is electrically connected with an input end of the ARM chip 11;
and a second PMIC chip 1241, configured to supply power to the transceiver analog unit, and collect a voltage and a current at an output terminal of the second PMIC chip 1241.
In the embodiment of the application, the power output end of the second PMIC chip 1241 supplies power to the transceiver analog unit, the output current of the second PMIC chip 1241 is collected through the current collection end of the second PMIC chip 1241, the output voltage of the second PMIC chip 1241 is collected through the voltage collection end of the second PMIC chip 1241, the collected output voltage of the second PMIC chip 1241 and the collected output current of the second PMIC chip 1241 are sent to the ARM chip 11, and after the ARM chip 11 receives the output voltage of the second PMIC chip 1241 and the output current of the second PMIC chip 1241, the product of the output voltage and the output current is used as a fourth power value.
Specifically, as shown in fig. 6, the fifth PMIC unit 125 includes a third PMIC chip 1251;
a power supply output end of the third PMIC chip 1251 is electrically connected with a current acquisition end of the third PMIC chip 1251, a voltage acquisition end of the third PMIC chip 1251 and a transceiver digital unit, and a control signal output end of the third PMIC chip 1251 is electrically connected with an input end of the ARM chip 11;
and a third PMIC chip 1251 configured to supply power to the transceiver digital unit and collect a voltage and a current at an output terminal of the third PMIC chip 1251.
In the embodiment of the application, a transceiver digital unit is powered by a power output end of the third PMIC chip 1251, an output current of the third PMIC chip 1251 is collected by a current collection end of the third PMIC chip 1251, an output voltage of the third PMIC chip 1251 is collected by a voltage collection end of the third PMIC chip 1251, the collected output current of the third PMIC chip 1251 and the collected output voltage of the third PMIC chip 1251 are sent to the ARM chip 11, the ARM chip 11 receives the output current of the third PMIC chip 1251 and the output voltage of the third PMIC chip 1251, and a product of the output current and the output voltage is used as a fifth power value.
Specifically, as shown in fig. 7, the sixth PMIC unit 126 includes a fourth PMIC chip 1261;
a power supply output end of the fourth PMIC chip 1261 is electrically connected with a current collection end of the fourth PMIC chip 1261, a voltage collection end of the fourth PMIC chip 1261 and an IO unit, and a control signal output end of the fourth PMIC chip 1261 is electrically connected with an input end of the ARM chip 11;
and the fourth PMIC chip 1261 is configured to supply power to the IO unit and collect a voltage and a current at an output terminal of the fourth PMIC chip 1261.
In the embodiment of the application, the IO unit is powered by a power output end of the fourth PMIC chip 1261, the output current of the fourth PMIC chip 1261 is collected by a current collection end of the fourth PMIC chip 1261, the output voltage of the fourth PMIC chip 1261 is collected by a voltage collection end of the fourth PMIC chip 1261, the collected output current of the fourth PMIC chip 1261 and the collected output voltage of the fourth PMIC chip 1261 are sent to the ARM chip 11, the ARM chip 11 receives the output current of the fourth PMIC chip 1261 and the output voltage of the fourth PMIC chip 1261, and the product of the output current and the output voltage is used as the sixth power value.
With the above embodiment, the ARM chip 11 outputs, for each set of output voltage and output current: and performing product processing on the output voltage and the output current to obtain output power, then performing summation processing on the obtained multiple output powers, and taking the obtained sum as the power consumption of the FPGA chip.
For example, the first power value, the second power value, the third power value, the fourth power value, the fifth power value, and the sixth power value are summed, and the obtained sum is used as the power consumption of the FPGA chip.
In this embodiment, the power supply apparatus provided in the present application may further include an address resistor corresponding to each PMIC unit;
for each address resistance: the address resistor is connected with the corresponding PMIC unit and is used for setting the address of the PMIC unit;
the ARM chip is further used for determining the address of the PMIC unit corresponding to each address resistor according to each address resistor.
For example, as shown in fig. 8, the power supply device includes a first address resistor 131 corresponding to the first PMIC unit 121, a second address resistor 132 corresponding to the second PMIC unit 122, a third address resistor 133 corresponding to the third PMIC unit 123, a fourth address resistor 134 corresponding to the fourth PMIC unit 124, a fifth address resistor 135 corresponding to the fifth PMIC unit 125, and a sixth address resistor 136 corresponding to the sixth PMIC unit 126, wherein the first address resistor 131 is connected to the first PWM controller 1211 of the first PMIC unit 121, the second address resistor 132 is connected to the second PWM controller 1221 of the second PMIC unit 122, the third address resistor 133 is connected to the first c chip 1231 of the third PMIC unit 123, the fourth address resistor 134 is connected to the second PWM chip 1241 of the fourth PMIC unit 124, the fifth address resistor 135 is connected to the third PMIC chip 125 of the fifth PMIC unit 125, and the sixth address resistor 1251 is connected to the sixth address resistor 1261 of the fourth PMIC unit 124;
the first address resistor 131 is used to set an address of the first PMIC unit 121, that is, an address of the first PWM controller 1211, and the ARM chip 11 determines the address of the first PMIC unit 121 according to the address of the first PMIC unit 121 set by the first address resistor 131;
the second address resistor 132 is configured to set an address of the second PMIC unit 122, that is, an address of the second PWM controller 1221, and the ARM chip 11 determines the address of the second PMIC unit 122 according to the address of the second PMIC unit 122 set by the second address resistor 132;
the third address resistor 133 is used to set an address of the third PMIC unit 123, that is, an address of the first PMIC chip 123, and the ARM chip 11 determines the address of the third PMIC unit 123 according to the address of the third PMIC unit 123 set by the third address resistor 133;
the fourth address resistor 134 is used to set the address of the fourth PMIC unit 124, i.e. the address of the second PMIC chip 1241, and the ARM chip 11 determines the address of the fourth PMIC unit 124 according to the address of the fourth PMIC unit 124 set by the fourth address resistor 134;
the fifth address resistor 135 is used to set the address of the fifth PMIC unit 125, that is, the address of the third PMIC chip 1251, and the ARM chip 11 determines the address of the fifth PMIC unit 125 according to the address of the fifth PMIC unit 125 set by the fifth address resistor 135;
the sixth address resistor 136 is used to set the address of the sixth PMIC unit 126, i.e., the address of the fourth PMIC chip 1261, and the ARM chip 11 determines the address of the sixth PMIC unit 126 according to the address of the sixth PMIC unit 126 set by the sixth address resistor 136.
The ARM chip 11 distinguishes the PMIC units by the addresses, so as to read the output voltage and the output current of all the PMIC units, thereby calculating the power consumption of the FPGA chip.
In specific implementation, as shown in fig. 8, the ARM chip 11 is connected to all PMIC units through PMBus, the ARM chip 11 reads the output voltage and the output current collected by each PMIC unit through PMBus, multiplies the obtained output voltage and the output current corresponding to the obtained output voltage, and sums up all products to obtain the power consumption of the whole FPGA chip.
Based on the same concept, an embodiment of the present application further provides an FPGA accelerator card, which includes an FPGA chip and any one of the power supply devices for the FPGA chip, and the implementation of the FPGA accelerator card may refer to the implementation of any one of the power supply devices for the FPGA chip, and repeated parts are not described again.
According to the embodiment of the application, the whole real-time power consumption of the FPGA chip can be obtained, and a reference basis can be provided for evaluating the performance power consumption ratio of the FPGA accelerator card and the board card power supply specification.
Based on the same concept, an embodiment of the present application further provides an electronic device, where the electronic device includes any one of the above power supply devices for an FPGA chip or includes the above FPGA accelerator card, and the implementation of the electronic device may refer to the implementation of any one of the above power supply devices for an FPGA chip, and repeated details are omitted.
Specifically, the electronic device may be a video card, a server, a computer motherboard, and the like, where the type of the server may be a computing integrated machine supporting privacy, and the like, which are merely exemplified above, but not limited to the above.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims (12)

1. A power supply device for an FPGA chip, the device comprising: the FPGA chip comprises an ARM chip and a plurality of PMIC units corresponding to a power supply module in the FPGA chip;
the ARM chip is electrically connected with the first end of each PMIC unit, and the second end of each PMIC unit is electrically connected with the corresponding powered module;
for each PMIC unit: the PMIC unit is used for supplying power to a power supply module connected with the PMIC unit and acquiring the output voltage and the output current of the PMIC unit;
and the ARM chip is used for calculating the power consumption of the FPGA chip according to the output voltage and the output current acquired by each PMIC unit.
2. The apparatus of claim 1, wherein the plurality of PMIC units comprise some or all of:
the first PMIC unit is used for supplying power to a core unit in the FPGA chip;
a second PMIC unit for powering a memory in the FPGA chip;
a third PMIC unit for supplying power to an auxiliary power supply unit in the FPGA chip;
a fourth PMIC unit for powering a transceiver analog unit in the FPGA chip;
a fifth PMIC unit for powering a transceiver digital unit in the FPGA chip;
and the sixth PMIC unit is used for supplying power to the IO unit in the FPGA chip.
3. The apparatus of claim 2, wherein the first PMIC unit comprises a first PWM controller and a plurality of first power chips;
the output end of the first PWM controller is electrically connected with the control end of each first power chip, and the first PWM controller is used for controlling each first power chip to supply power to the core unit;
for each first power chip: the power output end of the first power chip is electrically connected with the voltage acquisition end of the first power chip, the current acquisition end of the first power chip and the kernel unit, the control signal output end of the first power chip is electrically connected with the input end of the ARM chip, and the first power chip is used for supplying power to the kernel unit and acquiring the voltage and the current of the output end of the first power chip.
4. The apparatus of claim 2, wherein the second PMIC unit comprises a second PWM controller and a second power chip;
the output end of the second PWM controller is electrically connected with the control end of the second power chip, and the second PWM controller is used for controlling the second power chip to supply power to the memory;
the power output end of the second power chip is electrically connected with the voltage acquisition end of the second power chip, the current acquisition end of the second power chip and the memory, the control signal output end of the second power chip is electrically connected with the input end of the ARM chip, and the second power chip is used for supplying power to the memory and acquiring the voltage and the current of the output end of the second power chip.
5. The apparatus of claim 2, wherein the third PMIC unit comprises a first PMIC chip;
the power supply output end of the first PMIC chip is electrically connected with the current collection end of the first PMIC chip, the voltage collection end of the first PMIC chip and the auxiliary power supply unit, and the control signal output end of the first PMIC chip is electrically connected with the input end of the ARM chip;
the first PMIC chip is used for supplying power to the auxiliary power supply unit and collecting voltage and current of an output end of the first PMIC chip.
6. The apparatus of claim 2, wherein the fourth PMIC unit comprises a second PMIC chip;
the power supply output end of the second PMIC chip is electrically connected with the current acquisition end of the second PMIC chip, the voltage acquisition end of the second PMIC chip and the transceiver simulation unit, and the control signal output end of the second PMIC chip is electrically connected with the input end of the ARM chip;
and the second PMIC chip is used for supplying power to the transceiver analog unit and collecting the voltage and the current of the output end of the second PMIC chip.
7. The apparatus of claim 2, wherein the fifth PMIC unit comprises a third PMIC chip;
a power supply output end of the third PMIC chip is electrically connected with a current acquisition end of the third PMIC chip, a voltage acquisition end of the third PMIC chip and the transceiver digital unit, and a control signal output end of the third PMIC chip is electrically connected with an input end of the ARM chip;
and the third PMIC chip is used for supplying power to the transceiver digital unit and collecting the voltage and the current of the output end of the third PMIC chip.
8. The apparatus of claim 2, wherein the sixth PMIC unit comprises a fourth PMIC chip;
a power supply output end of the fourth PMIC chip is electrically connected with a current collection end of the fourth PMIC chip, a voltage collection end of the fourth PMIC chip and the IO unit, and a control signal output end of the fourth PMIC chip is electrically connected with an input end of the ARM chip;
and the fourth PMIC chip is used for supplying power to the IO unit and collecting the voltage and the current of the output end of the fourth PMIC chip.
9. The apparatus of any of claims 1 to 8, further comprising an address resistor corresponding to each PMIC cell;
for each address resistance: the address resistor is connected with the corresponding PMIC unit and used for setting the address of the PMIC unit;
the ARM chip is further used for determining the address of the PMIC unit corresponding to each address resistor according to the address of the PMIC unit set by each address resistor.
10. The apparatus of any one of claims 1-8, wherein the ARM chip is specifically configured to:
for each set of output voltage and output current: performing product processing on the output voltage and the output current to obtain output power;
and adding the obtained output powers, and taking the obtained sum as the power consumption of the FPGA chip.
11. An FPGA accelerator card comprising an FPGA chip and a power supply apparatus for the FPGA chip as claimed in any one of claims 1 to 10.
12. An electronic device, characterized in that it comprises a power supply device for an FPGA chip according to any one of claims 1 to 10 or comprises an FPGA accelerator card according to claim 11.
CN202223039124.XU 2022-11-15 2022-11-15 Power supply device for FPGA chip, FPGA accelerator card and electronic equipment Active CN218886548U (en)

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CN202223039124.XU CN218886548U (en) 2022-11-15 2022-11-15 Power supply device for FPGA chip, FPGA accelerator card and electronic equipment

Applications Claiming Priority (1)

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CN202223039124.XU CN218886548U (en) 2022-11-15 2022-11-15 Power supply device for FPGA chip, FPGA accelerator card and electronic equipment

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