CN218867107U

CN218867107U - System-on-chip and electronic device

Info

Publication number: CN218867107U
Application number: CN202223283312.7U
Authority: CN
Inventors: 谢灿; 刘志
Original assignee: Zhaoyi Innovation Technology Group Co ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd
Priority date: 2022-12-07
Filing date: 2022-12-07
Publication date: 2023-04-14
Anticipated expiration: 2032-12-07

Abstract

The utility model provides a system level chip and electronic equipment, the output port of the LDO circuit in the piece is not directly for the digital circuit power supply in the piece, but link to each other with the encapsulation pin through first bonding wire earlier, after the external big off-chip capacitor filtering of encapsulation pin, the second bonding wire on the rethread this encapsulation pin links to each other with the digital circuit's in the piece power port, solved among the prior art because the bonding wire equivalent parasitic big inductance and the digital circuit's in the piece equivalent capacitance combined action causes the problem of influence to LDO circuit stability from this.

Description

System-on-chip and electronic device

Technical Field

The utility model relates to an integrated circuit technical field, in particular to system level chip and electronic equipment.

Background

Because a Low-dropout regulator (LDO) has the characteristics of simple circuit, low noise, low voltage drop, low power consumption, and the like, in a System-on-Chip (SoC Chip), for example, an individual LDO circuit is required to be used as a power supply of a digital circuit (which may also be referred to as a digital area), that is, to supply power to the digital circuit of the SoC Chip.

At present, in the design of an SoC chip, a common structure of an LDO circuit is an external large off-chip capacitor (the external capacitor refers to a capacitor located outside a package of the SoC chip), specifically, an output port of the LDO circuit is connected to a power port of a digital circuit in a chip, and then is further led to a package pin of the SoC chip through a bonding wire (bonding wire), and the package pin of the SoC chip is further externally connected with the large off-chip capacitor, so as to ensure the stability of the LDO circuit, and the capacitance values of the off-chip capacitors are in the order of μ F, so that the on-chip integration in the SoC chip cannot be performed.

However, in some SoC chip packages, the parasitic parameters of the bonding wires may easily cause poor stability of the LDO circuit.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a system level chip and electronic equipment can make the stability of inside low dropout linear regulator (LDO) circuit be difficult to receive the influence of the parasitic parameter of bonding wire.

In order to achieve the above object, the utility model provides a system level chip, the on-chip integration has low dropout linear regulator circuit and digital circuit, just system level chip still has the encapsulation pin that is used for external chip outer electric capacity, the output port of low dropout linear regulator circuit through first bonding wire with the encapsulation pin links to each other, digital circuit's power port pass through the second bonding wire with the encapsulation pin links to each other.

Optionally, the off-chip capacitor has a capacitance value on the order of μ F.

Optionally, the equivalent capacitance of the digital circuit is 0 to 20nF.

Optionally, the output port of the low dropout regulator circuit and the power port of the digital circuit are both pads in the chip of the system-on-chip, at least a portion of the package pin is exposed outside the package of the system-on-chip, and the off-chip capacitor is located outside the package of the system-on-chip.

Optionally, the first bonding wire and the second bonding wire are both located outside a chip of the system-on-chip; one end of the first bonding wire is bonded to a bonding pad of an output port of the low dropout linear regulator circuit, and the other end of the first bonding wire is bonded to the packaging pin; one end of the second bonding wire is bonded to a bonding pad of a power supply port of the digital circuit, and the other end of the second bonding wire is bonded to the packaging pin.

Optionally, the low dropout regulator circuit includes an error amplifier, an output power transistor, and a feedback circuit, an input terminal of the error amplifier is coupled to an output terminal of the feedback circuit, an output terminal of the error amplifier is coupled to a gate of the output power transistor, and a drain of the output power transistor and an input terminal of the feedback circuit are both coupled to an output port of the low dropout regulator circuit.

Optionally, the feedback circuit includes a first feedback resistor and a second feedback resistor, one end of the first feedback resistor is coupled to the output port of the low dropout regulator circuit, the other end of the first feedback resistor is coupled to one end of the second feedback resistor, and the other end of the second feedback resistor is grounded.

Optionally, the output of the low dropout linear regulator circuit is filtered by the off-chip capacitor to power the digital circuit.

Based on same utility model the design, the utility model discloses still provide an electronic equipment, it has the system level chip, and, external be in the outer electric capacity of piece on the encapsulation pin of system level chip.

Compared with the prior art, the technical scheme of the utility model one of following beneficial effect has at least:

1. the method improves the bonding wire connection mode of the output port of the LDO circuit, and particularly, the output port of the LDO circuit in a system level chip sheet does not directly supply power to a digital circuit in the sheet, but is connected with a packaging pin through a first bonding wire, filtered by a large off-chip capacitor externally hung on the packaging pin and connected with a power supply port of the digital circuit in the sheet through a second bonding wire on the packaging pin, so that the problem that the stability of the LDO circuit is influenced due to the combined action of a parasitic large inductor equivalent to the bonding wire and an equivalent capacitor of the digital circuit in the sheet in the prior art is solved.

2. The scheme is simple, the general adaptability is realized, the good effect is achieved for any LDO circuit structure which has large off-chip capacitance and supplies power to a digital circuit in the system level chip, the reliability of the LDO circuit can be effectively improved, and the performances of the system level chip and the electronic equipment with the system level chip are provided.

Drawings

It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:

FIG. 1 is a schematic diagram of an LDO circuit with off-chip large capacitance connected to a bond wire.

FIG. 2 is a frequency response curve of the LDO circuit shown in FIG. 1.

Fig. 3 is a schematic structural diagram of the SoC chip of the present invention.

Fig. 4 is a frequency response curve of the LDO circuit in the SoC chip shown in fig. 3.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention. It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. It will be understood that when an element is referred to as being "connected to," "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The technical solution provided by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to precise scale, which is only used for the purpose of facilitating and clearly explaining the embodiments of the present invention.

An output port bonding wire connection manner of a typical low dropout regulator circuit LDO with an off-chip large capacitor in an existing system-on-chip, such as a system-on-chip SoC chip or a processing chip with multiple voltage domains, is shown in fig. 1, where the system-on-chip takes an SoC chip as an example, the low dropout regulator circuit LDO (hereinafter, abbreviated as LDO circuit) includes an error amplifier EA, an output power tube MP and feedback resistors R1 and R2, a connection node of the output power tube MP and the feedback resistor R1 is an output port VO of the LDO circuit, the output port VO of the LDO circuit is also a power port of the digital circuit 10 in the SoC chip to supply power to the digital circuit 10 in the SoC chip, and the output port VO of the LDO circuit is further connected to a package pin VCAP of the SoC chip through an off-chip (bonding wire) 20, and further connected to an off-chip large capacitor C connected to the package pin VCAP of the SoC chip _ext And (6) electrically connecting. The error amplifier EA controls the on and off of the output power tube MP according to the reference voltage VREF and the feedback voltage of the connection node of the R1 and the R2, thereby controlling the output port VO of the LDO to supply power to the digital circuit 10 in the SoC chip. Capacitor C _int The value of the equivalent capacitive load of the digital circuit 10 is typically in the range of a few nF to a dozen nF. Off-chip capacitor C connected to package pin VCAP _ext Is in the order of μ F. r is _b 、l _b Equivalent parasitic resistance and parasitic inductance of the bond wire 20, respectively, and the bond wire 20 has an equivalent parasitic capacitance C from the package pin VCAP to ground _b The value is in pF magnitude, and the capacitor C outside the follower _ext In contrast, the value is too small, and therefore the parasitic capacitance C is not shown in fig. 1 _b 。

With continued reference to fig. 1, the expression of the output impedance Zout as seen from the output port VO of the LDO circuit to the package pin VCAP is:

with C _int Is 10nF _ext Parasitic inductance l equivalent to the bond wire 20 of 4.7 muF _b 10nH, equivalent parasitic resistance r _b For example 300m Ω, the pole contributed by the output impedance Zout is determined by:

thus, there are:

the output impedance Zout contributes a pair of conjugate poles whose mode is determined by:

from this, one can see the equivalent parasitic large inductance l on the bond wire 20 _b Load capacitor C equivalent to digital circuit in SoC chip _int A pair of conjugate poles are brought to an LDO circuit in an SoC chip, and when an output port VO of the LDO circuit carries a large load current, the conjugate poles are close to a Gain bandwidth product GBW (Gain Band Width) of the LDO circuit, so that the out-of-Band phase of the LDO circuit is sharpThe gain margin is reduced, and the stability of the LDO circuit is seriously influenced.

Referring to fig. 2, fig. 2 shows an amplitude-frequency curve (Loop Gain-freq) and a Phase-frequency curve (Loop Phase-freq) of a Loop (Loop) when the LDO circuit has a load current of 500mA, from the amplitude-frequency curve of the LDO circuit, the Loop Gain (Gain) first drops below 0dB, then starts to rise due to the influence of the conjugate pole pair, and the Phase (Phase) of the Phase-frequency curve drops sharply at this time, when the Phase drops to 0, the value of the Loop Gain is positive at this time, so that the Gain margin does not meet the requirement, and the Loop is unstable and oscillates when the LDO circuit has a load current of 500 mA.

Moreover, the larger the load current carried by the LDO circuit, the larger the GBW value thereof, which means the equivalent parasitic large inductance l of the bonding wire 20 _b Equivalent capacitance load C of digital circuit in SoC chip _int The closer the formed conjugate pole pair is to the GBW of the LDO circuit, the greater the influence on the stability of the LDO circuit. In addition, once the maximum load current of the LDO circuit is determined, the maximum value of GBW of the LDO circuit is determined, and the influence of the conjugate pole pair on the stability of the LDO circuit can be reduced by pushing the conjugate pole pair to a high frequency. l _b 、C _int The smaller the value of (c), the higher the frequency value of the conjugate pole pair is generated, but when the package type is determined, l _b The value of (A) is determined, and C _int Is related to the area size of the digital circuit in the SoC chip, and is also an unchangeable value, thereby reducing l _b 、C _int Is not preferable in this case.

That is, under some SoC chip packages, the parasitic inductance l of the bonding wire 20 _b The LDO circuit is easy to have poor stability, which is similar to the equivalent capacitance load C of the digital circuit in the SoC chip _int A conjugate pole pair is formed and still easily affects the stability of the LDO circuit.

To the above problem, the utility model provides a system level chip (for example the SoC chip, all refer to the system level chip with the SoC chip after this, nevertheless the utility model discloses be not limited to the SoC chip), its bonding wire connected mode through the output port that improves the LDO circuit shields the combined action of the parasitic parameter of equivalent electric capacity and bonding wire equivalence of digital circuit in the SoC chip, makes the stability of LDO circuit be difficult to receive the influence of the parasitic parameter of bonding wire.

Specifically, referring to fig. 3, an embodiment of the present invention provides a system-on-chip (hereinafter referred to as SoC chip), which has a low dropout regulator (LDO) circuit and a digital circuit 10 integrated therein, and the SoC chip further has an external capacitor C for external connection _ext The output port VO of the LDO circuit is connected to the package pin VCAP through a first bonding wire 21, and the power port VO _ INT of the digital circuit 10 is connected to the package pin VCAP through a second bonding wire 22. Off-chip capacitor C _ext It is possible to have a capacitance value in the order of muf. Off-chip capacitor C _ext And the chip is positioned outside the chip of the SoC chip and is positioned outside the package of the system-on-chip.

In this embodiment, the output port VO of the LDO circuit and the power port VO _ INT of the digital circuit 10 are respectively different pads (pads) in the SoC chip, and at least a portion of the package pin VCAP is exposed outside a package (package) of the SoC chip. The first bonding wire 21 and the second bonding wire 22 are both located outside the SoC chip, one end of the first bonding wire 21 is bonded to a pad of the output port VO of the LDO circuit and the other end is bonded to the package pin VCAP, one end of the second bonding wire 22 is bonded to a pad of the power port VO _ INT of the digital circuit 10 and the other end is bonded to the package pin VCAP. It is worth noting that the utility model discloses the inside that the "piece" that indicates SoC chip's bare chip (die), the utility model discloses the outside that the "piece of saying" indicates SoC chip's bare chip (die), different pads in SoC chip's the piece can be connected to this SoC chip different encapsulation pins outside the piece via respective bonding wire, and these encapsulation pins all are located SoC chip's bare chip's piece outside, and expose at least the encapsulation outside in SoC chip. Notably, the first and

second bond wires

21, 22 are both located off-chip of the SoC chip die but still within the package of the SoC chip.

In this embodiment, LDO circuit and digital circuit 10 may adopt any suitable circuit design, and the present invention is not specifically limited to this. For example, the LDO circuit includes an error amplifier EA, an output power transistor MP, and a feedback circuit, an input terminal of the feedback circuit is coupled to the output port VO of the LDO circuit, and an output terminal of the feedback circuit is coupled to an input terminal "+" of the error amplifier EA, for providing a feedback voltage VFB for feeding back a voltage variation of the output port VO of the LDO circuit to the error amplifier EA. The output end of the error amplifier EA is coupled to the gate of the output power transistor MP, and the drain of the output power transistor MP is coupled to the output port VO of the LDO circuit. The source of the output power transistor MP can be connected to a corresponding input voltage (not shown). The feedback circuit may be implemented by any suitable circuit design, for example, the feedback circuit includes a first feedback resistor R1 and a second feedback resistor R2, one end of the first feedback resistor R1 is coupled to the output port VO of the LDO circuit, the other end of the first feedback resistor R1 is coupled to one end of the second feedback resistor R2, and the other end of the second feedback resistor R2 is grounded. The other input end of the error amplifier EA is connected to a reference voltage VREF, the reference voltage VREF may be provided by a band-gap reference voltage source in the chip, the error amplifier EA controls the on and off of the output power tube MP according to the reference voltage VREF and the feedback voltage VFB, so that the corresponding input voltage is converted into the corresponding output voltage, the output voltage is output through the output port VO, and then the digital circuit 10 is supplied with power through the first bonding wire 21, the package pin VCAP, the second bonding wire 22 and the power port VO _ INT.

Obviously, the SoC chip of this embodiment differs from the prior art shown in fig. 1 in that the output port (pad) VO of the LDO circuit does not directly supply power to the digital circuit 10 inside the SoC chip, but is connected to the package pin VCAP through the first bonding wire 21, and passes through the large off-chip capacitor C _ext After filtering, the output of the LDO circuit is connected to the power port (pad) VO _ INT of the digital circuit 10 inside the SoC chip through the second bonding wire 22 on the package pin VCAP, i.e. the output of the digital circuit is connected to the off-chip capacitor C _ext Filtered and then supplied to the digital circuit 10. It should be noted that, a system-on-chip (e.g., soC chip, etc.) often includes a multi-voltage domain circuit, and the voltage required by the digital circuit 10 is often lower than other circuits of the system-on-chip, so that a special LDO circuit is required to process the power voltage and then supply the processed power voltage to the digital circuit 10The source network supplies power.

Defining the equivalent parasitic resistance of the first bonding wire 21 as r _b1 Parasitic inductance of l _b1 The equivalent parasitic resistance of the second bond wire 22 is r _b2 Parasitic inductance of l _b2 Then the expression of the output impedance Zout1 is:

when in the above formula C _int Is 10nF _ext At 4.7 μ F, there are:

as can be seen from the above equation, due to the large off-chip capacitance C _ext Is present, shielding C _int The influence on the LDO circuit, therefore, the equivalent parasitic large inductance of the first bonding wire 21 and the second bonding wire 22 and the equivalent capacitance C of the digital circuit 10 _int Conjugate pole pairs can not be generated, and the improved bonding wire connection mode solves the problem that the LDO stability is influenced due to the combined action of a parasitic large inductor equivalent to the bonding wire and an equivalent capacitor in a digital area inside an SoC chip.

In this embodiment, under the condition that the LDO circuit has a 500mA load current, the Gain Margin (GM) of the LDO circuit follows C _int Is shown in FIG. 4, and C can be seen _int When the gain margin changes from 0nF to 20nF, the gain margin has reasonable value and small change, which shows that the output port VO of the LDO circuit is firstly connected to the packaging pin VCAP through the first bonding wire 21 and passes through the large off-chip capacitor C _ext After the filtering, the equivalent capacitor C of the digital circuit 10 is shielded by the connection mode that the second bonding wire 22 on the package pin VCAP is connected with the power port VO _ INT of the digital circuit 10 in the SoC chip _int Influence on LDO Circuit stability, equivalent capacitance C of digital Circuit 10 _int Equivalent inductance l to the first bonding wire 21 and the second bonding wire 22 _b1 、l _b2 No conjugate pole is generatedIn contrast, the stability of the LDO circuit is not easily affected by package parasitic parameters.

The bonding wire connection mode between the output port VO of the LDO circuit and the power port VO _ INT of the digital circuit 10 of this embodiment has general adaptability, and has a good effect on any LDO circuit structure with a large off-chip capacitance and supplying power to the digital circuit inside the system-on-chip, and can effectively improve the influence of the bonding wire on the stability of the LDO circuit.

In addition, referring to fig. 3, the present embodiment further provides an electronic device having the system-on-chip (for example, soC chip) described in the present embodiment and an off-chip capacitor C externally connected to a package pin VCAP of the system-on-chip _ext A first bonding wire 21 and a second bonding wire 22. One end of the first bonding wire 21, one end of the second bonding wire 22, and the off-chip capacitor C _ext One end of the first bonding wire 21 is connected to the package pin VCAP, the other end of the first bonding wire 21 is connected to the output port VO of the LDO circuit in the system-on-chip (for example, soC chip), the other end of the second bonding wire 22 is connected to the power port VO _ INT of the digital circuit 10 in the system-on-chip (for example, soC chip), and the off-chip capacitor C _ext And the other end of the same is grounded.

It should be understood that, in the above embodiments, only the core of the LDO circuit, the LDO circuit in a system-on-chip (for example, an SoC chip), and the equivalent capacitance of the digital circuit are shown, but the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, the LDO circuit may further include a bandgap reference voltage source (not shown) and other circuits for providing a reference voltage VREF, and functional circuits such as a corresponding signal acquisition circuit, an analog-to-digital conversion circuit, a memory, an embedded computing engine (a microprocessor, a microcontroller, or a DSP processor, etc.), an input and output (I/O) circuit, and a programmable logic circuit may also be integrated in the SoC chip. The electronic device with the system-on-chip (e.g., soC-chip) may further include peripherals mounted on the system-on-chip (e.g., soC-chip), such as a display, a keyboard (mechanical or touch keyboard), key switches, indicator lights, voice devices (microphone, speaker), and the like.

The above description is only for the description of the preferred embodiment of the present invention, and not for any limitation of the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure all belong to the protection scope of the technical solution of the present invention.

Claims

1. A system-on-chip (SOC) is integrated with a low dropout regulator circuit and a digital circuit, and is characterized in that the SOC is also provided with a packaging pin for externally connecting an off-chip capacitor, an output port of the LDO circuit is connected with the packaging pin through a first bonding wire, and a power supply port of the digital circuit is connected with the packaging pin through a second bonding wire.

2. The system-on-chip of claim 1, in which the off-chip capacitor has a capacitance value on the order of μ F.

3. The system-on-chip of claim 1 wherein the digital circuit has an equivalent capacitance of 0 to 20nF.

4. The system-on-chip of claim 1, wherein the output port of the low dropout linear regulator circuit and the power port of the digital circuit are pads within an on-chip of the system-on-chip, wherein at least a portion of the package pins are exposed outside a package of the system-on-chip, and wherein the off-chip capacitors are located outside the package of the system-on-chip.

5. The system-on-chip of claim 1, wherein the first bond wire and the second bond wire are both located off-chip from the system-on-chip; one end of the first bonding wire is bonded to a bonding pad of an output port of the low dropout linear regulator circuit, and the other end of the first bonding wire is bonded to the packaging pin; one end of the second bonding wire is bonded to a bonding pad of a power supply port of the digital circuit, and the other end of the second bonding wire is bonded to the packaging pin.

6. The system-on-chip of any one of claims 1-5, wherein the LDO circuit comprises an error amplifier, an output power transistor, and a feedback circuit, wherein an input of the error amplifier is coupled to an output of the feedback circuit, an output of the error amplifier is coupled to a gate of the output power transistor, and a drain of the output power transistor and an input of the feedback circuit are both coupled to an output port of the LDO circuit.

7. The system-on-chip of claim 6, wherein the feedback circuit comprises a first feedback resistor and a second feedback resistor, one end of the first feedback resistor is coupled to the output port of the low dropout linear regulator circuit, the other end of the first feedback resistor is coupled to one end of the second feedback resistor, and the other end of the second feedback resistor is grounded.

8. The system-on-chip of claim 1 wherein an output of the low dropout linear regulator circuit is filtered via the off-chip capacitor to power the digital circuit.

9. An electronic device, characterized by a system-on-chip according to any of claims 1-8 and an off-chip capacitor externally connected to package pins of the system-on-chip.