CN218866478U - High-reliability large-current operational amplifier layout structure - Google Patents
High-reliability large-current operational amplifier layout structure Download PDFInfo
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- CN218866478U CN218866478U CN202223111598.0U CN202223111598U CN218866478U CN 218866478 U CN218866478 U CN 218866478U CN 202223111598 U CN202223111598 U CN 202223111598U CN 218866478 U CN218866478 U CN 218866478U
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Abstract
The utility model discloses a high reliability heavy current operational amplifier's domain structure contains first domain region, the second domain region, the third domain region, the fourth domain region, and the fifth domain region, the sixth domain region, the seventh domain region, the eighth domain region, the ninth domain region, the tenth domain region, the eleventh domain region, the twelfth domain region, the utility model provides a domain structure of the heavy current operational amplifier of internal integration band gap reference source and ESD electrostatic protection device has under the prerequisite of stronger anti ESD ability when fully considering current operational amplifier need have great current output ability, through the reasonable layout wiring design to the domain, has realized current operational amplifier's circuit function better, makes the reliability of the chip of design high, output current ability is strong, the security is high.
Description
Technical Field
The utility model relates to an integrated circuit design field, a high reliability heavy current operational amplifier territory structure of specific design.
Background
With the rapid development of integrated circuit design, the process is mature, so that the device size is moving towards the limit of moore's law. In the face of more and more advanced nano-fabrication processes, more and more effects are being considered in the design of integrated circuits. ESD is one of the key factors affecting the reliability of integrated circuit chips, and it causes billions of dollars of losses in the world electronics industry in terms of IC yield and early field failures each year, with the failure of chips by ESD accounting for more than 12% of the total number of chip failures.
The amplifier plays an important role in an integrated circuit, the high-reliability large-driving-current operational amplifier also plays an important role in the driving field, and although a large number of products of large-current driving operational amplifiers exist, the electrostatic protection level of the operational amplifiers is low.
Therefore, those skilled in the art are dedicated to develop a high-reliability large-current operational amplifier layout structure with a higher ESD protection level and a larger output current capability.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model aims to solve the technical problem that a high reliability heavy current operational amplifier territory structure is provided, its reasonable layout and wiring through to the chip territory increases ESD protective device, extension protection ring and reasonable design output level power tube territory structure, has improved current operational amplifier's electrostatic protection level and has improved current operational amplifier's output current ability.
The utility model provides a technical scheme of above-mentioned problem is:
a high reliability heavy current operational amplifier territory structure which characterized in that: the layout structure comprises a first layout region, a second layout region, a third layout region, a fourth layout region, a fifth layout region, a sixth layout region, a seventh layout region, an eighth layout region, a ninth layout region, a tenth layout region, an eleventh layout region and a twelfth layout region; the first layout region, the second layout region, the fifth layout region, the sixth layout region, the seventh layout region, the eighth layout region, the ninth layout region and the tenth layout region are all rectangular, and the third layout region, the fourth layout region, the eleventh layout region and the twelfth layout region are octagonal; the outermost periphery of the layout structure is the eleventh layout area, the other layout areas are surrounded by the eleventh layout area, and the layout area surrounded by the eleventh layout area is set as a first surrounding area; the fifth layout region and the sixth layout region are positioned at the uppermost edge of the first surrounding region, and the fifth layout region is positioned at the right left edge of the sixth layout region; the seventh layout area and the eighth layout area are positioned on the leftmost side of the first surrounding area, and the seventh layout area is positioned right above the eighth layout area; the ninth layout area is positioned on the rightmost side of the first surrounding area; the tenth layout area is positioned at the lowest part of the first surrounding area; the twelfth layout region is positioned in the middle of the layout structure and is surrounded by the fifth layout region, the sixth layout region, the seventh layout region, the eighth layout region, the ninth layout region, the tenth layout region, the first layout region, the second layout region, the third layout region and the fourth layout region, and the layout region surrounded by the twelfth layout region is set as a second surrounding region; the first layout area is positioned at the upper left corner of the second surrounding area; the second layout area is positioned at the lower right corner of the second surrounding area; the third layout area is positioned at the upper right corner of the second surrounding area; the fourth layout area is positioned at the lower right corner of the second surrounding area;
the first layout area is a bias module for providing current for the second layout area;
the second layout area is an amplifying module for amplifying and outputting the received input signal;
the third layout area and the fourth layout area are output modules for expanding output current;
the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area and the ninth layout area are used for electrostatic protection of the circuit so as to improve the reliability of the circuit;
the tenth layout area is a ground terminal PAD for the current operational amplifier;
the eleventh layout area and the twelfth layout area are protection rings for the circuit, so that the reliability and the safety of the circuit are improved;
further, the first layout area is a band-gap reference source module and provides bias current for the current operational amplifier of the second layout area.
Furthermore, the second layout area is an input and amplification module of a current operational amplifier, and provides amplification signals for the third layout area and the fourth layout area.
Further, the third layout area and the fourth layout area are current operational amplifier output power tube modules for expanding output current.
Furthermore, the fifth layout region, the sixth layout region, the seventh layout region, the eighth layout region and the ninth layout region are ESD device modules, and are used for providing ESD protection for a circuit and improving the reliability of the circuit. The fifth layout area is used for performing electrostatic protection on the power supply port, and the sixth layout area, the seventh layout area, the eighth layout area and the ninth layout area are respectively used for performing electrostatic protection on an enabling port, a same-phase input port, a reverse input port and an output port of the circuit.
Further, the tenth layout area is a circuit ground PAD.
Furthermore, the eleventh layout area and the twelfth layout area are protection rings of the circuit, and the protection rings are used for reducing interference of external noise to the circuit and mutual interference of signals among the circuit modules.
Furthermore, the fourth layout area, the fifth layout area, the eleventh layout area and the twelfth layout area are octagonal, so that point discharge is prevented, the reliability and the safety of the circuit are improved, the layout area is properly widened, and the output current capability of the circuit is expanded.
Therefore, the utility model provides a high reliability heavy current operational amplifier territory structure, through the reasonable layout design to individual territory, the reinforced circuit ESD protective capability when making the circuit have great output current ability, has improved the electrostatic protection grade of circuit, has strengthened the circuit reliability.
The conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings, so as to fully understand the objects, the features and the effects of the present invention.
Drawings
Fig. 1 is a schematic structural diagram of a preferred embodiment of the present invention;
FIG. 2 is a diagram illustrating a preferred layout and wiring of the present invention;
fig. 3 is a layout diagram of a preferred first layout area according to the present invention;
fig. 4 is a layout diagram of a preferred second layout area according to the present invention;
fig. 5 is a layout diagram of a preferred third layout area according to the present invention;
fig. 6 is a layout diagram of a fourth layout area according to a preferred embodiment of the present invention;
fig. 7 is a layout diagram of a fifth preferred layout area according to the present invention;
fig. 8 is a layout diagram of a sixth layout area according to the present invention;
fig. 9 is a layout diagram of a seventh layout area according to the present invention;
fig. 10 is a layout diagram of an eighth preferred layout area according to the present invention;
fig. 11 is a layout diagram of a ninth layout area according to the present invention;
fig. 12 is a layout diagram of a tenth preferred layout area according to the present invention;
fig. 13 is a layout diagram of an eleventh layout area according to the present invention;
fig. 14 is a layout diagram of a twelfth layout region according to the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and examples.
A high-reliability large-current operational amplifier layout structure is shown in figures 1 and 2, and comprises a first layout region (such as figure 3), a second layout region (such as figure 4), a third layout region (such as figure 5), a fourth layout region (such as figure 6), a fifth layout region (such as figure 7), a sixth layout region (such as figure 8), a seventh layout region (such as figure 9), an eighth layout region (such as figure 10), a ninth layout region (such as figure 11), a tenth layout region (such as figure 12), an eleventh layout region (such as figure 13) and a twelfth layout region (such as figure 14); the first layout region, the second layout region, the fifth layout region, the sixth layout region, the seventh layout region, the eighth layout region, the ninth layout region and the tenth layout region are all rectangular, and the third layout region, the fourth layout region, the eleventh layout region and the twelfth layout region are octagonal; the outermost periphery of the layout structure is the eleventh layout region, the other layout regions are surrounded by the eleventh layout region, and the layout region surrounded by the eleventh layout region is set as a first surrounding region; the fifth layout area and the sixth layout area are positioned at the uppermost edge of the first surrounding area, and the fifth layout area is positioned at the right left edge of the sixth layout area; the seventh layout area and the eighth layout area are positioned on the leftmost side of the first surrounding area, and the seventh layout area is positioned right above the eighth layout area; the ninth layout area is positioned on the rightmost side of the first surrounding area; the tenth layout area is positioned at the lowest part of the first surrounding area; the twelfth layout region is positioned in the middle of the layout structure and is surrounded by the fifth layout region, the sixth layout region, the seventh layout region, the eighth layout region, the ninth layout region, the tenth layout region, the first layout region, the second layout region, the third layout region and the fourth layout region, and the layout region surrounded by the twelfth layout region is set as a second surrounding region; the first layout area is positioned at the upper left corner of the second surrounding area; the second layout area is positioned at the lower right corner of the second surrounding area; the third layout area is positioned at the upper right corner of the second surrounding area; the fourth layout area is positioned at the lower right corner of the second surrounding area.
Specifically, as shown in fig. 3, the first layout area is a layout wiring diagram of the first layout area, and the first layout area is a bandgap reference module, which has extremely high temperature stability and provides accurate and stable bias current for the circuit.
As shown in fig. 4, 5, and 6, the layout wiring diagrams of the second layout region, the third layout region, and the fourth layout region together form a layout of the current operational amplifier, the input stage of the current operational amplifier adopts a folding cascode structure to increase the output swing, and the folding cascode amplifying circuit adopts an active load technology to increase the dc gain of the first-stage operational amplifier unit; the circuit adopts a transconductance linear ring structure to provide stable bias voltage for the grid electrode of the output stage power transistor, the output stage adopts a Class-AB structure, the output stage transistor adopts a larger width-length ratio to expand output current, and meanwhile, the output stage transistor is surrounded by a properly widened octagonal protection ring, so that the output current capability of the circuit is further improved, and the adverse effect of point discharge on the circuit is avoided.
As shown in fig. 8, the wiring diagram is laid out in the sixth layout area, the sixth layout area is a power port ESD protection device, and the module adopts an MOS transistor with a certain index and extends the length of the MOS transistor, so as to increase the failure current of the power port ESD protection device, add a resistor and a capacitor, reduce the trigger voltage of the ESD protection device, and perform an electrostatic protection function on the power port.
As shown in fig. 7, fig. 9, fig. 10, and fig. 11, the fifth layout region, the seventh layout region, the eighth layout region, and the ninth layout region are an enable port ESD protection device, a equidirectional input port ESD protection device, an inverse phase input port ESD protection device, and an output port ESD protection device, respectively, and the layout regions are used for increasing the failure current of the power source end ESD protection device and adding a resistor at the same time by using an MOS transistor with a certain index and lengthening the finger length of the MOS transistor, so as to reduce the trigger voltage of the ESD protection device, and perform an electrostatic protection function on the enable end.
As shown in fig. 13 and fig. 14, the eleventh layout region and the twelfth layout region are protection rings of the circuit, and the protection rings are used to reduce interference of external noise to the circuit and mutual interference of signals between each circuit module. By properly widening the layout area of the circuit and using the octagonal layout structure, the output current capability of the circuit can be further improved, the adverse effect of point discharge on the circuit is prevented, and the reliability and the safety of the circuit are further improved.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (10)
1. A high reliability heavy current operational amplifier territory structure which characterized in that: the layout structure comprises a first layout region, a second layout region, a third layout region, a fourth layout region, a fifth layout region, a sixth layout region, a seventh layout region, an eighth layout region, a ninth layout region, a tenth layout region, an eleventh layout region and a twelfth layout region; the first layout area, the second layout area, the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area, the ninth layout area and the tenth layout area are all rectangles, and the third layout area, the fourth layout area, the eleventh layout area and the twelfth layout area are octagons; the outermost periphery of the layout structure is the eleventh layout region, the first layout region, the second layout region, the third layout region and the fourth layout region, the fifth layout region, the sixth layout region, the seventh layout region, the eighth layout region, the ninth layout region, the tenth layout region and the twelfth layout region are surrounded by the eleventh layout region, and the layout region surrounded by the eleventh layout region is set as a first surrounding region; the fifth layout area and the sixth layout area are positioned at the uppermost edge of the first surrounding area, and the fifth layout area is positioned at the right left edge of the sixth layout area; the seventh layout area and the eighth layout area are positioned on the leftmost side of the first surrounding area, and the seventh layout area is positioned right above the eighth layout area; the ninth layout area is positioned on the rightmost side of the first surrounding area; the tenth layout area is positioned at the lowest part of the first surrounding area; the twelfth layout region is positioned in the middle of the layout structure and is surrounded by the fifth layout region, the sixth layout region, the seventh layout region, the eighth layout region, the ninth layout region, the tenth layout region, the first layout region, the second layout region, the third layout region and the fourth layout region, and the layout region surrounded by the twelfth layout region is set as a second surrounding region; the first layout area is positioned at the upper left corner of the second surrounding area; the second layout area is positioned at the lower right corner of the second surrounding area; the third layout area is positioned at the upper right corner of the second surrounding area; the fourth layout area is positioned at the lower right corner of the second surrounding area;
the first layout area is a bias module for providing current for the second layout area;
the second layout area is an amplifying module for amplifying and outputting the received input signal;
the third layout area and the fourth layout area are output modules for expanding output current;
the fifth layout area, the sixth layout area, the seventh layout area, the eighth layout area and the ninth layout area are used for electrostatic protection of the circuit so as to improve the reliability of the circuit;
the tenth layout area is a ground terminal for the current operational amplifier;
and the eleventh layout area and the twelfth layout area are protection rings for the circuit, so that the reliability and the safety of the circuit are improved.
2. The layout structure of a high-reliability high-current operational amplifier according to claim 1, wherein the first layout region is a bandgap reference source module and provides a bias current for the current operational amplifier of the second layout region.
3. The layout structure of a high-reliability high-current operational amplifier according to claim 1, wherein the second layout region is a current operational amplifier input and amplification module, and provides amplification signals for the third layout region and the fourth layout region.
4. The high-reliability large-current operational amplifier layout structure according to claim 1, wherein the third layout region and the fourth layout region are current operational amplifier output power tube modules for expanding output current.
5. The layout structure of the high-reliability high-current operational amplifier according to claim 1, wherein the fifth layout region, the sixth layout region, the seventh layout region, the eighth layout region and the ninth layout region are ESD device modules for providing ESD protection to a circuit and improving the reliability of the circuit.
6. The layout structure of a high-reliability high-current operational amplifier according to claim 5, wherein the fifth layout area is used for performing electrostatic protection on a power port.
7. The layout structure of a high-reliability high-current operational amplifier according to claim 5, wherein the sixth layout region, the seventh layout region, the eighth layout region and the ninth layout region are respectively used for performing electrostatic protection on an enable port, a non-inverting input port, a inverting input port and an output port of a circuit.
8. The high-reliability high-current operational amplifier layout structure according to claim 1, wherein the tenth layout area is a circuit ground PAD.
9. The high-reliability high-current operational amplifier layout structure according to claim 1, wherein the eleventh layout region and the twelfth layout region are protection rings of a circuit.
10. The layout structure of a high-reliability high-current operational amplifier according to claim 1, wherein the fourth layout region, the fifth layout region, the eleventh layout region and the twelfth layout region are octagonal.
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| CN202223111598.0U CN218866478U (en) | 2022-11-22 | 2022-11-22 | High-reliability large-current operational amplifier layout structure |
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| CN202223111598.0U CN218866478U (en) | 2022-11-22 | 2022-11-22 | High-reliability large-current operational amplifier layout structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117439556A (en) * | 2023-12-22 | 2024-01-23 | 成都天成电科科技有限公司 | Cascode amplifier circuit and circuit layout |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117439556A (en) * | 2023-12-22 | 2024-01-23 | 成都天成电科科技有限公司 | Cascode amplifier circuit and circuit layout |
| CN117439556B (en) * | 2023-12-22 | 2024-03-05 | 成都天成电科科技有限公司 | Cascode amplifier circuit and circuit layout |
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