CN218825335U - Circuit with ultra-low power consumption - Google Patents
Circuit with ultra-low power consumption Download PDFInfo
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- CN218825335U CN218825335U CN202223008364.3U CN202223008364U CN218825335U CN 218825335 U CN218825335 U CN 218825335U CN 202223008364 U CN202223008364 U CN 202223008364U CN 218825335 U CN218825335 U CN 218825335U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model discloses an ultra-low power consumption circuit, wherein in, including MOS pipe switch circuit, be equipped with respectively with MOS pipe switch circuit connection's button and button detection circuitry and master control power supply on MOS pipe switch circuit, reach the MOS pipe control circuit who is connected with accuse power supply. The MOS tube control circuit is connected with the MOS tube switch circuit. The MOS tube switching circuit is connected with the voltage input end. The utility model discloses have the effect that reduces standby circuit consumption.
Description
Technical Field
The utility model belongs to the field of medical equipment, in particular to have super low-power consumption circuit in electric power storage charging function product.
Background
At present, in order to reduce power consumption, a main control chip is mainly adopted to reduce the power consumption of products with storage batteries on the market; however, the main control chip actually still provides a certain standby current to the main control chip power IC, so that the main control chip power IC has the required current and is kept in a working state, and the standby current of the whole device at this time cannot be the lowest, so that the purpose of reducing power consumption of the main control chip cannot be achieved in a power consumption reduction mode.
SUMMERY OF THE UTILITY MODEL
In view of the above, an object of the present invention is to provide an ultra-low power circuit that reduces power consumption of a standby circuit.
In order to achieve the above object, the utility model provides a pair of ultra-low power consumption circuit, wherein, including MOS pipe switch circuit, be equipped with respectively with MOS pipe switch circuit connection's button and button detection circuitry and master control power supply on MOS pipe switch circuit, reach the MOS pipe control circuit who is connected with accuse power supply. The MOS tube control circuit is connected with the MOS tube switch circuit. The main control power supply is connected with a host of the electronic product.
In some embodiments, the MOS transistor switch circuit is connected in series with the key and the key detection circuit. The key and the key detection circuit are connected in series with the MOS tube control circuit.
In some embodiments, the power selection circuit is connected in series with the MOS transistor switch circuit.
In some embodiments, the MOS transistor switching circuit includes a transistor Q12, a MOS transistor Q10 connected to an output terminal of the transistor Q12, and an output voltage terminal V _ OUT connected to the MOS transistor. The MOS tube Q10 is provided with a G pole terminal, a D pole terminal and an S pole terminal; the D pole terminal is connected with an output voltage terminal V _ OUT; the triode Q12 is provided with a B pole terminal, a C pole terminal and an E pole terminal; the terminal C of the triode Q12 is connected with the terminal of the MOS transistor Q10G.
In some embodiments, the KEY and KEY detection circuit includes a double diode D19 connected to the MOS transistor Q10, and a KEY1 connected to the double diode D19; the 1 st pin of the double diode D19 is connected with a detection IO port; the 2 nd pin on the double diode D19 is connected with the G pole on the MOS tube Q10; the 3 rd pin of the double diode D19 is connected with the KEY KEY1.
IN some embodiments, the MOS transistor control circuit includes a double diode D18 connected to the MOS transistor Q10, a POWER _ EN output and a USB _ IN _5V output respectively connected to the double diode D18, and a resistor R86 connected IN series to an output of the double diode D18; the POWER _ EN output end is connected with the USB _ IN _5V output end IN parallel; the output terminal of the resistor R86 is connected to the terminal B of the transistor Q12.
IN some embodiments, the POWER _ EN output and the USB _ IN _5V output are connected IN parallel to pins 1 and 2 of the dual diode D18; the 3 rd pin of the double diode D18 is connected in series with a resistor R86.
In some embodiments, the power selection circuit comprises a double diode D20 connected with the MOS transistor Q10, a triode Q11 connected with the double diode D20 in series with the USB input terminal, and connected with the double diode D20 in parallel; the triode Q11 is connected with a battery BAT + end; the S terminal of the MOS transistor Q10 is connected in series with a double diode D20.
The beneficial effects of the utility model are that reduce the purpose of standby circuit consumption. Due to the improved circuit, when the detection key is started, the MOS tube control circuit outputs a state of locking the MOS tube switching circuit by a high level, so that the master control power supply is normal and works normally; when the shutdown of the key is detected, the high level output by the MOS tube control circuit is converted into the low level to disconnect the MOS tube switching circuit, so that the MOS tube switching circuit and the master control power supply are disconnected, the power consumption of electronic products in the shutdown state is reduced to the minimum, and the host is in an ultra-low power consumption state; at the moment, the power supply at the rear end of the MOS tube switching circuit in the shutdown state is completely powered off; through the cooperation of button control MOS pipe and MOS pipe switch circuit for the circuit is in standby state, and MOS pipe switch circuit and master control power supply are outage, reduce power consumptive electronic product to minimum under the standby state, accomplish super low-power consumption standby state, and standby current is less than 1uA this moment, has realized reducing the purpose of standby circuit power consumption.
Drawings
FIG. 1 is a schematic block diagram of the present invention;
fig. 2 is a circuit diagram of the present invention.
Detailed Description
The following describes the present invention in further detail with reference to the accompanying drawings.
As shown in fig. 1-2, an ultra-low power circuit includes a MOS transistor switch circuit, a key and key detection circuit and a master power supply, which are respectively connected to the MOS transistor switch circuit, and a MOS transistor control circuit connected to the master power supply. The MOS tube control circuit is connected with the MOS tube switch circuit. The MOS tube switching circuit is connected with the voltage input end. The MOS tube switching circuit is connected in series with the key and the key detection circuit. The key and the key detection circuit are connected with the MOS tube control circuit in series. The MOS tube switching circuit comprises a triode Q12, an MOS tube Q10 connected with the output end of the triode Q12, and an output voltage end V _ OUT connected with the MOS tube. The MOS tube Q10 is provided with a G pole terminal, a D pole terminal and an S pole terminal. The D pole terminal is connected with the output voltage terminal V _ OUT. And the triode Q12 is provided with a B pole terminal, a C pole terminal and an E pole terminal. And the C pole end of the triode Q12 is connected with the pole end of the MOS transistor Q10G. The KEY and the KEY detection circuit comprise a double diode D19 connected with the MOS tube Q10 and a KEY KEY1 connected with the double diode D19. The 1 st pin of the double diode D19 is connected with the detection IO port. The 2 nd pin of the double diode D19 is connected with the G pole of the MOS transistor Q10. The 3 rd pin of the double diode D19 is connected with the KEY KEY1. During operation, the KEY1 is connected with the 3 rd pin of the double diode D19, the 1 st pin of the diode D19 is connected with the host detection IO port, and the 2 nd pin of the diode D19 is connected with the Q10 (G pole). The purpose is that when the button is pressed, the 3 rd pin of D19 is pulled down to the low level, after D19, the 1 st pin and the 2 nd pin of D19 are both pulled down to the low level, the host computer detects the button after the 1 st pin of D19 is pulled down, after the 2 nd pin of D19 is pulled down, Q10 (G pole) is also pulled down, Q10 (S pole) and Q10 (D pole) are conducted, and the rear end power supply V _ OUT is electrified. The MOS tube control circuit comprises a double diode D18 connected with the MOS tube Q10, a POWER _ EN output end and a USB _ IN _5V output end which are respectively connected with the double diode D18, and a resistor R86 which is connected IN series with the output end of the double diode D18. The output end of the POWER _ EN is connected with the output end of the USB _ IN _5V IN parallel. The output terminal of the resistor R86 is connected to the terminal B of the transistor Q12. During operation, the POWER _ EN output end and the USB _ IN _5V output end are connected IN parallel to the 1 st pin and the 2 nd pin of the dual diode D18, the 3 rd pin of the D18 is connected IN series to the R86, and the R86 is connected to the B pole of the triode Q12. The purpose is that there is output high level all the way between host computer IO (POWER _ EN) and USB input 5V (USB _ IN _ 5V), R86 just becomes high level, and triode Q12 ' S B utmost point becomes high level, and triode Q12 ' S C utmost point and E utmost point switch on, and triode Q12 ' S C utmost point is pulled down and is become low level, and the G utmost point of the Q10 who is connected with triode Q12 becomes low level, and Q10 (S utmost point) and Q10 (D utmost point) switch on, and rear end POWER supply V _ OUT is gone up electrically. The POWER _ EN output and the USB _ IN _5V output are connected IN parallel to pin 1 and pin 2 of the dual diode D18. The 3 rd pin of the double diode D18 is connected in series with a resistor R86.
The power selection circuit is connected with the MOS tube switch circuit in series. The power supply selection circuit comprises a double diode D20 connected with the MOS tube Q10, a triode Q11 connected with the double diode D20 in series with the USB input end and connected with the double diode D20 in parallel. The triode Q11 is connected with a battery BAT + end. The S terminal of the MOS transistor Q10 is connected with the double diode D20 in series. In operation, the USB input terminal is connected in series with the diode D20, and the voltage is output to the MOS transistor Q10 (S-pole) connected in series with the diode D20 via the diode D20. The transistor Q11 (D pole) is connected to the battery BAT +, and the transistor Q11 (S pole) is connected to the double diode D20. The purpose is that when there is 5V for the USB input, the S-voltage of Q10 is 5V for the USB input. If there is no USB input of 5V, the S voltage of Q10 is the battery voltage.
The working principle is as follows:
in a shutdown state, after the KEY1 is pressed, the G pole terminal on the MOS transistor Q10 is pulled down to become a low level, the MOS transistor Q10 is turned on, the output voltage terminal V _ OUT is powered on to supply power to a subsequent circuit, and a host connected with a main control power supply is powered on. After the host is powered on, a high level is output to the output end of the POWER _ EN, the terminal B of the triode Q12 becomes the high level, the triode Q12 is conducted, the terminal C of the triode Q12 is pulled down, and the terminal C is connected with the terminal G of the MOS tube Q10, so that the voltage output end V _ OUT of the MOS tube Q10 is in a continuous conducting state, and a stable POWER supply is supplied to a subsequent master control POWER supply.
In a POWER-on state, when the key and the key detection circuit detect that the key is turned off, the POWER _ EN output end outputs a low level, the MOS transistor Q10 is turned off, the output voltage end V _ OUT is powered off, the subsequent POWER supply is turned off, and the whole circuit of the host connected with the master POWER supply is in an ultra-low POWER consumption state.
IN addition, when a 5V power supply (USB _ IN _ 5V) is input to the adapter, the adapter is connected to the mains supply without considering the condition of low power consumption, the terminal B of the transistor Q12 becomes high level, the transistor Q12 is turned on, the terminal C of the transistor Q12 is pulled low, and the terminal C is connected to the terminal G of the MOS transistor Q10, so that the MOS transistor Q10 is continuously turned on, and the output voltage terminal V _ OUT is continuously powered on to stably supply power to the subsequent circuit.
What has been described above is merely some embodiments of the present invention. For those skilled in the art, without departing from the inventive concept, several modifications and improvements can be made, which all fall within the scope of the invention.
Claims (8)
1. The ultra-low power consumption circuit is characterized by comprising an MOS tube switching circuit, wherein the MOS tube switching circuit is provided with a key, a key detection circuit, a master control power supply and an MOS tube control circuit, wherein the key, the key detection circuit and the master control power supply are respectively connected with the MOS tube switching circuit;
the MOS tube control circuit is connected with the MOS tube switch circuit;
and the MOS tube switching circuit is connected with the voltage input end.
2. The circuit of claim 1, wherein the MOS transistor switching circuit is connected in series with the key and the key detection circuit; the key and the key detection circuit are connected with the MOS tube control circuit in series.
3. The ultra-low power consumption circuit as claimed in claim 1 or 2, further comprising a power selection circuit connected in series with the MOS transistor switching circuit.
4. The ultra-low power consumption circuit as claimed in claim 1, wherein the MOS transistor switching circuit comprises a transistor Q12, a MOS transistor Q10 connected to an output terminal of the transistor Q12, and an output voltage terminal V _ OUT connected to the MOS transistor;
the MOS tube Q10 is provided with a G pole terminal, a D pole terminal and an S pole terminal;
the D pole terminal is connected with the output voltage terminal V _ OUT;
the triode Q12 is provided with a B pole terminal, a C pole terminal and an E pole terminal;
and the C pole end of the triode Q12 is connected with the pole end of the MOS transistor Q10G.
5. The circuit of claim 4, wherein the KEY and KEY detection circuit comprises a double diode D19 connected to the MOS transistor Q10, and a KEY KEY1 connected to the double diode D19;
the 1 st pin of the double diode D19 is connected with a detection IO port;
the 2 nd pin of the double diode D19 is connected with the G pole of the MOS tube Q10;
the 3 rd pin of the double diode D19 is connected with the KEY KEY1.
6. The circuit of claim 4, wherein the MOS transistor control circuit comprises a double diode D18 connected to the MOS transistor Q10, a POWER _ EN output and a USB _ IN _5V output respectively connected to the double diode D18, and a resistor R86 connected IN series to an output of the double diode D18;
the POWER _ EN output end is connected with the USB _ IN _5V output end IN parallel;
the output end of the resistor R86 is connected with the B pole end of the triode Q12.
7. The ultra-low POWER consumption circuit as claimed IN claim 6, wherein the POWER _ EN output and the USB _ IN _5V output are connected IN parallel to pins 1 and 2 of the dual diode D18; the 3 rd pin of the double diode D18 is connected in series with a resistor R86.
8. The circuit of claim 1, wherein the power selection circuit comprises a double diode D20 connected to the MOS transistor Q10, a transistor Q11 connected to the double diode D20 in series with the USB input terminal, and connected to the double diode D20 in parallel;
the triode Q11 is connected with a battery BAT + end;
the S pole terminal of the MOS tube Q10 is connected with a double diode D20 in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223008364.3U CN218825335U (en) | 2022-11-11 | 2022-11-11 | Circuit with ultra-low power consumption |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223008364.3U CN218825335U (en) | 2022-11-11 | 2022-11-11 | Circuit with ultra-low power consumption |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218825335U true CN218825335U (en) | 2023-04-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223008364.3U Active CN218825335U (en) | 2022-11-11 | 2022-11-11 | Circuit with ultra-low power consumption |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218825335U (en) |
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2022
- 2022-11-11 CN CN202223008364.3U patent/CN218825335U/en active Active
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