CN218772122U - Distributed internet of things gateway - Google Patents

Abstract

The application relates to a distributed internet of things gateway, comprising: casing, host computer module, first network interface, second network interface and a plurality of GPI interface, GPO interface, first serial port communication interface, second serial port communication interface and relay interface, host computer module includes: power supply circuit, CPU, and connect CPU's first GMAC pin and first PHY circuit of first network interface, connect CPU's second GMAC pin and second network interface's second PHY circuit, connect CPU's first GPIO pin and GPI interface's GPI circuit, connect CPU's second GPIO pin and GPO interface's GPO circuit, connect CPU's third GPIO pin and relay interface's relay circuit, connect CPU's SPI pin and first serial ports communication interface's SPI to serial ports circuit, connect CPU's UART pin and second serial ports communication interface's serial ports communication circuit, connect CPU's RTC circuit of RTC pin, wherein, second network interface connects power supply circuit. By the method and the device, more port expansion can be realized at low cost, and the cost is reduced.

Description

Distributed internet of things gateway

Technical Field

The utility model relates to a network communication technical field, more specifically say, relate to distributed thing networking gateway.

Background

The internet of things gateway is a device for connecting internet of things equipment, an equipment system, a sensor and cloud. By connecting the field devices to the centralized cloud, the internet of things gateway provides a local processing and storage solution and is able to autonomously control the field devices based on data input by the sensors. An internet of things gateway (which may be a hardware or virtual device) receives data from the internet of things sensors, which may then be sent to the cloud. The internet of things gateway also receives information from the cloud, which then enters the device itself. This means that all information transferred from the internet of things device to the cloud passes through the connected internet of things gateway. In the current setting and use of the gateway, the gateway is limited in performance and device performance, a complex application scene is generated in many times, the number of connection interfaces is not enough, the application scene coverage is realized by adding equipment and performing complex equipment networking design, and the whole application cost is greatly increased.

SUMMERY OF THE UTILITY MODEL

The technical problem to be solved by the utility model is to provide a distributed internet of things gateway,

the utility model provides a technical scheme that its technical problem adopted is: constructing a distributed internet of things gateway, comprising: a shell, a host module arranged in the shell, a first network interface, a second network interface, a plurality of GPI interfaces, a plurality of GPO interfaces, a plurality of first serial port communication interfaces, a plurality of second serial port communication interfaces and a plurality of relay interfaces which are arranged on the shell and connected with the host module,

the host module includes: the system comprises a power supply circuit, a CPU, a first PHY circuit, a second PHY circuit, a GPIO circuit, a GPO circuit, a relay circuit, an SPI (serial peripheral interface) to serial port conversion circuit, a UART (universal asynchronous receiver/transmitter) circuit, and an RTC circuit, wherein the first PHY circuit is connected with a first GMAC (general purpose input/output) pin of the CPU, the second PHY circuit is connected with a second GMAC pin of the CPU, the first PHY circuit is connected with a first GPIO pin of the CPU, the GPIO circuit is connected with a GPIO interface, the second GPIO pin of the CPU and the GPO interface, the third GPIO pin of the CPU and the relay circuit is connected with the relay interface, the SPI pin of the CPU is connected with the SPI of the first serial port communication interface, the UART pin of the CPU is connected with the serial port communication circuit of the second serial port communication interface, the RTC circuit is connected with the RTC pin of the CPU, and the second PHY circuit is connected with the first network interface.

Preferably, in the distributed internet of things gateway described in the present application, the SPI-to-serial port circuit includes an SPI interface UART chip U5 and a plurality of first UART communication circuits;

SPI interface UART chip U5's SPI end is connected the SPI pin of CPU, SPI interface UART chip U5's UART pin corresponds respectively and connects first UART communication circuit's first end, each first UART communication circuit's second end is connected one first serial port communication interface.

Preferably, in the distributed internet of things gateway described in the present application, each of the first UART communication circuits includes a first serial port switching chip, a first RS232 communication unit, a first RS485 communication unit, and a first relay switch, respectively;

the utility model discloses a relay switch, including SPI interface UART chip U5, first RS232 communication unit, first relay switch, first RS485 communication unit, first relay switch, second relay switch, first serial port switch chip's common port is connected SPI interface UART chip U5's UART pin, first RS232 communication unit's first signal end is connected first RS232 communication unit's first end, first RS485 communication unit's second end is connected first relay switch's second switch end, first relay switch's common port is connected first serial port communication interface, first relay switch's control end is connected CPU's UART control pin.

Preferably, in the distributed internet of things gateway described in the present application, the serial port communication circuit includes a plurality of second UART communication circuits, and each second UART communication circuit includes a second serial port switching chip, a second RS232 communication unit, a second RS485 communication unit, and a second relay switch, respectively;

the utility model discloses a serial ports switch device, including CPU, serial ports switch chip, second RS485 communication unit, second RS232 communication unit, second relay switch's first end, the common port of second serial ports switch chip is connected CPU's UART pin, the first signal end of second serial ports switch chip is connected the first end of second RS232 communication unit, the second signal end of second serial ports switch chip is connected the first end of second RS485 communication unit, the second end of second RS485 communication unit is connected the second switching end of second relay switch, the common port of second relay switch is connected the second serial ports communication interface, the control end of second relay switch is connected CPU's UART control pin.

Preferably, in the distributed internet of things gateway described in the present application, two of the first RS232 communication unit and the second RS232 communication unit are integrated into one RS232 communication chip.

Preferably, in the distributed internet of things gateway described in the present application, the GPI circuit includes a plurality of GPI subunits, and each GPI subunit includes a first optical coupler, a first resistor, a second resistor, a third resistor, a fourth resistor, a first fuse, a first diode, a second diode, and a first capacitor;

a first end of the first optical coupler is connected with a first end of the first resistor and a first end of the second resistor, the first end of the first resistor is connected with a GPIO pin of the CPU, the first end of the second resistor is connected with a power supply voltage, a third end of the first optical coupler is connected with a first end of the third resistor and a first end of the first capacitor, a second end of the first optical coupler, a fourth end of the first optical coupler, a second end of the first capacitor, a first end of the fourth resistor and an anode of the first diode are all grounded, and a second end of the third resistor, a second end of the fourth resistor and a cathode of the first diode are connected with a signal end of the GPI interface;

and a power supply end of the GPI interface is connected with a first end of the first fuse and a cathode of the second diode, an anode of the second diode is grounded, and a second end of the first fuse is connected with the power supply circuit.

Preferably, in the distributed internet of things gateway described in the present application, the GPO circuit includes a plurality of GPO subunits, and each GPO subunit includes a first triode, a sixth resistor, a seventh resistor, an eighth resistor, a second fuse, a third diode, and a fourth diode;

the first end of the sixth resistor is connected to a GPIO pin of the CPU, the second end of the sixth resistor is connected to the first end of the seventh resistor and the base of the first triode, the collector of the first triode is connected to the first end of the eighth resistor, the cathode of the third diode and the signal end of the GPI interface, the second end of the eighth resistor and the first end of the second fuse are connected to the power supply circuit, the second end of the second fuse and the cathode of the fourth diode are connected to the power supply terminal of the GPI interface, and the second end of the seventh resistor, the emitter of the first triode, the anode of the third diode and the anode of the fourth diode are all grounded.

Preferably, in the distributed internet of things gateway described in the present application, the first PHY circuit includes a first network chip with a model number of RTL8211F, the first network interface includes an RJ45 connector J2, and a signal pin of the connector J2 is connected to a signal pin of the first network chip;

the second PHY circuit comprises a second network chip of which the model is RTL8211F, the second network interface comprises an RJ45 connector J3 with POE, a signal pin of the connector J3 is connected with a signal pin of the second network chip, and a power supply pin of the connector J3 is connected with the power supply circuit.

Preferably, in the distributed internet of things gateway described in the present application, the RTC circuit includes an RTC chip with a model number of HYM 8563.

Preferably, in the distributed internet of things gateway described in the present application, the distributed internet of things gateway further includes a wireless communication circuit connected to the CPU.

Implement the utility model discloses a distributed thing networking gateway has following beneficial effect: and more port expansion is realized at low cost, and the application cost is reduced.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

fig. 1 is a logic block diagram of an embodiment of a distributed internet of things gateway of the present invention;

FIG. 2 is a schematic diagram of a portion of one embodiment of the SPI to serial circuit of FIG. 1;

FIG. 3 is a schematic diagram of a portion of another embodiment of the SPI/serial interface circuit of FIG. 1;

FIG. 4 is a schematic diagram of a portion of another embodiment of the SPI interface circuit of FIG. 1;

FIG. 5 is a schematic diagram of a portion of another embodiment of the SPI to serial circuit of FIG. 1;

FIG. 6 is a partial circuit schematic of one embodiment of the GPI circuit of FIG. 1;

FIG. 7 is a partial circuit schematic diagram of one embodiment of the GPO circuit of FIG. 1;

FIG. 8 is a schematic diagram of a partial circuit of one embodiment of the GPI interface and GPO interface of FIG. 1;

FIG. 9 is a partial circuit schematic of one embodiment of the second PHY circuit of FIG. 1;

FIG. 10 is a partial circuit schematic of one embodiment of the first network interface and the second network interface of FIG. 1;

FIG. 11 is a partial circuit schematic of the power supply circuit of FIG. 1;

FIG. 12 is a schematic diagram of a portion of the RTC circuit of FIG. 1;

FIG. 13 is a partial circuit schematic of the repeater circuit of FIG. 1;

fig. 14 is a schematic diagram of a local circuit according to another embodiment of the present invention.

Detailed Description

In order to clearly understand the technical features, objects, and effects of the present invention, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in fig. 1, in the first embodiment of the utility model, a distributed internet of things gateway includes: the casing and set up in the inside host computer module of casing to and set up on the casing and connect host computer module's first network interface 210, second network interface 220, a plurality of GPI interface 230, a plurality of GPO interface 240, a plurality of first serial ports communication interface 260, a plurality of second serial ports communication interface 250 and a plurality of relay interface 270, host computer module includes: the power supply circuit 130, the CPU110, a first PHY circuit 310 connecting a first GMAC pin of the CPU110 and the first network interface 210, a second PHY circuit 320 connecting a second GMAC pin of the CPU110 and the second network interface 220, a GPI circuit 330 connecting a first GPIO pin of the CPU110 and the GPI interface 230, a GPO circuit 340 connecting a second GPIO pin of the CPU110 and the GPO interface 240, a relay circuit 370 connecting a third GPIO pin of the CPU110 and the relay interface 270, an SPI-to-serial circuit 360 connecting an SPI pin of the CPU110 and the first serial communication interface 260, a serial communication circuit 350 connecting a UART pin of the CPU110 and the second serial communication interface 250, and an RTC circuit 120 connecting an RTC pin of the CPU110, wherein the second network interface 220 is connected with the power supply circuit 130. Specifically, in the gateway device, a plurality of interfaces are disposed on the housing, and network connection can be achieved through the interfaces, where in the network interfaces, the first network interface 210 may be a common signal network interface, and the second network interface 220 may be a network interface capable of providing power, that is, the second network interface 220 may be connected to the power supply circuit 130 on the host module. A plurality of serial port communication interfaces are arranged to be connected with an external circuit, and serial port communication with external equipment is achieved. The serial communication data may implement UART data communication with the CPU110 through the serial communication circuit 350 and the UART pin of the CPU 110. In addition, in order to realize the maximization of serial port quantity, the SPI signal of CPU110 is converted through SPI to serial port circuit 360, and the realization is carried out data communication with external equipment in serial port data communication format through the serial port. In an embodiment, 6 sets of serial communication interfaces can be implemented through the UART interface of the CPU110, 4 sets of serial communication interfaces can be implemented through the SPI interface of the CPU110, and finally 10 sets of serial communication interfaces can be implemented without adding additional CPU110 resources. In addition, the GPIO interface of the CPU110 may be correspondingly connected to the GPI interface 230 and the GPO interface 240 through the GPI circuit 330 and the GPO circuit 340, respectively, so that the device performs data transmission with the external device through the GPI interface 230 and the GPO interface 240. In one embodiment, four sets of GPI interfaces 230 and GPO interfaces 240 can be implemented using CPU110 resources. In the host module, the GPIO interface of the CPU110 is also connected to the relay interface 270 through the relay circuit 370, so as to implement analog data transmission, for example, direct-current voltage transmission in the range of 30V DC2A or alternating-current voltage transmission in the range of 125VAC 1A. In one embodiment, the CPU may be of the type Core-3568J.

As shown in fig. 2, fig. 3, fig. 4 and fig. 5, the SPI-to-serial circuit 360 includes an SPI interface UART chip U5 and a plurality of first UART communication circuits; the SPI end of the SPI interface UART chip U5 is connected to the SPI pin of the CPU110, the UART pin of the SPI interface UART chip U5 is correspondingly connected to the first end of the first UART communication circuit, respectively, and the second end of each first UART communication circuit is connected to a first serial port communication interface 260. Specifically, the SPI pin of the CPU110 may communicate with the UART communication circuit through the SPI to UART chip of the model WK 2124.

Optionally, each first UART communication circuit includes a first serial port switching chip, a first RS232 communication unit, a first RS485 communication unit, and a first relay switch, respectively; the common end of the first serial port switching chip is connected with a UART pin of an SPI interface UART chip U5, the first signal end of the first serial port switching chip is connected with the first end of a first RS232 communication unit, the second signal end of the first serial port switching chip is connected with the first end of a first RS485 communication unit, the second end of the first RS232 communication unit is connected with the first switching end of a first relay switch, the second end of the first RS485 communication unit is connected with the second switching end of the first relay switch, the common end of the first relay switch is connected with a first serial port communication interface 260, and the control end of the first relay switch is connected with a UART control pin of a CPU 110. Specifically, among the UART communication circuit, switch the 232 signal and 485 signals that receive through serial ports switching chip, wherein the 232 signal transmits through RS232 communication unit, and the 485 signal transmits through RS485 communication unit, and the 232 signal can realize through relay switch's switching with serial ports communication interface communication with the 485 signal simultaneously. Taking one of the paths as an example, the third pin of the serial port switching chip U9 is used to receive 232 signals, the first pin of U9 is used to receive 485 signals, the common pin of U9 is used to connect the UART receiving pin of the UART chip U5, and the UART transmitting pin of the UART chip U9 is connected to the RS232 communication unit and the RS485 communication unit through a resistor respectively. The relay switch is controlled by the control level output by the CPU110, and the switching of the output 232 signal and the output 485 signal is realized. The serial port switching chip is TS5A3159.

Optionally, the serial port communication circuit 350 includes a plurality of second UART communication circuits, and each second UART communication circuit includes a second serial port switching chip, a second RS232 communication unit, a second RS485 communication unit, and a second relay switch; the common end of the second serial port switching chip is connected with the UART pin of the CPU110, the first signal end of the second serial port switching chip is connected with the first end of the second RS232 communication unit, the second signal end of the second serial port switching chip is connected with the first end of the second RS485 communication unit, the second end of the second RS232 communication unit is connected with the first switching end of the second relay switch, the second end of the second RS485 communication unit is connected with the second switching end of the second relay switch, the common end of the second relay switch is connected with the second serial port communication interface 250, and the control end of the second relay switch is connected with the UART control pin of the CPU 110. Specifically, in the second UART communication circuit, the same circuit structure of the first UART communication circuit can be adopted, the switching of the input 232 signal and the input 485 signal is realized through the serial port switching chip, wherein the 232 signal is transmitted through the RS232 communication unit, the 485 signal is transmitted through the RS485 communication unit, and the 232 signal and the 485 signal can be communicated with the serial port communication interface through the switching of the relay switch. Taking one of the paths as an example, the third pin of the serial port switching chip U6 is used to receive 232 signals, the first pin of the U6 is used to receive 485 signals, the common pin of the U6 is used to connect the UART receiving pin of the CPU110, and simultaneously, the UART transmitting pin of the CPU110 is connected to the RS232 communication unit and the RS485 communication unit through a resistor respectively.

Optionally, two of the first RS232 communication unit and the second RS232 communication unit are integrated into one RS232 communication chip. Specifically, the RS232 communication unit may adopt a dual-channel integrated chip, and the first RS232 communication unit and the RS232 communication unit may be combined in pairs to realize 232 signal communication through a dual-channel RS232 communication chip. In a specific embodiment, two-way RS232 communication is realized through the RS232 communication chip U16 and its peripheral circuits. In one embodiment, RS485 communication can be achieved through the RS485 chip U24 and its peripheral circuits.

Optionally, as shown in fig. 6 and fig. 8, the GPI circuit 330 includes a plurality of GPI subunits, each GPI subunit including a first optocoupler, a first resistor, a second resistor, a third resistor, a fourth resistor, a first fuse, a first diode, a second diode, and a first capacitor; the first end of the first optical coupler is connected with the first end of the first resistor and the first end of the second resistor, the first end of the first resistor is connected with a GPIO pin of the CPU110, the first end of the second resistor is connected with a power supply voltage, the third end of the first optical coupler is connected with the first end of the third resistor and the first end of the first capacitor, the second end of the first optical coupler, the fourth end of the first optical coupler, the second end of the first capacitor, the first end of the fourth resistor and the anode of the first diode are all grounded, and the second end of the third resistor, the second end of the fourth resistor and the cathode of the first diode are connected with the signal end of a GPI interface 230; the power source terminal of the GPI interface 230 is connected to the first terminal of the first fuse and the cathode of the second diode, the anode of the second diode is grounded, and the second terminal of the first fuse is connected to the power supply circuit. Specifically, in GPI circuit 330, a plurality of GPI subunits are used to implement a one-to-one correspondence connection with GPI interface 230. In each GPI subunit, when an external GPI signal is input to a high level, the optical coupler is switched on. Causing the internal signal CPU _ GPI to be pulled low. Otherwise, GPI inputs the low level, CPU _ GPI is connected to VCC3V3_ SYS high level; this serves as a control for the high and low levels received by the CPU _ GPI.

Optionally, as shown in fig. 7 and 8, the GPO circuit 340 includes a plurality of GPO subunits, each GPO subunit including a first transistor, a sixth resistor, a seventh resistor, an eighth resistor, a second fuse, a third diode, and a fourth diode; the first end of the sixth resistor is connected with a GPIO pin of the CPU110, the second end of the sixth resistor is connected with the first end of the seventh resistor and the base electrode of the first triode, the collector electrode of the first triode is connected with the first end of the eighth resistor, the cathode of the third diode and the signal end of the GPI interface 230, the second end of the eighth resistor and the first end of the second fuse are connected with the power supply circuit, the second end of the second fuse and the cathode of the fourth diode are connected with the power supply end of the GPI interface 230, and the second end of the seventh resistor, the emitter electrode of the first triode, the anode of the third diode and the anode of the fourth diode are all grounded. Specifically, in the GP0 circuit, the one-to-one connection to the GPO interface 240 is realized by a plurality of GPO subunits. In each GPO subunit, when an internal signal CPU _ GPO is at a high level, the output signal GPO is conducted to the ground by a triode and is at a low level; conversely, when the CPU _ GPO is low, the output signal GPO is connected to +12V and is high. Thereby controlling the high and low states of the output signal GPO.

Alternatively, as shown in fig. 9, 10 and 11, the first PHY circuit 310 includes a first network chip with model number RTL8211F, the first network interface 210 includes an RJ45 connector J2, and signal pins of the connector J2 are connected to signal pins of the first network chip; the second PHY circuit 320 includes a second network chip with a model number RTL8211F, the second network interface 220 includes an RJ45 connector J3 with POE, a signal pin of the connector J3 is connected to a signal pin of the second network chip, and a power pin of the connector J3 is connected to the power supply circuit 130. Specifically, the first PHY circuit 310 and the second PHY circuit 320 may both be composed of a network chip with a model number of RTL8211F and peripheral circuits thereof, so as to implement transmission of network signals. And the RJ45 connector J2 connected with the first network chip is a common connector, and the RJ45 connector J3 connected with the second network chip is a connector capable of supplying power to POE. The connector J3 may be connected to the power supply terminal of the power supply circuit 130 through a connector M2, and in the power supply circuit 130, an external power supply may be connected through a connector J1, and power conversion may be performed through the power conversion chip U3 and the power conversion chip U4 to supply power to the internal circuit.

Optionally, as shown in fig. 12, the RTC circuit 120 includes an RTC chip with model number HYM 8563. Specifically, in the RTC circuit 120, the RTC chip U18 is used to implement that the clock signal RTC circuit of the CPU110 provides system time for the device, where the RTC circuit 120 may be connected to a battery, and the battery is used to continuously supply power to the chip after the device is powered off, so as to ensure that the system time continues to operate.

In one embodiment, the relay circuit is controlled in its operating state by the CPU as shown in fig. 13.

Optionally, as shown in fig. 14, the distributed internet of things gateway of the present application further includes a wireless communication circuit connected to the CPU 110. Specifically, the gateway device may communicate with the external device through a wireless communication circuit, where the wireless communication circuit may include a WIFI communication circuit and a bluetooth communication circuit. In an embodiment, the WIFI communication circuit and the bluetooth communication circuit may be collected as chips for implementation. Such as WIF communication and bluetooth communication using the signal AP6275S and its peripheral circuit devices.

In the distributed internet of things gateway of the application, the distributed internet of things gateway can further comprise a display circuit connected with the SPI of the CPU110, and the display circuit displays the working state, working parameters and the like of the gateway through a display screen.

In the distributed internet of things gateway, a USB interface and a USB circuit connected with the USB interface are further arranged. I.e. data transmission via the USB interface.

It is to be understood that the foregoing examples merely represent preferred embodiments of the present invention, and that the description thereof is more specific and detailed, but not intended to limit the scope of the invention; it should be noted that, for those skilled in the art, the above technical features can be freely combined, and several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention; therefore, all changes and modifications that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims (10)

1. A distributed Internet of things gateway, comprising: a shell, a host module arranged in the shell, a first network interface, a second network interface, a plurality of GPI interfaces, a plurality of GPO interfaces, a plurality of first serial port communication interfaces, a plurality of second serial port communication interfaces and a plurality of relay interfaces which are arranged on the shell and connected with the host module,

the host module includes: the system comprises a power supply circuit, a CPU, a first PHY circuit, a second PHY circuit, a GPIO circuit, a GPO circuit, a relay circuit, an SPI (serial peripheral interface) to serial port conversion circuit, a UART (universal asynchronous receiver/transmitter) circuit, and an RTC circuit, wherein the first PHY circuit is connected with a first GMAC (general purpose input/output) pin of the CPU, the second PHY circuit is connected with a second GMAC pin of the CPU, the first PHY circuit is connected with a first GPIO pin of the CPU, the GPIO circuit is connected with a GPIO interface, the second GPIO pin of the CPU and the GPO interface, the third GPIO pin of the CPU and the relay circuit is connected with the relay interface, the SPI pin of the CPU is connected with the SPI of the first serial port communication interface, the UART pin of the CPU is connected with the serial port communication circuit of the second serial port communication interface, the RTC circuit is connected with the RTC pin of the CPU, and the second PHY circuit is connected with the first network interface.

2. The distributed internet of things gateway of claim 1, wherein the SPI-to-serial circuit comprises an SPI interface UART chip U5 and a plurality of first UART communication circuits;

SPI interface UART chip U5's SPI end is connected the SPI pin of CPU, SPI interface UART chip U5's UART pin corresponds respectively and connects first UART communication circuit's first end, each first UART communication circuit's second end is connected one first serial port communication interface.

3. The distributed internet of things gateway of claim 2, wherein each first UART communication circuit comprises a first serial port switching chip, a first RS232 communication unit, a first RS485 communication unit, and a first relay switch, respectively;

the utility model discloses a relay switch, including SPI interface UART chip U5, first RS232 communication unit, first relay switch, first RS485 communication unit, first relay switch, second relay switch, first serial port switch chip's common port is connected SPI interface UART chip U5's UART pin, first RS232 communication unit's first signal end is connected first RS232 communication unit's first end, first RS485 communication unit's second end is connected first relay switch's second switch end, first relay switch's common port is connected first serial port communication interface, first relay switch's control end is connected CPU's UART control pin.

4. The distributed internet of things gateway of claim 3, wherein the serial port communication circuit comprises a plurality of second UART communication circuits, and each second UART communication circuit comprises a second serial port switching chip, a second RS232 communication unit, a second RS485 communication unit and a second relay switch;

the utility model discloses a serial ports switch device, including CPU, serial ports switch chip, second RS485 communication unit, second RS232 communication unit, second relay switch's first end, the common port of second serial ports switch chip is connected CPU's UART pin, the first signal end of second serial ports switch chip is connected the first end of second RS232 communication unit, the second signal end of second serial ports switch chip is connected the first end of second RS485 communication unit, the second end of second RS485 communication unit is connected the second switching end of second relay switch, the common port of second relay switch is connected the second serial ports communication interface, the control end of second relay switch is connected CPU's UART control pin.

5. The distributed internet of things gateway of claim 4, wherein each two of the first RS232 communication unit and the second RS232 communication unit are integrated on an RS232 communication chip.

6. The distributed internet of things gateway of claim 1, wherein the GPI circuit comprises a plurality of GPI subunits, each GPI subunit comprising a first optocoupler, a first resistor, a second resistor, a third resistor, a fourth resistor, a first fuse, a first diode, a second diode, and a first capacitor;

the first end of the first optical coupler is connected with the first end of the first resistor and the first end of the second resistor, the first end of the first resistor is connected with a GPIO pin of the CPU, the first end of the second resistor is connected with a power supply voltage, the third end of the first optical coupler is connected with the first end of the third resistor and the first end of the first capacitor, the second end of the first optical coupler, the fourth end of the first optical coupler, the second end of the first capacitor, the first end of the fourth resistor and the anode of the first diode are all grounded, and the second end of the third resistor, the second end of the fourth resistor and the cathode of the first diode are connected with a signal end of a GPI interface;

and a power supply end of the GPI interface is connected with a first end of the first fuse and a cathode of the second diode, an anode of the second diode is grounded, and a second end of the first fuse is connected with the power supply circuit.

7. The distributed internet of things gateway of claim 1, wherein the GPO circuit comprises a plurality of GPO subunits, each GPO subunit comprising a first triode, a sixth resistor, a seventh resistor, an eighth resistor, a second fuse, a third diode, and a fourth diode;

the first end of the sixth resistor is connected to a GPIO pin of the CPU, the second end of the sixth resistor is connected to the first end of the seventh resistor and the base of the first triode, the collector of the first triode is connected to the first end of the eighth resistor, the cathode of the third diode and the signal end of the GPI interface, the second end of the eighth resistor and the first end of the second fuse are connected to the power supply circuit, the second end of the second fuse and the cathode of the fourth diode are connected to the power supply terminal of the GPI interface, and the second end of the seventh resistor, the emitter of the first triode, the anode of the third diode and the anode of the fourth diode are all grounded.

8. The distributed IOT gateway of claim 1,

the first PHY circuit comprises a first network chip with the model of RTL8211F, the first network interface comprises an RJ45 connector J2, and a signal pin of the connector J2 is connected with a signal pin of the first network chip;

the second PHY circuit comprises a second network chip of which the model is RTL8211F, the second network interface comprises an RJ45 connector J3 with POE, a signal pin of the connector J3 is connected with a signal pin of the second network chip, and a power supply pin of the connector J3 is connected with the power supply circuit.

9. The distributed internet of things gateway of claim 1, wherein the RTC circuit comprises an RTC chip model number HYM 8563.

10. The distributed internet of things gateway of claim 1, further comprising wireless communication circuitry connected to the CPU.

Images