CN218771809U

CN218771809U - Three-phase improved hybrid cascade multilevel inverter topological structure

Info

Publication number: CN218771809U
Application number: CN202223147904.6U
Authority: CN
Inventors: 颜景斌; 王玺哲; 许森洋
Original assignee: Harbin University of Science and Technology
Current assignee: Harbin University of Science and Technology
Priority date: 2022-11-27
Filing date: 2022-11-27
Publication date: 2023-03-28
Anticipated expiration: 2032-11-27

Abstract

The utility model provides a three-phase improved generation mixes cascades multilevel inverter topological structure, this topological structure includes that the three-phase cascades H bridge inverter (Q) and a traditional three-bridge arm inverter (E), direct current voltage source V1, V2, V3, V4, load R1, R2, R3, compare many the output voltage that the improved generation mixes and cascades multilevel inverter with traditional three-phase rectifier and produce harmonic wave form less, output voltage is more close pure sinusoidal wave form, it is lower to produce reactive power, power loss is littleer, reduce the voltage stress between the switch, be applicable to low switching frequency, more be suitable for the application of high power, can produce the voltage of more levels, improve power handling capacity under the condition that does not increase single equipment rated value, application prospect is very extensive.

Description

Three-phase improved hybrid cascade multilevel inverter topological structure

Technical Field

The utility model relates to a power electronics field, concretely relates to three-phase improved generation mixes and cascades multilevel inverter topological structure.

Background

In recent years, power semiconductor devices and control technologies have been developed rapidly and widely applied in the field of power electronics, and various power electronic devices have come into operation with continuous innovation of the technologies. Inverters are such power converters that produce ac power from dc power, including Voltage Source Inverters (VSI) and Current Source Inverters (CSI), and the output produced will be a constant voltage and frequency. With the development of the inverter technology, great progress has been made in some key technical fields, but the traditional inverter circuit has many disadvantages.

In the case of VSI, the output voltage depends on the source voltage, while in CSI, the load current depends on the source current. For an under-damped load, the VSI is a load swap and uses a feedback diode to provide reactive power back to the load consumption. The IGBT switch is adopted, and is suitable for high-power application.

Conventional square wave and half square wave inverters are marked as unusable for high power applications due to their high total harmonic distortion and losses. Three single-phase half (or full) bridges can be connected in parallel to form a three-phase inverter, and can be applied under the condition of high power. Today's multi-level inverters have had a greater impact in the power industry, with the multi-level inverter output voltage being closer to a pure sinusoidal waveform, which has less total harmonic distortion, and thus less power loss. The cascaded H-bridge type (CHB) inverter is formed by cascading units of a full-bridge structure, a converter does not contain a diode and a suspension capacitor, and the number of cascaded modules can be determined according to power and voltage levels. Because the cascade H-bridge topology structure needs the least power devices, the control method is simple, the redundancy design is easy to realize, and the cascade H-bridge topology structure is suitable for multi-level occasions.

With the rapid development of inverter technology, the conventional inverter topology can not meet the requirements. Therefore, the development of an inverter suitable for a low switching frequency has been in the trend, in which the generated energy is low, the power loss is small, and the voltage stress between the switches is reduced.

SUMMERY OF THE UTILITY MODEL

To the not enough among the above-mentioned prior art, the utility model provides a three-phase improved generation mixes and cascades multilevel inverter topological structure. The output voltage of the circuit can generate less harmonic wave forms, the output voltage is closer to a pure sine wave form, the generated reactive power is lower, the power loss is smaller, the voltage stress between switches is reduced, and the circuit is suitable for low switching frequency and is more suitable for high-power application. The embodiment of the utility model adopts the following technical scheme, specifically as follows.

The utility model provides a many level inverter topological structure of three-phase improved generation mixed cascade, its characterized in that: the three-phase cascade H-bridge inverter comprises a three-phase cascade H-bridge inverter (Q), a three-bridge arm inverter (E), 18 IGBTs in total, direct-current voltage sources V1, V2, V3 and V4 and loads R1, R2 and R3. The three-phase cascade H-bridge inverter (Q) consists of 12 IGBTs and comprises a seventh IGBT (S7), an eighth IGBT (S8), a ninth IGBT (S9), a tenth IGBT (S10), an eleventh IGBT (S11), a twelfth IGBT (S12), a thirteenth IGBT (S13), a fourteenth IGBT (S14), a fifteenth IGBT (S15), a sixteenth IGBT (S16), a seventeenth IGBT (S17) and an eighteenth IGBT (S18); the emitter of the seventh IGBT (S7) is connected with the collector of the eighth IGBT (S8) to form a bridge arm; the emitter of the ninth IGBT (S9) is connected with the collector of the tenth IGBT (S10) to form another bridge arm; one end of the direct-current voltage source V2 is respectively connected with the collector electrodes of the seventh IGBT (S7) and the ninth IGBT (S9); the other end of the direct-current voltage source V2 is respectively connected with emitting electrodes of an eighth IGBT (S8) and a tenth IGBT (S10) to form a first phase of the three-phase cascade H-bridge inverter (Q); the emitter of the eleventh IGBT (S11) is connected with the collector of the twelfth IGBT (S12) to form a bridge arm; the emitter of the thirteenth IGBT (S13) is connected with the collector of the fourteenth IGBT (S14) to form the other bridge arm; one end of the direct-current voltage source V3 is respectively connected with the collectors of the eleventh IGBT (S11) and the thirteenth IGBT (S13); the other end of the direct-current voltage source V3 is respectively connected with emitting electrodes of a twelfth IGBT (S12) and a fourteenth IGBT (S14) to form a second phase of the three-phase cascade H-bridge inverter (Q); the emitter of the fifteenth IGBT (S15) is connected with the collector of the sixteenth IGBT (S16) to form a bridge arm; the emitter of the seventeenth IGBT (S17) is connected with the collector of the eighteenth IGBT (S18) to form another bridge arm; one end of the direct-current voltage source V4 is respectively connected with the collectors of the fifteenth IGBT (S15) and the seventeenth IGBT (S17); the other end of the direct-current voltage source V3 is respectively connected with the emitting electrodes of the sixteenth IGBT (S16) and the eighteenth IGBT (S18) to form a third phase of the three-phase cascade H-bridge inverter (Q).

The three-phase improved hybrid cascade multilevel inverter topology structure is characterized in that the three-bridge arm inverter (E) consists of 6 IGBTs and comprises a first IGBT (S1), a second IGBT (S2), a third IGBT (S3), a fourth IGBT (S4), a fifth IGBT (S5) and a sixth IGBT (S6); the connection mode is that the emitter of the first IGBT (S1) is connected with the collector of the second IGBT (S2) to form a first bridge arm; the emitter of the third IGBT (S3) is connected with the collector of the fourth IGBT (S4) to form a second bridge arm; the emitter of the fifth IGBT (S5) is connected with the collector of the sixth IGBT (S6) to form a third bridge arm; one end of the direct-current voltage source V1 is respectively connected with the collector electrodes of the first IGBT (S1), the third IGBT (S3) and the fifth IGBT (S5); the other end of the direct-current voltage source V1 is respectively connected with the emitting electrodes of the second IGBT (S2), the fourth IGBT (S4) and the sixth IGBT (S6).

The three-phase improved hybrid cascade multilevel inverter topology structure is characterized in that a first bridge arm of a three-bridge arm inverter (E), a ninth IGBT (S9) and a tenth IGBT (S10) form bridge arm cascade; the second bridge arm is cascaded with a bridge arm formed by a thirteenth IGBT (S13) and a fourteenth IGBT (S14); the third bridge arm is cascaded with a bridge arm consisting of a seventeenth IGBT (S17) and an eighteenth IGBT (S18).

According to the three-phase improved hybrid cascade multilevel inverter topology structure, one end of a load R1 is connected between an emitter of a seventh IGBT (S7) and a collector of an eighth IGBT (S8); one end of the load R2 is connected between an emitter of the eleventh IGBT (S11) and a collector of the twelfth IGBT (S12); one end of the load R3 is connected between the emitter of the fifteenth IGBT (S15) and the collector of the sixteenth IGBT (S16); the other ends of the three loads are connected in parallel and then grounded.

Preferably, the three-phase improved hybrid cascaded multi-level inverter topology is characterized in that an independent isolation direct-current power supply is adopted to realize a three-phase cascaded H-bridge inverter (Q), the three-phase cascaded H-bridge inverter can generate output voltage close to sine, the size and weight problems of the traditional multi-pulse inverter are solved, and the three-phase improved hybrid cascaded multi-level inverter topology can be used for high-voltage and high-power applications.

Preferably, the three-phase improved hybrid cascade multilevel inverter topology is characterized by comprising a three-leg inverter (E) and a three-phase cascade H-bridge inverter (Q), and the model can generate a five-level phase voltage waveform.

The utility model discloses there is following beneficial effect: after the technical scheme is adopted, the output voltage generates less harmonic wave forms, the output voltage is closer to a pure sine wave form, the generated reactive power is lower, the power loss is smaller, the voltage stress between the switches is reduced, and the device is suitable for low switching frequency and is more suitable for high-power application. More levels of voltage can be generated, the power processing capacity is improved under the condition of not increasing the rated value of a single device, and the method has great theoretical and practical significance.

Drawings

For a clear explanation of the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a topology structure diagram of a three-phase improved hybrid cascaded multi-level inverter.

Fig. 2 is a first phase equivalent diagram of a three-phase improved hybrid cascaded multi-level inverter topology.

Fig. 3 is a table of switching states for a first phase of a three-phase improved hybrid cascaded multi-level inverter topology.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it should be noted that the embodiments described herein are only some embodiments of the present invention, not all implementation manners of the present invention, and the embodiments are only exemplary.

The utility model provides a many level inverter topological structure of three-phase improved generation mixed cascade, its characterized in that: the three-phase cascade H-bridge inverter comprises a three-phase cascade H-bridge inverter (Q) and a three-bridge arm inverter (E), wherein the total number of the three-bridge arm inverter is 18 IGBTs, direct-current voltage sources V1, V2, V3 and V4 and loads R1, R2 and R3; the three-phase improved hybrid cascaded multi-level inverter topology structure is characterized in that the three-phase cascaded H-bridge inverter (Q) consists of 12 IGBTs, and comprises a seventh IGBT (S7), an eighth IGBT (S8), a ninth IGBT (S9), a tenth IGBT (S10), an eleventh IGBT (S11), a twelfth IGBT (S12), a thirteenth IGBT (S13), a fourteenth IGBT (S14), a fifteenth IGBT (S15), a sixteenth IGBT (S16), a seventeenth IGBT (S17) and an eighteenth IGBT (S18); the emitter of the seventh IGBT (S7) is connected with the collector of the eighth IGBT (S8) to form a bridge arm; the emitter of the ninth IGBT (S9) is connected with the collector of the tenth IGBT (S10) to form another bridge arm; one end of the direct-current voltage source V2 is respectively connected with the collector electrodes of the seventh IGBT (S7) and the ninth IGBT (S9); the other end of the direct-current voltage source V2 is respectively connected with emitting electrodes of an eighth IGBT (S8) and a tenth IGBT (S10) to form a first phase of the three-phase cascade H-bridge inverter (Q); the emitter of the eleventh IGBT (S11) is connected with the collector of the twelfth IGBT (S12) to form a bridge arm; the emitter of the thirteenth IGBT (S13) is connected with the collector of the fourteenth IGBT (S14) to form the other bridge arm; one end of the direct-current voltage source V3 is respectively connected with the collectors of the eleventh IGBT (S11) and the thirteenth IGBT (S13); the other end of the direct-current voltage source V3 is respectively connected with emitting electrodes of a twelfth IGBT (S12) and a fourteenth IGBT (S14) to form a second phase of the three-phase cascade H-bridge inverter (Q); the emitter of the fifteenth IGBT (S15) is connected with the collector of the sixteenth IGBT (S16) to form a bridge arm; the emitter of the seventeenth IGBT (S17) is connected with the collector of the eighteenth IGBT (S18) to form another bridge arm; one end of the direct-current voltage source V4 is respectively connected with the collectors of the fifteenth IGBT (S15) and the seventeenth IGBT (S17); the other end of the direct-current voltage source V3 is respectively connected with the emitting electrodes of the sixteenth IGBT (S16) and the eighteenth IGBT (S18) to form a third phase of the three-phase cascade H-bridge inverter (Q).

The three-phase improved hybrid cascaded multilevel inverter topology structure is characterized in that one end of a load R1 is connected between an emitter of a seventh IGBT (S7) and a collector of an eighth IGBT (S8); one end of the load R2 is connected between an emitter of the eleventh IGBT (S11) and a collector of the twelfth IGBT (S12); one end of the load R3 is connected between the emitter of the fifteenth IGBT (S15) and the collector of the sixteenth IGBT (S16); the other ends of the three loads are connected in parallel and then grounded.

According to the three-phase improved hybrid cascaded multi-level inverter topology, the first phase of the three phases is taken as an example, and is shown in fig. 2. Assuming that the output voltage of a first phase bridge arm of a three-bridge arm inverter (E) is v1, and the output voltage of a first phase of a three-phase cascade H-bridge inverter (Q) is v1, the following steps are provided:

v0=v1+v2

where V0 is the output voltage, assuming that the dc voltage source V1= E and the dc voltage source V2= E, the half-bridge inverter will generate ± E voltage and the full-bridge inverter will generate ± E,0, so that five-level voltage outputs ± 2E, ± E,0 are generated, and the switching states are as shown in fig. 3.

The above description is only illustrative, and not restrictive, of the technical solutions, so that the present invention is not limited to the above embodiments, and all the persons skilled in the art can easily replace and change the technical solutions of the present invention without departing from the spirit and scope of the present invention.

Claims

1. The utility model provides a three-phase improved generation mixes cascaded multilevel inverter topological structure which characterized in that: the three-phase cascade H-bridge inverter comprises a three-phase cascade H-bridge inverter (Q) and a three-bridge arm inverter (E), wherein the total number of the three-bridge arm inverter is 18 IGBTs, direct-current voltage sources V1, V2, V3 and V4 and loads R1, R2 and R3; the three-phase cascade H-bridge inverter (Q) consists of 12 IGBTs and comprises a seventh IGBT (S7), an eighth IGBT (S8), a ninth IGBT (S9), a tenth IGBT (S10), an eleventh IGBT (S11), a twelfth IGBT (S12), a thirteenth IGBT (S13), a fourteenth IGBT (S14), a fifteenth IGBT (S15), a sixteenth IGBT (S16), a seventeenth IGBT (S17) and an eighteenth IGBT (S18); the emitter of the seventh IGBT (S7) is connected with the collector of the eighth IGBT (S8) to form a bridge arm; the emitter of the ninth IGBT (S9) is connected with the collector of the tenth IGBT (S10) to form another bridge arm; one end of the direct-current voltage source V2 is respectively connected with the collector electrodes of the seventh IGBT (S7) and the ninth IGBT (S9); the other end of the direct-current voltage source V2 is respectively connected with emitting electrodes of an eighth IGBT (S8) and a tenth IGBT (S10) to form a first phase of the three-phase cascade H-bridge inverter (Q); the emitter of the eleventh IGBT (S11) is connected with the collector of the twelfth IGBT (S12) to form a bridge arm; the emitter of the thirteenth IGBT (S13) is connected with the collector of the fourteenth IGBT (S14) to form another bridge arm; one end of the direct-current voltage source V3 is respectively connected with the collectors of the eleventh IGBT (S11) and the thirteenth IGBT (S13); the other end of the direct-current voltage source V3 is respectively connected with emitting electrodes of a twelfth IGBT (S12) and a fourteenth IGBT (S14) to form a second phase of the three-phase cascade H-bridge inverter (Q); the emitter of the fifteenth IGBT (S15) is connected with the collector of the sixteenth IGBT (S16) to form a bridge arm; the emitter of the seventeenth IGBT (S17) is connected with the collector of the eighteenth IGBT (S18) to form another bridge arm; one end of the direct-current voltage source V4 is respectively connected with the collectors of the fifteenth IGBT (S15) and the seventeenth IGBT (S17); the other end of the direct-current voltage source V3 is respectively connected with the emitting electrodes of the sixteenth IGBT (S16) and the eighteenth IGBT (S18) to form a third phase of the three-phase cascade H-bridge inverter (Q).

2. The topology of claim 1, wherein the three-leg inverter (E) comprises 6 IGBTs including a first IGBT (S1), a second IGBT (S2), a third IGBT (S3), a fourth IGBT (S4), a fifth IGBT (S5), and a sixth IGBT (S6); the connection mode is that the emitter of the first IGBT (S1) is connected with the collector of the second IGBT (S2) to form a first bridge arm; the emitter of the third IGBT (S3) is connected with the collector of the fourth IGBT (S4) to form a second bridge arm; the emitter of the fifth IGBT (S5) is connected with the collector of the sixth IGBT (S6) to form a third bridge arm; one end of the direct-current voltage source V1 is respectively connected with the collector electrodes of the first IGBT (S1), the third IGBT (S3) and the fifth IGBT (S5); the other end of the direct-current voltage source V1 is respectively connected with the emitting electrodes of the second IGBT (S2), the fourth IGBT (S4) and the sixth IGBT (S6).

3. The topology of the three-phase improved hybrid cascaded multi-level inverter according to claim 1, wherein a first bridge arm of the three-bridge arm inverter (E) and a ninth IGBT (S9) and a tenth IGBT (S10) form a bridge arm cascade; the second bridge arm is cascaded with a bridge arm formed by a thirteenth IGBT (S13) and a fourteenth IGBT (S14); the third bridge arm is cascaded with a bridge arm consisting of a seventeenth IGBT (S17) and an eighteenth IGBT (S18).

4. The topology of claim 1, wherein one end of the load R1 is connected between the emitter of the seventh IGBT (S7) and the collector of the eighth IGBT (S8); one end of the load R2 is connected between an emitter of the eleventh IGBT (S11) and a collector of the twelfth IGBT (S12); one end of the load R3 is connected between the emitter of the fifteenth IGBT (S15) and the collector of the sixteenth IGBT (S16); the other ends of the three loads are connected in parallel and then grounded.