CN218734340U - EtherCAT main station and EtherCAT bus system - Google Patents

Abstract

The utility model discloses an etherCAT main website and etherCAT bus system. The EtherCAT master station comprises an ARM module, an FPGA module, a PHY module and a network interface module, wherein the ARM module is used for processing a protocol and an application layer of the EtherCAT master station; the FPGA module is connected with the ARM module and is used for receiving and transmitting data frames; the PHY module is connected with the FPGA module and is used for converting signals of data frames; and the network interface module is connected with the PHY module and is used for communicating with the outside to transmit signals. This application is based on half soft half hard etherCAT main website of FPGA with ARM for half soft half hard main website has very high real-time, satisfies the requirement of industrial control field high accuracy, and the development degree of difficulty is also less simultaneously, and development cycle is shorter, and human-computer interaction is stronger.

Description

EtherCAT main station and EtherCAT bus system

Technical Field

The utility model relates to a field bus technical field especially relates to an etherCAT main website and etherCAT bus system.

Background

Industrial ethernet systems have developed today for fairly powerful communication systems and have an increasingly important role in the field of automation. The real-time industrial Ethernet Technology EtherCAT (Ethernet for Control Automation Technology) is improved on the basis of the traditional Ethernet, and has the advantages of flexible network topology, simple system configuration, high communication rate, good real-time performance, high effective data rate and the like through the technologies of processing on the fly, distributed clock synchronization and the like, and meanwhile, the compatibility problem and the speed of the interface Technology, the gateway Technology and the like are not difficult to solve after the EtherCAT is used, so the EtherCAT Technology has quite open application prospect in the field of modern industrial Control.

The existing EtherCAT master station has two main implementation schemes, one is a scheme based on a pure software operating system, and adopts a system architecture of a CPU plus a network card; the other is a pure hardware scheme based on FPGA, and the master station is realized based on hardware. The pure software scheme based on the operating system is not favorable for high-precision control in the industrial field due to poor real-time performance of the multitask characteristic of a CPU (Central processing Unit), and is difficult to transplant; and the pure hardware master station based on the FPGA has higher development difficulty, longer development period and poorer man-machine interaction.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides an EtherCAT main website and EtherCAT bus system aims at solving current pure software EtherCAT main website real-time not high, the transplantation degree of difficulty is big, the pure hardware main website development degree of difficulty is big, cycle length and the relatively poor problem of human-computer interaction nature.

The utility model provides an etherCAT main website, include: the system comprises an ARM module, an FPGA module, a PHY module and a network interface module, wherein the ARM module is used for processing a protocol and an application layer of the EtherCAT master station; the FPGA module is connected with the ARM module and is used for receiving and transmitting data frames; the PHY module is connected with the FPGA module and is used for converting signals of data frames; and the network interface module is connected with the PHY module and is used for communicating with the outside to transmit signals.

The utility model provides an among the EtherCAT main website, the FPGA module includes CPU interface module and data frame transceiver module, CPU interface module with the ARM module is connected, data frame transceiver module respectively with CPU interface module with the PHY module is connected, CPU interface module is used for the ARM module with data interaction between the FPGA module, data frame transceiver module be used for with data frame sends out and receives the data frame of returning according to network communication protocol.

The utility model provides an among the EtherCAT main website, the FPGA module is still including sending the buffer memory, send the buffer memory connect in CPU interface module with between the data frame transceiver module, it is used for the buffer memory to send the buffer memory ARM module to transmit for the data of FPGA module.

The utility model provides an among the EtherCAT main website, the FPGA module is still including receiving the buffer memory, receive the buffer memory connect in CPU interface module with between the data frame transceiver module, receive the buffer memory and be used for the buffer memory the FPGA module transmits for the data of ARM module.

The utility model provides an among the EtherCAT main website, the FPGA module still includes the timing module, the timing module with data frame transceiver module connects, the timing module is used for timing so that data frame transceiver module sends according to fixed time periodicity the data frame.

The utility model provides an among the EtherCAT main website, the FPGA module still includes the clock synchronization module, the clock synchronization module with data frame transceiver module connects, the clock synchronization module is used for synchronizing the system time of EtherCAT main website and slave station.

The utility model provides an among the EtherCAT main website, network interface module is RJ45 network interface.

The utility model also provides a etherCAT bus system, include as above etherCAT main website.

The utility model provides an among the EtherCAT bus system, etherCAT bus system still includes the slave station, the slave station is connected with network interface module.

The utility model provides an among the EtherCAT bus system, the slave station is including referring to the slave station, it is used for providing the reference clock for the FPGA module to refer to the slave station.

The utility model provides an etherCAT main website and etherCAT bus system, this etherCAT main website, include: ARM module, the FPGA module, PHY module and network interface module, the ARM module is responsible for the protocol drive and the application layer's of etherCAT main website processing, the comparatively complicated protocol drive and the application of etherCAT main website are realized well to make full use of ARM multitask characteristic, the FPGA module is responsible for the receiving and dispatching of etherCAT main website data frame, the pure hardware circuit of make full use of FPGA disturbs lessly, the stronger characteristics of real-time, fine improvement the real-time of main website, satisfy the real-time control requirement of industrial field high accuracy, the utility model discloses ARM and FPGA's advantage has been combined, both disadvantages have been avoidd simultaneously for half soft and half hard main website has had very high real-time, satisfies the requirement in industrial control field, and the development degree of difficulty is also less simultaneously, and development cycle is shorter, and human-computer interaction is stronger.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without any creative effort.

Fig. 1 is a schematic diagram of an EtherCAT master station according to an embodiment of the present invention;

fig. 2 is a schematic diagram of an FPGA module of an EtherCAT master station according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an EtherCAT bus system according to an embodiment of the present invention.

Description of reference numerals:

100. an EtherCAT master station; 10. an ARM module; 20. an FPGA module; 21. a CPU interface module; 22. a data frame transceiver module; 23. receiving a cache region; 24. sending a buffer area; 25. a timing module; 26. A clock synchronization module; 30. a PHY module; 40. a network interface module; 200. and (4) a secondary station.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the present invention, directional terms such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc. refer to directions of the attached drawings only. Accordingly, the directional terms used are used for describing and understanding the present invention, and are not used for limiting the present invention. Further, in the drawings, structures that are similar or identical are denoted by the same reference numerals;

in the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected" and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; the connection can be mechanical connection, electrical connection or communication connection; may be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The embodiment of the utility model provides a through providing an etherCAT main website and etherCAT bus system, it is not high to have solved current pure software etherCAT main website real-time, the transplantation degree of difficulty is big, the pure hardware main website development degree of difficulty is big, the relatively poor problem of cycle length and human-computer interaction, through the half soft half hard etherCAT main website based on FPGA adds ARM, ARM and FPGA both's advantage has been combined, the disadvantage of both has been avoidd simultaneously, make the existing very high real-time of half soft half hard main website, satisfy the requirement of industrial control field high accuracy, the development degree of difficulty is also less simultaneously, the development cycle is shorter, human-computer interaction is stronger.

The conventional EtherCAT master station is usually a pure software scheme or a pure hardware scheme, wherein for the pure software scheme, an ARM-based open source Linux pure software master station is used, and the protocol and data transmission and receiving of the EtherCAT master station are finished on an ARM core. For the scheme adopting pure hardware, the pure hardware master station based on the FPGA is used, the protocol and data receiving and transmitting of the EtherCAT master station are completed on the FPGA core, and the pure hardware master station has the disadvantages of high development difficulty, long development period, poor man-machine interaction and high investment development cost due to the huge protocol of the master station.

The embodiment of the utility model provides a for solving above-mentioned not high and the difficult problem of development of real-time, its technical scheme as follows:

the technical scheme includes that the FPGA and ARM based semi-soft and semi-hard EtherCAT main station is provided, ARM is used for processing EtherCAT protocols and application, the more complex protocol driving and application of the EtherCAT main station are well achieved by fully utilizing the multitask characteristic of the ARM, FPGA is used for processing data receiving and sending, the FPGA is used for achieving low interference of pure hardware circuits of the FPGA, the real-time performance of the main station is high, the real-time performance of the main station is well improved, the high-precision real-time control requirement of the industrial field is met, therefore, the disadvantages of the FPGA and the industrial field are avoided, the semi-soft and semi-hard main station is enabled to have high real-time performance, the high-precision requirement of the industrial control field is met, meanwhile, the development difficulty is low, the development period is short, and the man-machine interaction is high.

In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.

Referring to fig. 1, fig. 1 is a schematic diagram of an EtherCAT master station 100 provided in an embodiment of the present invention, where the EtherCAT master station 100 includes: the Ethernet control system comprises an ARM module 10, an FPGA module 20, a PHY module 30, a network interface module 40 and the ARM module 10, wherein the ARM module is used for processing a protocol and an application layer of the EtherCAT master station 100; the FPGA module 20 is connected with the ARM module 10, and the FPGA module 20 is used for receiving and transmitting data frames; the PHY module 30 is connected to the FPGA module 20, and the PHY module 30 is configured to convert a data frame; and a network interface module 40 connected to the PHY module 30, wherein the network interface module 40 is configured to communicate with the outside for signal transmission.

Specifically, the ARM module 10 is an ARM (Acorn RISCMachine) processor, and in practical applications, a person skilled in the art can select an appropriate type of processor according to needs, which is not limited herein. The PHY module 30 is specifically a Physical Layer chip, which is referred to as PHY chip for short, and the PHY chip mainly functions to acquire a data frame of the EtherCAT master station 100 through a communication bus, convert the data frame of the EtherCAT master station 100 into a differential signal, transmit the differential signal to an EtherCAT network, and transmit the differential signal to each EtherCAT slave station 200 through a network interface, that is, the PHY module is equivalent to a function of implementing data transceiving. The network interface module 40 is specifically an RJ45 network interface.

Through implementing this embodiment, based on semi-soft half hard EtherCAT main website 100 of FPGA plus ARM make full use of both advantages, synthesize both strong points, solved the pure software main website real-time not high promptly, transplant the great problem of the degree of difficulty, solved the pure hardware main website development degree of difficulty again great, the development cycle is longer and human-computer interaction is relatively poor problem.

Referring to fig. 2, in an embodiment, the FPGA module 20 (field programmable Gate Array module) includes a CPU interface module 21, a data frame transceiver module 22, a receiving buffer 23, a sending buffer 24, a timing module 25, and a clock synchronization module 26. In this embodiment, the CPU interface module 21 is connected to the ARM module 10, the data frame transceiver module 22 is connected to the CPU interface module 21 and the PHY module 30, the CPU interface is used for data interaction between the ARM module 10 and the FPGA module 20, and the data frame transceiver module 22 is used for sending out a data frame and receiving a returned data frame according to a network communication protocol; the sending buffer area 24 is connected between the CPU interface module 21 and the data frame transceiver module 22, and the sending buffer area 24 is used for buffering data transmitted to the FPGA module 20 by the ARM module 10; the receiving buffer area 23 is connected between the CPU interface module 21 and the data frame transceiver module 22, and the receiving buffer area 23 is used for buffering data transmitted to the ARM module 10 by the FPGA module 20; the timing module 25 is connected to the data frame transceiver module 22, and the timing module 25 is configured to time to enable the data frame transceiver module 22 to periodically transmit data frames according to a fixed time; and the clock synchronization module 26, the clock synchronization module 26 is connected with the data frame transceiver module 22, and the clock synchronization module 26 is used for synchronizing the system time of the EtherCAT master station 100 and the system time of the EtherCAT slave station 200. By setting the separate receiving buffer area 23 and sending buffer area 24, the data is buffered, so that the processing pressure of the ARM module 10 can be reduced, and the stability and efficiency of data receiving and sending can be improved. The data frame transceiver module 22 is also used for verifying the valid data frame.

Specifically, the FPGA module 20 includes a CPU interface module 21, a receiving buffer 23, a sending buffer 24, a data frame transceiving module 22, a timing module 25, and a clock synchronization module 26. The CPU interface module 21 is in charge of being connected with the ARM core in a butt joint mode and is used for data interaction between the ARM core and the FPGA core; the sending buffer area 24 is used for buffering data transmitted to the FPGA by the ARM; the receiving buffer area 23 is used for buffering data transmitted to the ARM by the FPGA; the data frame transceiver module 22 sends out an EtherCAT data frame according to a network communication protocol and receives back the EtherCAT data frame at the same time; the timing module 25 is responsible for timing and periodically sends out EtherCAT data frames according to fixed time; the clock synchronization module 26 is responsible for synchronizing the system time of the EtherCAT master station 100 and the system time of the slave station 200, so that high real-time performance is guaranteed, and the requirements of the industrial field are met.

In other embodiments, in order to ensure the clock synchronization of the EtherCAT master 100 and the slave 200, in addition to the above-mentioned implementation by the clock synchronization module 26, the present embodiment also provides an alternative synchronization method. For example, a real-time patch such as Xenomai can be inserted into the Linux operating system of the ARM core, and the real-time performance of the EtherCAT master station 100 is ensured through the FPGA core and the real-time patch.

In order to show the advantages of the EtherCAT master station 100 of this embodiment, the following description is provided by a data transmission and reception process of the EtherCAT master station 100 of this embodiment.

Firstly, the FPGA module 20 triggers an interrupt of the ARM through a signal, where the signal is a common pulse signal generated by the FPGA, the interrupt type of the ARM is set as a rising edge trigger, and the rising edge of the pulse signal is detected to trigger the ARM interrupt. When an interrupt is received by ARM module 10, a corresponding datagram is prepared according to the protocol of EtherCAT master station 100 and sent to send buffer 24 via the application interface, where the datagram refers to EtherCAT standard datagram, for example, etherCAT datagram with initialization configuration data is sent when master station needs to initialize slave stations 200 it controls. The FPGA polls the data in the sending buffer 24, and then calls the data frame transceiver module 22 to send the data frame, when the EtherCAT master station 100 protocol is still in the initialization stage, the data frame can be directly sent, and when in the operation stage, that is, when sending the periodic process data, the timing module 25 needs to be called to send the data at regular time according to the set period. After the datagram returns to the FPGA through the slave station 200, the FPGA calls the transceiver module to receive the returned data frame, and stores the data frame in the receiving buffer area 23, then generates a signal to trigger ARM interruption to notify the ARM module 10 to take away the data in the buffer area, and then the ARM sends a new data frame according to the received data and the EtherCAT master station 100 protocol, and the process is circulated, so that the data receiving and sending processes are realized.

Referring to fig. 3, the embodiment of the present invention further provides an EtherCAT bus system, where the EtherCAT bus system includes the EtherCAT master station 100 described in the above embodiment, the EtherCAT bus system further includes a slave station 200, and the slave station 200 is connected to the network interface module 40. Since the foregoing description has described the architecture and the operation principle of the EtherCAT master station 100 in detail, the details are not repeated herein for the simplicity of the description.

In this embodiment, the slave station 200 comprises a reference slave station 200, and the reference slave station 200 is used for providing a reference clock for the FPGA module 20. Specifically, in the EtherCAT bus system, the EtherCAT master station 100 and a plurality of slave stations 200 are included, the slave stations 200 are in communication connection with the EtherCAT master station 100 through a network interface, and a referencing slave station 200 is disposed in the slave stations 200, and the referencing slave station 200 is specially used for providing a referencing clock to perform clock synchronization with the EtherCAT master station 100. Specifically, the FPGA receives the datagram returned by the slave station 200, and at the same time, the FPGA calls the clock synchronization module 26 to analyze the datagram returned by the slave station 200 to obtain the system time of the reference slave station 200, and then corrects the system time of the FPGA, so that the system time of the FPGA and the reference clock are kept consistent, and the real-time performance of the master station is improved.

Through the EtherCAT bus system of this embodiment, based on FPGA and ARM's half soft half hard EtherCAT main website 100, the advantage of ARM and FPGA both has been combined, the disadvantage of both has been avoided simultaneously for half soft half hard main website has very high real-time, satisfies the requirement of industrial control field high accuracy, and the development degree of difficulty is also less simultaneously, and development cycle is shorter, and human-computer interaction is stronger, and the time synchronization of EtherCAT main website 100 and slave station 200 is accomplished at FPGA simultaneously.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope of the present invention, and these modifications or replacements should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. An EtherCAT master station, comprising:

the ARM module is used for processing a protocol and an application layer of the EtherCAT master station;

the FPGA module is connected with the ARM module and is used for receiving and transmitting data frames;

the PHY module is connected with the FPGA module and is used for converting the signals of the data frames;

and the network interface module is connected with the PHY module and is used for communicating with the outside to transmit signals.

2. The EtherCAT master station according to claim 1, wherein the FPGA module includes a CPU interface module and a data frame transceiver module, the CPU interface module is connected to the ARM module, the data frame transceiver module is connected to the CPU interface module and the PHY module, respectively, the CPU interface module is used for data interaction between the ARM module and the FPGA module, and the data frame transceiver module is used for sending out the data frame and receiving a returned data frame according to a network communication protocol.

3. The EtherCAT master station of claim 2, wherein the FPGA module further comprises a transmit buffer, the transmit buffer is connected between the CPU interface module and the data frame transceiver module, and the transmit buffer is configured to buffer data transferred to the FPGA module by the ARM module.

4. The EtherCAT master station of claim 3, wherein the FPGA module further comprises a receive buffer, the receive buffer is connected between the CPU interface module and the data frame transceiver module, and the receive buffer is configured to buffer data transmitted from the FPGA module to the ARM module.

5. The EtherCAT master station of claim 4, wherein the FPGA module further comprises a timing module, the timing module is connected to the data frame transceiver module, and the timing module is configured to time to enable the data frame transceiver module to periodically transmit the data frame according to a fixed time.

6. The EtherCAT master station of claim 5, wherein the FPGA module further comprises a clock synchronization module, the clock synchronization module is connected to the data frame transceiver module, and the clock synchronization module is configured to synchronize system times of the EtherCAT master station and the EtherCAT slave station.

7. The EtherCAT master station according to any one of claims 1 to 6 wherein the network interface module is an RJ45 network interface.

8. An EtherCAT bus system comprising an EtherCAT master station according to any one of claims 1 to 7.

9. The EtherCAT bus system according to claim 8, further comprising a slave station, the slave station being connected to the network interface module.

10. The EtherCAT bus system according to claim 9 wherein the slave station comprises a reference slave station for providing a reference clock to the FPGA module.

Images