CN218679039U - Analog-digital converter - Google Patents

Abstract

The embodiment of the disclosure provides an analog-digital converter, which comprises a channel multiplexing selection unit, a grouping/channel control configuration unit, a grouping/channel arbitration control unit, an incremental accumulator and a sampling time register unit. Through the processing scheme disclosed by the invention, the analog-to-digital converter can effectively reduce the problem of overlarge matching error between the sampling time and the conversion result of sampling conversion of a certain analog channel caused by the reason that other analog channels are processed preferentially or the time consumption of sampling conversion fluctuates, so that the precision of performing subsequent analysis processing on the sampling result under the condition is improved.

Description

Analog-digital converter

Technical Field

The utility model relates to an analog-to-digital converter controller technical field, concretely relates to analog-to-digital converter.

Background

Generally, the analog-to-digital conversion process performed by the AD circuit is a discrete sampling and conversion process (simply referred to as sampling and conversion process) for digitizing an analog signal. Therefore, the mapping precision between the sampling time of the sampling and transferring process and the content of the sampling and transferring result is very important for the subsequent analysis and processing of the sampling and transferring result in the MCU (microprocessor chip) system. Although theoretically, the error deviation of the mapping relationship may be minimized by applying some compensation/correction algorithm in the MCU system (such operation increases the complexity of the analysis process). However, if not timely and sufficiently reduced, the accumulation to a certain extent may result in a complete breakdown/uncorrectable of the subsequent analysis process (i.e., an initialization operation is introduced to restore the analysis processing system to normal, which increases the complexity of the analysis process and reduces the available time margin for the normal subsequent analysis process).

In order to minimize the deviation of the mapping relationship between the sampling time and the sampling result content, the designer of the MCU system must take some measures:

the first common measure is: a plurality of sets of AD circuits are physically integrated, so that the conventional grouping and the injection grouping can respectively complete the sampling and conversion processing in different AD circuits, and the condition of 'the insertion flow of the injection grouping' is fundamentally avoided. However, obviously, the biggest drawback of this measure is that it significantly increases the overhead of additional hardware resources, and is not an effective method for improving the matching error between the sampling time and the conversion result.

Another common measure is: the normal packet is given priority over the injected packet to avoid the extraction process of the injected packet being inserted during the extraction of the normal packet. However, it is obvious that the main defect of this measure is that the existence definition of the injection packet is violated, and further the timeliness of the sampling and conversion processing of the injection channel analog signal cannot be ensured, and the matching error between the sampling time and the conversion result cannot be effectively improved.

SUMMERY OF THE UTILITY MODEL

The disclosed embodiments provide an analog-to-digital converter, a chip and an electronic device, which at least partially solve the problems in the prior art.

In a first aspect, an embodiment of the present disclosure provides an analog-to-digital converter, including: the channel multiplexing selection unit is used for determining a target channel to be subjected to AD processing and a target analog signal corresponding to the channel to be subjected to AD processing from a plurality of input channels based on at least one input analog signal and at least one channel selection signal corresponding to the analog signal, and transmitting the target analog signal to the AD circuit to perform actual analog-digital conversion processing;

the system comprises a grouping/channel control configuration unit, a channel control configuration unit and a control unit, wherein the grouping/channel control configuration unit is used for determining control configuration information according to received configuration information of an MCU system, and the control configuration information is used for carrying out configuration control on acquisition and transfer processing of different groups or channels;

the grouping/channel arbitration control unit is used for determining a channel selection signal and a channel sampling trigger signal of each channel based on the received global sampling-switching trigger signal, the control configuration information and a rule of processing sequence or priority pre-programmed for each channel, wherein the channel selection signal is used for making a selection instruction for the channel, and the channel sampling trigger signal is used for making a starting instruction of current AD processing for the AD circuit;

the incremental accumulator is used for carrying out incremental accumulation updating on the working clock period of each analog-to-digital converter under the driving of the working clock of the analog-to-digital converter so as to provide a time reference for capturing sampling time;

and the sampling time registering unit is used for capturing and registering a real-time value of the incremental accumulator based on the channel sampling trigger signal to serve as a sampling time, and combining the sampling time and the content of a channel conversion result and then providing the combined sampling time and the content of the channel conversion result to the MCU system.

According to a specific implementation manner of the embodiment of the present disclosure, the method further includes:

the global sampling and conversion trigger signal generating unit is generated by other circuit logics outside the analog-to-digital converter and/or by some circuit logics inside the analog-to-digital converter, and the global sampling and conversion trigger signal is used for starting sequential continuous sampling and conversion processes of analog signals of a plurality of channels;

the incremental accumulator is used for regarding the global sampling and rotation trigger signal as a time zero point when in an absolute counting mode, and the incremental accumulation is started from the corresponding zero point value, and the incremental accumulator returns to the zero point value when the zero point value is increased to the maximum value or the MCU system reset is met.

According to a specific implementation manner of the embodiment of the present disclosure, when the incremental accumulator is in the relative counting mode, the incremental accumulator is used to regard the global sampling and rotation trigger signal and the sampling trigger signal of any channel as a time zero, and increment and accumulate from the corresponding zero value, capture the real-time value of the incremental accumulator at the start of the next sampling and rotation, and then return to the zero value.

According to a specific implementation manner of the embodiment of the present disclosure, when the incremental accumulator is in the absolute count mode, the sampling time register unit is configured to represent a sampling time start time value of each channel.

According to a specific implementation manner of the embodiment of the present disclosure, when the incremental accumulator is in the relative count mode, the sampling time register unit is configured to represent a time-consuming value of completion of the sampling and transfer processing of the latest historical channel.

According to a specific implementation manner of the embodiment of the present disclosure, after a certain effective global sampling trigger signal occurs, the first sampling time captured by the sampling time register unit represents a time difference between the effective global sampling trigger signal and a first effective channel sampling trigger signal.

According to a specific implementation manner of the embodiment of the present disclosure, the MCU system is configured to calculate a sampling start time point of each channel according to the sampling time captured by the sampling time register unit.

According to a specific implementation manner of the embodiment of the present disclosure, under the condition that the MCU system does not need to know the sampling time information of each channel, the incremental accumulator and the sampling time register unit are in an idle state that are not used.

In a second aspect, an embodiment of the present disclosure provides a chip, including: an analog to digital converter as claimed in any one of the preceding aspects.

In a third aspect, an embodiment of the present disclosure further provides an electronic device including: at least one chip as described in the second aspect.

The analog-to-digital converter, the chip and the electronic equipment in the embodiment of the disclosure comprise a channel multiplexing selection unit, a grouping/channel control configuration unit, a grouping/channel arbitration control unit, an incremental accumulator and a sampling time register unit. The scheme disclosed by the invention can effectively reduce the problem of overlarge matching error between the sampling time of sampling conversion and a conversion result of a certain analog channel caused by the reason that other analog channels are preferentially processed or the time consumption of sampling conversion fluctuates by adding the incremental accumulator and the sampling time register unit, thereby improving the precision of performing subsequent analysis processing on the sampling result under the condition.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic circuit architecture diagram of an analog-to-digital converter according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of the analog-to-digital conversion process for a continuous analog signal;

FIG. 3 is a diagram illustrating the effect of a single channel when a mismatch between the sampling time and the conversion result occurs;

FIG. 4 is a schematic diagram of a plurality of channels associated with each other being unable to perform absolute synchronous sampling;

FIG. 5 is a schematic diagram of the application of the analog-to-digital conversion process in a conventional motor closed-loop automatic control system;

FIG. 6 is a schematic diagram of the present disclosure with injected packet mining-transfer processing queue in the middle of normal packet mining-transfer in the absolute count mode;

fig. 7 is a schematic diagram of the injection packet transfer processing queue in the middle of the conventional packet transfer in the relative count mode according to the present disclosure.

Detailed Description

Many Microprocessor Chips (MCU) are integrated with Analog-to-Digital converters (ADC) or Analog-to-Digital converters (ADC) to control Analog-to-Digital conversion circuits (AD) to perform sampling and Digital conversion of Analog signals. An ADC can control the AD circuit to perform time-division sampling of the multi-channel analog signal and convert the multi-channel analog signal into a digital signal by multiplexing (refer to fig. 2, fig. 2 is a schematic diagram of the analog-to-digital conversion process for continuous analog signals). The analog signal of each channel has a corresponding sampling trigger signal, the AD circuit is triggered at a specific moment to complete analog-digital sampling and conversion, and the conversion result needs to keep a one-to-one correspondence with the time (which can be referred to as sampling time, the same below) of the sampling trigger moment so as to determine the matching relationship between the sampling time and the digital conversion result. Only if this matching relationship is accurate, the characteristic curve of the analog signal can be reproduced relatively accurately in the subsequent processing of the digital signal.

In one application scenario, the analog signals of some channels in the multi-channel analog signals to be processed by the ADC are a set of correlated signals, and it is desirable to sample and convert the set of signals at the same time to restore the correlation between the set of signals at the time. However, since one AD circuit can only process one channel analog signal at one time, the ADC can only perform scanning sequential continuous sampling on the group of analog signals after receiving the effective sampling trigger signal of the group of analog signals, and complete the sampling within a short time as much as possible; the sampling conversion time consumption of each channel of the set of signals is always the same, if the ADC does not insert sampling conversion processing of other analog signals in the scanning sampling process of the set of analog signals, the conversion result of each channel can be matched with the sampling time one by one, and then the conversion result of the set of analog signals can be restored by a post-processing algorithm relatively realistically, or the non-sampled signal condition can be derived by using the obtained conversion result and the known correlation.

However, in practical application of the MCU chip, it is difficult to ensure that a sampling application of an analog signal of a certain channel can be processed in time, or because the AD sampling conversion time itself fluctuates, it may cause the sampling time of the analog signal of the certain channel to deviate from the expected value, thereby introducing an error in the matching relationship between the conversion result and the expected sampling time. The error in this matching relationship will necessarily increase the error between the original analog signal curve and the digitally fitted signal curve, or will increase the complexity of the post-processing algorithm for the digital signal.

At present, the expected sampling time of an ADC for an analog signal of a certain channel is calculated based on a sampling trigger signal of the ADC, and the ADC only outputs a sampling conversion result of the channel and does not output any sampling time information. When the effective sampling trigger signal of a certain channel cannot be responded by the ADC in time (for example, other channels need to be processed preferentially), or the effective sampling trigger signal of the channel itself has time fluctuation, which causes the actual sampling time of the channel to deviate from the expected value thereof, an error is inevitably introduced in the matching relationship between the conversion result and the sampling time, and the post-processing algorithm generally cannot know the error only from the conversion result, which in turn increases the error between the original analog signal curve and the digitized fitted signal curve, or increases the complexity of the post-processing algorithm for the digital signal.

Fig. 3 is a schematic diagram of a single channel when a mismatch between the sampling time and the conversion result occurs. Assuming that a single target channel is subjected to analog-to-digital conversion processing on corresponding analog signals repeatedly at times such as t1/t 2/\ 8230;/t 7 without any special condition. It is further assumed that the original input analog signal is in the form of an ideal triangular waveform (which is also the original analog signal curve, as shown by the dashed waveform).

Now, because the valid channel sampling trigger signal of the channel cannot be responded by the ADC in time (for example, other channels need to be processed preferentially), or the valid channel sampling trigger signal of the channel has time fluctuation, the channel sampling process originally expected to start at the time t2/t5 is delayed to start at the time tA/tB. However, without the MCU system being aware of this special case, it would misinterpret the conversion at time tA/tB as the conversion at time t2/t5 and then derive a falsely biased digitized fit curve based on an ideal fit function (as shown by the solid line waveform). Therefore, the MCU system will then generate accumulated errors in subsequent processing of the digital signal based on this fitted curve with significant error bias.

Fig. 4 is a schematic diagram illustrating that a plurality of mutually associated channels cannot perform absolute synchronous sampling. In one embodiment of the MCU system, the three-phase stator winding coils are configured in a three-three conducting (not two-two conducting) application, so that the back emf E is estimated by synchronously detecting the three-phase armature currents. However, in general, a motor control MCU is usually integrated with only one set of AD circuits to save hardware resource overhead, and therefore, it is necessary to queue up and separate the sampling and conversion processes of three-phase current analog signals from different channels, which are originally expected to start at the same time.

As shown in fig. 4, it is assumed that the sampling and conversion process is first started for the U-phase current at time t0, and is correspondingly completed at time t0+ n; therefore, the sampling and transfer processing of the V-phase current and the W-phase current can be triggered only at the moment t0+ n and t0+2n respectively at the earliest (note that, in the figure, for the convenience of a reader, the three moments are drawn to be larger in distance, and are very close to each other in an actual waveform curve); therefore, the actual conversion results of the V-phase and W-phase currents (shown as Iv 'and Iw' in the figure) are certainly different from the conversion results (shown as Iv and Iw in the figure) originally expected to be obtained at the time t 0. However, if the correlation matching precision of the sampling time and the conversion result of each channel of the three-phase current can be guaranteed, the MCU system can reversely calculate a high-precision approximate value of the expected conversion result on the time axis based on the detected actual conversion result and the target fitting function, so that a back emf curve with sufficient precision can be calculated based on the conversion result of the three-phase current at the same time during subsequent analysis.

Taking a brushless dc motor control MCU chip (hereinafter referred to as a motor control MCU) as an example, a general motor control MCU needs to acquire a set of back electromotive force voltage analog signals corresponding to three-phase stator winding coils of a motor, and calculate information such as an angular position, a rotation speed, etc. of the motor winding coils relative to a permanent magnet of an inner ring rotor of the motor by using changes of the set of back electromotive force voltage analog signals. Since the sum of the three back electromotive force voltage analog signals of the three-phase stator winding coil of the motor at any moment is constant to zero in an ideal situation, the back electromotive force voltage of the other phase can be calculated by sampling the back electromotive force voltage analog signals of any two phases.

In a configuration scenario without a position sensor, in order to obtain the three-phase back electromotive force voltage analog signals through sampling, in a common scheme, current analog signals corresponding to three-phase stator winding coils of the motor need to be output from the motor and provided to the motor control MCU as feedback information.

While the current analog signal is subjected to the AD processing (i.e., analog/digital conversion processing), the same motor control MCU may also need to perform sampling conversion (i.e., abbreviation of sampling conversion) to process input analog signals of other channels, such as power supply voltage, chip temperature, driving current, and the like of the MCU itself. Therefore, the MCU will have the possibility to perform AD and subsequent analysis processing on analog signals of multiple input channels from different sources relatively synchronously within the same short time window.

The conventional method in the MCU system for motor control is to perform the above processing on the input analog signals from different sources with multiple channels, which generally includes:

ensuring that the sampling rate of the AD process is much higher than the required sampling rate of the input analog signal, while the sampling frequency is more than twice the maximum frequency of the input analog signal;

grouping the analog signals on the plurality of input channels into different categories; (for example, in the above example, the motor feedback current and the MCU chip temperature are two types of analog signals that need to be grouped differently);

adopt time-sharing multiplexing way and preset priority algorithm, only integrate a set of ADC circuit to finish AD processing control work of input analog signal of the multichannel in different groups (certainly can also be the same group);

the sampling and conversion results of the different channels are provided to the MCU system by the single ADC circuit so as to carry out further subsequent analysis processing.

In a more specific application scenario, the common rules of making the motor control MCU are: the current analog signals fed back by the motor are defined in a regular grouping (note: respectively called regular channel), while analog signals of other sources are defined in an injection grouping (note: respectively called injection channel). When the MCU system generates a sampling trigger signal for starting the conventional packet sampling and transfer processing, the input analog signals of a plurality of channels selected in the conventional packet are sequentially and continuously processed according to the preset precedence order or priority (note: the control involved in the processing is taken charge of by the ADC circuit, the analog-to-digital sampling and transfer processing at the bottom layer is realized by the AD circuit, and the same is true for the injected packet). In the general design of the ADC circuit, the processing priority of the injected packet is generally designed to be higher than that of the conventional packet; in other words, if the application for the sampling and transfer processing of the injected packet is inserted in the multi-channel sampling and transfer process of a certain conventional packet, the sampling and transfer processing of the current remaining channels of the conventional packet is suspended, and the ADC circuit preferentially performs the sampling and transfer processing of each channel of the injected packet inserted in the queue until the sampling and transfer processing of all the selected channels in the injected packet is completed, and then returns to resume performing the sampling and transfer processing control of the remaining channels in the conventional packet. Note that: the entire process of injection queueing → conventional interruption → conventional recovery above may be simply referred to as "flow of insertion of injected packets".

Now assume that: the insertion process of the injection packet does not occur at all in the sampling and transfer process of each channel of a certain conventional packet, because the sampling and transfer time consumption of a single channel is usually determined (on the premise that the operating principle and the sampling and transfer resolution of the AD circuit are both determined, the single sampling and transfer time consumption of the conventional channel and the injection channel are consistent and fixed), and if the sampling time point time of the first channel in the packet can be determined (hereinafter, the sampling time of the first channel is referred to as the sampling and transfer start time), the sampling time of each channel in the conventional packet can be calculated. Therefore, on the premise that the sampling and conversion results can be timely stored, the mapping corresponding relation between the sampling time of each conventional channel and the contents of the sampling and conversion results is bound and associated.

If the above assumption is not satisfied, that is, "the insertion process of the injection packet" occurs during the sampling and transfer process of each channel of the normal packet, since the MCU system cannot predict the specific insertion time of the injection packet, if it still calculates the mapping relationship between the sampling time and the sampling and transfer result content of the normal channel according to the above assumption, an error deviation will inevitably occur.

In some cases where higher accuracy is required for the analog-to-digital conversion processing, it is obvious that the above-mentioned error deviation of the mapping relationship is extremely disadvantageous for the digital analysis processing to be performed subsequently to the conversion result. In order to avoid the mapping deviation between the sampling time and the sampling result content when the input analog signals of multiple channels are subjected to AD and subsequent analysis processing, the present disclosure provides an analog-to-digital converter, and the following describes an embodiment of the present disclosure in detail with reference to the accompanying drawings.

The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

Referring to fig. 1, fig. 1 is a schematic diagram of some embodiments of an analog-to-digital converter according to the present disclosure. As shown in fig. 1, the analog-to-digital converter includes:

the channel multiplexing selection unit is used for determining a target channel to be subjected to AD processing and a target analog signal corresponding to the channel to be subjected to AD processing from a plurality of input channels based on at least one input analog signal and at least one channel selection signal corresponding to the analog signal, and transmitting the target analog signal to the AD circuit to perform actual analog-digital conversion processing;

the system comprises a grouping/channel control configuration unit, a channel control configuration unit and a control unit, wherein the grouping/channel control configuration unit is used for determining control configuration information according to received configuration information of an MCU system, and the control configuration information is used for carrying out configuration control on acquisition and transfer processing of different groups or channels;

the packet/channel arbitration control unit is used for determining a channel selection signal and a channel sampling trigger signal of each channel based on the received global sampling and switching trigger signal, the control configuration information and a pre-programmed processing sequence or priority rule for each channel, wherein the channel selection signal is used for making a selection instruction for the channel, and the channel sampling trigger signal is used for making a starting instruction of current AD processing for the AD circuit;

the incremental accumulator is used for carrying out incremental accumulation updating on the working clock period of each analog-to-digital converter under the driving of the working clock of the analog-to-digital converter so as to provide a time reference for capturing sampling time;

and the sampling time registering unit is used for capturing and registering a real-time value of the incremental accumulator based on the channel sampling trigger signal to serve as a sampling time, and combining the sampling time and the content of a channel conversion result and then providing the combined sampling time and the content of the channel conversion result to the MCU system.

In some embodiments, referring to fig. 1, the circuit architecture includes an ADC circuit 1 (i.e., an analog-to-digital conversion controller), and an AD circuit 2, where the ADC circuit 1 is responsible for performing operations such as arbitration selection of an input signal to be analog-to-digital converted and register of a conversion result. The ADC controller first includes several components and key signals that the following general ADC circuits would normally include:

a multiplex selection unit 10;

a packet/channel control configuration unit 11;

a packet/channel arbitration control unit 12;

a channel conversion result register unit 13;

global sampling transfer trigger signal;

a channel selection signal;

the channel samples the trigger signal.

The multiplexing selection unit 10 is configured to select a path of analog signal from multiple input channels based on a corresponding channel selection signal, and transmit the analog signal to an AD circuit for actual analog-to-digital conversion;

the grouping/channel control configuration unit 11 is configured to perform configuration control on sampling and conversion processing that the ADC circuit may perform for different groups or channels according to related configuration information derived from the MCU system;

the grouping/channel arbitration control unit 12 is configured to make arbitration selection for a channel currently to be subjected to AD processing based on the control configuration information and a processing sequence or priority setting preprogrammed for each channel;

the channel conversion result registering unit 13 is configured to appropriately register a conversion result output by the AD circuit after completion of the sampling and conversion, so as to be conveniently obtained by the MCU system in various application situations;

the global sampling and converting trigger signal is used for starting a group of sequential continuous sampling and converting processes of analog signals of a plurality of channels. Generally, it is usually generated by other circuit logic outside the ADC circuit, alternatively it may be generated by some part of the circuit logic inside the ADC circuit.

Wherein the channel selection signal is used for making selection indication for the channel to be AD-processed currently, and is generated by the grouping/channel arbitration control unit.

Wherein, the channel sampling trigger signal is used for indicating the starting of the current AD processing to the AD circuit, and is generated by the grouping/channel arbitration control unit.

Next, based on any of the above embodiments, the embodiments of the analog-to-digital converter of the present disclosure add the following components on the basis of a general ADC circuit: an incremental accumulator and a sample time register unit.

The incremental accumulator is driven by an ADC circuit working clock, and is updated in an incremental accumulation mode in each ADC clock period so as to provide a time reference for capturing the sampling time.

The sampling time register unit is used for capturing and registering the real-time value of the incremental accumulator based on an effective channel sampling trigger signal, and combining the real-time value as the sampling time information and the channel conversion result content for the MCU system to obtain in pairs.

Based on any of the above embodiments, the incremental accumulator can realize the absolute counting mode and/or the relative counting mode by only integrating one (or more according to actual conditions) in the ADC circuit.

In absolute count mode, the incremental accumulator increments the accumulation starting from some selected zero value (including but not limited to 0 or 1, the same below) treating the global sampling-transition trigger signal as a time zero; the incremental accumulator returns to a zero value only when it increments to a limit or maximum value (e.g., a 32-bit wide accumulator increments back to a zero value if it counts to 0xffff _ffff) or a system reset is encountered.

In the relative counting mode, the incremental accumulator considers the global sampling and conversion trigger signal and any channel sampling trigger signal as a time zero and increments and accumulates from a selected zero value; typically, the incremented accumulator should return to a zero value (e.g., 1) to restart the incrementing when it increments to some smaller corresponding value (e.g., the accumulator of 5-bit width is counting to 0x 12). The difference between the smaller corresponding value and the selected zero value is the time consumed for completing the single AD (i.e., single channel) sampling process.

Wherein the zero value at the relative count modulus may be preset.

In the relative count modulo, the global sampling trigger signal and the sampling trigger signal of any channel are regarded as a time zero, and are accumulated in increments from the corresponding zero value, and the real-time value of the incremental accumulator is captured and returned to the zero value when the next sampling is started, so that the difference between the captured real-time value and the zero value is the generalized time consumption of the current sampling (the narrow time consumption is the time consumption of the sampling process itself, and the generalized time consumption is increased by other factors, such as the queue insertion of the injected packets).

On the basis of any embodiment, the sampling time register unit is integrated into at least one of the ADC circuits, or a plurality of the ADC circuits according to the requirements of specific applications. Generally speaking, the integration number of the channel conversion result register unit and the integration number of the channel conversion result register unit can be kept consistent.

Regardless of the counting mode of the incremental accumulator, the sampling time register unit is captured and registered as a real-time value of the incremental accumulator when any channel sampling trigger signal is valid.

On the basis of any of the above embodiments, the number and the edge of the sampling time register units can be divided into:

1) The integrated channels of all the conventional groups are respectively integrated with an independent sampling time register unit, so that the conversion results of the conventional channels cannot be mutually covered to cause data omission;

2) Only one shared sampling time register unit is integrated for all integrated channels of the conventional grouping, so that conversion results of the MCU system to all conventional channels can be conveniently obtained from the same register unit, and the corresponding control complexity is reduced;

3) Independent sampling time register units are respectively integrated for all the integrated channels of the injection grouping, so that conversion results of all the injection channels cannot be mutually overlapped to cause data omission;

4) Only one shared sampling time register unit is integrated for all integrated channels of the injection grouping, so that conversion results of the MCU system to all injection channels can be conveniently obtained from the same register unit, and the corresponding control complexity is reduced;

5) In the case of the conventional packet and the injection packet existing at the same time, the sampling time register unit integration scheme of the two types of packets can be selected from the schemes 1) or 2), and 3) or 4) respectively. In addition, it may also be possible to integrate one or more of the sample time register units indiscriminately for both types of packets, under certain circumstances as allowed by the application and configuration environment.

In addition, if the application can ensure that the channel sampling process of the injected packet always has the highest priority, it is not necessary to integrate a dedicated sampling time register unit for the channel sampling process, that is, a conventional packet and the injected packet can share one or more sampling time register units.

On the basis of any of the above embodiments, when the incremental accumulator is in the absolute count mode, the sampling time register unit generally represents the sampling time start time value of each channel.

On the basis of any one of the above embodiments, when the incremental accumulator is in the relative count mode, the sampling time register unit generally represents the value of the sampling completion time consumption of the latest historical channel.

Regardless of the counting mode of the incremental accumulator, the sampling time register unit is a real-time value captured and registered as the incremental accumulator when any channel sampling trigger signal is active.

On the basis of any of the above embodiments, no matter in which counting mode, the capture value of the first sampling time register unit after a certain effective global sampling-transfer trigger signal appears specifically represents the time difference between the effective global sampling-transfer trigger signal and the first effective channel sampling-transfer trigger signal;

on the basis of any of the above embodiments, in any of the counting modes, the MCU system can calculate the same time information of the sampling start time point of each channel from the captured value of the sampling time register unit, that is, the high-precision sampling start time information of each channel on the time axis with the valid position of the global sampling trigger signal as the initial time zero point.

Based on any of the above embodiments, the incremental accumulator, sample time register unit may in some cases be in an idle state that is not enabled. These include, but are not limited to: the MCU system does not need to know the sampling time information of each channel, for example, the MCU system can confirm that the sampling and conversion process of other channels will not be inserted in the sampling and conversion process of a certain set of input channel analog signals, and the sampling and conversion time of each channel of the set is known and determined.

The analog-to-digital converter in the embodiment of the disclosure comprises a channel multiplexing selection unit, a grouping/channel control configuration unit, a grouping/channel arbitration control unit, an incremental accumulator and a sampling time register unit. The scheme disclosed by the invention can effectively reduce the problem of overlarge matching error between the sampling time of sampling conversion and a conversion result of a certain analog channel caused by the reason that other analog channels are preferentially processed or the time consumption of sampling conversion fluctuates by adding the incremental accumulator and the sampling time register unit, thereby improving the precision of performing subsequent analysis processing on the sampling result under the condition.

In one embodiment, a global sampling trigger signal corresponds to the time zero, and the first channel sampling trigger signal is driven to be generated in the ADC circuit after a unit time elapses, and the incremental accumulator is updated to a (whether in absolute or relative count mode). After the sampling trigger signal of the first channel is effectively generated, the AD sampling conversion processing of the first channel starts to be carried out, and in the period:

1. if the incremental accumulator is in the relative counting mode, the updating process is to increment from 1 (selected zero value) to n (representing the time consumed for completing the sampling and transferring of a single AD treatment);

2. if the incremental accumulator is in the absolute counting mode, the updating process of the incremental accumulator is to increment from A +1 (selected zero value) to A + n (representing the time consumed for completing the acquisition and transfer of a single AD processing);

when the sampling and conversion of the first channel are finished, according to the comprehensive consideration of the conditions of the MCU system and the AD circuit, the sampling trigger signal of the second channel can be synchronously generated or generated after little delay. Note that, specifically, whether it must be generated after a delay or immediately, it needs to consider the following two factors in combination:

a specific delay from the channel sampling trigger signal generated by the ADC circuit to the corresponding receiving port of the AD circuit in the actual circuit environment can be identified;

in an actual circuit environment, a specific delay from "a channel sampling completion indication signal generated by an AD circuit" to "a corresponding receiving port of an ADC circuit can recognize the sampling completion indication signal".

In some application scenarios, the two delay factors are negligible, in other words, the following process is described on the premise that "the sampling trigger signal of the next channel is synchronously generated at the sampling completion time of the previous channel". That is, the system will generate the channel sampling trigger signal (i ≧ 2) of the ith channel while the sampling and conversion of the (i-1) th channel is completed. Therefore, during the sampling and conversion process of the ith channel, the updating process of the incremental accumulator is as follows:

(1) In relative count mode, increment from 1 to n by + 1;

(2) In absolute count mode, start with "A +1+ (i-2) × n" and increment +1 to "A + (i-1) × n".

It can be seen that in the relative count mode, the achievable maximum value of the incremental accumulator is a or n, whichever is, which is relatively the smaller achievable maximum value, and therefore the circuit scale of the incremental accumulator and the sampling time register unit can be made to a relatively small level. In the absolute count mode, the maximum value of the incremental accumulator that can be counted is obviously much larger, so the circuit scale of the incremental accumulator and the sampling time register unit must be relatively large.

The sampling time, i.e. the capture value of the sampling time register unit, which is one of the final conversion results, must be accessed by the MCU system in pairs together with the contents of the conversion results in the method provided by the present invention; obviously, the increase of the circuit scale of the sampling time register unit inevitably increases the access data volume of the MCU system, which may reduce the overall performance of the AD and subsequent analysis processing.

It can be seen that in some specific environment situations, the relative counting mode is adopted for the incremental accumulator, which is beneficial to improve the system processing performance in the aspect of accessing the sampling time from the sampling time register unit. In other environment occasions, the incremental accumulator adopts an absolute counting mode, so that the MCU system can omit software operation for calculating the absolute starting time based on the relative completion time consumption, and the overall system processing performance is improved under the environment.

Fig. 5 is a schematic diagram of the analog-to-digital conversion process in a conventional motor closed-loop automatic control system.

The automatic control system is a management system which is composed of a control subject, a control object and a control medium and has own target and function, wherein the management system automatically controls certain critical parameters in production so that the critical parameters can be automatically adjusted to return to a value range required by the process when the critical parameters deviate from a normal state due to the influence of external interference.

Automatic control systems are generally divided into open-loop and closed-loop control systems, and closed-loop control is usually selected in motor drive control applications with high control precision requirements. The system of the so-called closed-loop control, namely (negative) feedback control, comprises a detection device, a control device, an actuator and a controlled object. The detecting device detects certain state information (output quantity) of the controlled object, converts the state information into a physical signal (generally an analog electric signal), and transmits the physical signal to the control device. The control device compares the deviation of the current state (output quantity) of the controlled object to the expected state (reference quantity), generates a group of control signals, and drives the controlled object to move through the actuating mechanism so that the moving state of the controlled object is close to the expected state.

In the above description, particularly in the application environment of motor control, the components of the closed-loop control system are generally mapped as: detection means = feedback detection circuit (e.g. with hall position sensor), control means = motor control MCU system (chip) (containing circuit sub-modules responsible for analog-to-digital conversion processing and PWM waveform signal generation), actuator = electrode power amplification driving circuit, controlled object = motor body, i.e. the (brushless dc) electrodes in the figure.

In order to achieve a closed-loop control of the brushless dc motor, and thus an automated intelligent control of its rotational speed + angular position + rotational torque (torque for short), in one embodiment such a motor control system as shown in fig. 5 may be implemented. It is noted that in the application where the requirement for control accuracy is high, it is a major business difficulty in the motor control industry to drive the motor to generate a smoother torque (even if the torque ripple is as small as possible). To overcome this difficulty, the MCU system usually adopts the feedback algorithm called PID and FOC for short to control the motor more finely. The precondition for effective development of these feedback algorithms is that the motor control MCU system obtains correct and sufficiently fine corresponding feedback information.

In a common brushless direct current motor body with stator winding coils arranged in a Y shape, three stator windings arranged at intervals of 120 degrees on the outer ring are generally referred to as three phases for short; the armature magnetic field can be generated by controlling the existence and the direction of the current (namely, the armature current) flowing in the coil, so that the armature magnetic field and the permanent magnet of the inner ring of the motor form a magnetic field attraction or repulsion effect, and the motor rotating shaft coaxially bound with the permanent magnet of the inner ring can be driven to rotate. In the "two-conduction" configuration scenario known in the motor industry, only two of the three-phase stator winding coils may be in a conducting state (referred to as "conducting phase") and the remaining one in a non-conducting state (referred to as "non-conducting phase") during the same short time window. If the conducting phases are A and B and the non-conducting phase is C in a certain time window, whether current passes through a winding coil of the A + B two phases or not and the positive and negative directions of the current can be controlled by a circuit model such as 'two half-bridges share 4N-type MOS tubes'; and for the C phase, 2N-type MOS tubes in a half bridge are kept in a closed state even if no current passes through the winding coil.

For three half-bridges of a + B + C three phases, which have 6N-type MOS transistors, the current motor usually employs a PWM modulation-based control technique to control the presence or absence and direction of the source-drain two-stage applied voltage of the MOS transistor on the microscopic level, so as to control the presence or absence and direction of the aforementioned conducting phase armature current. In a common six-step PWM modulation scheme, a revolution of the motor shaft through 360 ° is divided into six sectors of 60 ° each; during the single-step 60 modulation period, the selection of two conducting phases and one non-conducting phase is maintained, so that the motor shaft is continuously driven to rotate 60 degrees in the given direction. When the rotating shaft rotates to the vicinity of the dividing point of the sector, the combination of the conducting phase and the non-conducting phase (for example, originally, C is the non-conducting phase, a + B is the conducting phase, and after the change, B is the non-conducting phase, a + C is the conducting phase) must be changed to drive the rotating shaft of the motor to continue rotating in the predetermined direction, which is generally called phase change operation.

The feedback detection circuit in the motor closed-loop automatic control system can be divided into two types (inductive and non-inductive) of a position sensor and a non-position sensor. For the inductive type of feedback detection circuit, it is generally responsible for providing angular position information of the motor shaft by an additional position sensor (such as a hall element or a grating encoder). The non-inductive feedback detection circuit is desirable in some applications because it eliminates the cost and volume of the position sensor. As a cost, in a non-inductive feedback detection circuit, the zero crossing point time of the so-called back electromotive force Ea is generally required to be monitored to calculate the angular position information; to monitor the back electromotive force Ea, the armature currents of the three phases must be monitored.

During the switching process of the phase-change operation, also because of the existence of the back electromotive force, an "excitation current component having an effect opposite to that of the original armature current component" is formed in the coil of the conducting phase winding (note: this description is only a simple understanding), so that the armature current of the conducting phase does not reach the original ideal level, which is expressed as a relatively short-term drop jitter, that is, a so-called motor torque ripple, on the formed motor torque waveform diagram.

In order to compensate the torque fluctuation in the phase commutation process and to make the torque waveform smooth to the maximum extent, and based on the consistent idea of a closed-loop automatic control system, the deviation between the current state of the armature current of the controlled object (motor body) and the expected state of the armature current expected by the system needs to be known by a control device (motor control MCU system) in real time, so that the control device can simulate the armature current with a sine waveform and added with compensation components in a direct current circuit system on a macroscopic level based on a PWM signal with constant voltage amplitude and real-time modulation of conduction duty ratio.

To obtain the armature current deviation, the more accurate and better current state of the armature current must be obtained, which leads to the necessity of implementing high-precision analog-to-digital conversion and subsequent analysis processing in the motor control MCU system. In addition, the armature current deviation is calculated, and is definitely calculated based on the current state and the expected state of a certain single-phase current at the same target time; therefore, if an error on the time axis (for example, comparing the desired state at time t1 with the current state at time t 2) occurs and the error exceeds a certain threshold, it is difficult to achieve the desired control effect of reducing the torque ripple by controlling the generated PWM signal by the closed-loop feedback control algorithm. Therefore, the implementation of the analog-to-digital conversion and the subsequent analysis process must ensure high precision of the sampling process and low error degree of the analysis process.

It can be seen from the embodiment of fig. 5 that, by using the analog-to-digital converter of the present disclosure, a time error when the motor outputs each phase of armature current and is detected and obtained by the motor control MCU system can be effectively avoided in the motor closed-loop automatic control system under a non-inductive configuration environment.

Fig. 6 and 7 are schematic diagrams of the present disclosure in which the injection packet sampling and transfer processing queue is inserted in the middle of the normal packet sampling and transfer in the absolute and relative counting modes, respectively.

In one embodiment, the three-phase armature current analog signal output by the motor may be mapped into 3 or 6 input channels of a conventional packet (depending on whether the current signal is single-ended or differential), while the reference voltage signal internal to the MCU system is mapped into 1 channel of an injected packet. Therefore, when the three-phase armature current signal is analog-to-digital converted through the conventional channel, it is usually impossible to predict when the AD conversion application for the internal reference voltage signal will be issued, so that the possibility arises that the conversion process of a conventional channel and the remaining channels after the conventional channel is dragged due to the conversion processing queue of the injection channel and is not known by the MCU system.

A detailed explanation of the above possible solution can be developed with specific embodiment circuit logic as shown in fig. 6 and 7. The essential difference between fig. 6 and fig. 7 is that the incremental accumulator is an update change in absolute and relative count modes, respectively.

As shown in fig. 6, it is assumed that a global acquisition trigger signal of a normal packet is generated in the system at time t1 on the time axis, and it is expected that the armature current signals of the UVW three phases are continuously AD-processed in the order of U → V → W → 8230on the basis of the channels of the normal packet in terms of application. Further assume that, after a delay of Δ (a) has elapsed since time t1, the packet/channel arbitration control unit 12 generates a first channel sampling trigger signal (at time t 2); at this point, the corresponding incremented accumulator has been incremented to a, so this a value (when the channel sample trigger signal is active) is captured and stored in the sample time register unit that is specific to the conventional packet.

After time t2, the first conventional channel (labeled RG # 1), gated according to a preprogrammed sequencing or priority setting, begins its acquisition and transfer process. On the common premise that the sampling principle and resolution of the AD circuit 2 are constant, the sampling completion time of a single AD process for a single channel is constant, and if the value is n (the unit is 1 ADC clock cycle, the same applies below), the AD circuit 2 outputs the current content of the AD sampling result when the incremental accumulator updates to the (a + n) value; at the same time, a channel sampling trigger signal for the RG #2 channel is also generated (at time t 3; note: as described above, the sampling trigger signal for the next channel can be generated immediately, assuming that the sampling transition of the current channel is completed); therefore, at this time, the real-time value (a + n) of the incremental accumulator is captured and stored in the same sample time register unit.

After time t3, and similar to the above, the second conventional channel (labeled RG # 2) begins its sampling process, which completes and outputs the conversion result (at time t 4) when the incremental accumulator updates to the (a +2 n) value; at the same time, a channel sampling trigger signal for the RG #3 channel is also generated; therefore, at this time, the real-time value (a +2 n) of the incremental accumulator is captured and stored in the same sample time register unit.

After time t4, the third conventional channel (labeled RG # 3) begins its acquisition process, similar to that described above. However, unlike the above, at time t5 before this AD process is not completed, there is suddenly an injection packet global acquisition trigger signal inserted with a higher priority. The injection global trigger signal is detected by the packet/channel arbitration control unit 12, and then skips to perform the acquisition and transfer processing control of the injection packet after the acquisition and transfer processing of the RG #3 channel is completed. Note that for both embodiments shown in FIGS. 6 and 7, this time window of { t5-t6} represents: a time delay from the generation of the above-mentioned injection global trigger signal to the time when the first injection channel sampling trigger signal is generated.

Assuming that the injected packet in the embodiment shown in fig. 6 corresponds to a sampling application of two injected channels, similarly to the above, the packet/channel arbitration control unit 12 recognizes that the two channel sampling trigger signals at times t6 and t7 do not belong to a normal packet, and thus the real-time values of the incremental accumulators at the above two times are not captured and stored in the sampling time register unit specific to the normal packet in the absolute count mode.

At time t8, the packet/channel arbitration control unit 12 finds that all channels injected with packets have completed sampling processing, so it immediately (and with possibly some delay, as described above) resumes sampling processing control of the next channel of the conventional packet (i.e., RG # 4) that was interrupted previously, i.e., generates a channel sampling trigger signal for RG # 4. Then, the switching process of RG #4, RG #5, \ 8230, and other remaining conventional channels is completed in the time window of t8-t9, t9-t10, and \8230. Assuming that the real-time value of the incremental accumulator is C at time t8, the real-time values C, C + n, \ 8230; etc. of the incremental accumulator at time t8, t9, \ 8230, etc. are captured and registered in the same sampling time register unit, similar to the above.

Comparing fig. 6 and 7, also with reference to the above-mentioned definition differences between the absolute counting mode and the relative counting mode, it is apparent from fig. 7 that: in the relative count mode, the incremental accumulator should be initialized to a zero value (1 in fig. 7) at the time of each conventional channel sampling trigger signal generation, rather than a continuous incremental accumulation as in the absolute count mode.

As shown in fig. 6, at the sampling processing completion time of the conventional channels such as t3, t4, t6, t9, t10 in the absolute count mode, the real-time values (i.e., a + n, a +2n, C + n) of the sampling time register units are exactly the corresponding sampling start time values of these conventional channels.

As shown in fig. 7, at the sampling and rotation processing completion time of the conventional channels such as t3, t4, t6, t9, t10, etc. in the relative counting mode, the accumulated result of the real-time values of the sampling time register unit (i.e. a, a + n, a +2n, a +2n + b, a +3n + b) is exactly the corresponding sampling start time value of these conventional channels.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (8)

1. An analog-to-digital converter, comprising:

the channel multiplexing selection unit is used for determining a target channel to be subjected to AD processing and a target analog signal corresponding to the channel to be subjected to AD processing from a plurality of input channels based on at least one input analog signal and at least one channel selection signal corresponding to the analog signal, and transmitting the target analog signal to the AD circuit to perform actual analog-digital conversion processing;

the system comprises a grouping/channel control configuration unit, a channel control configuration unit and a control unit, wherein the grouping/channel control configuration unit is used for determining control configuration information according to received configuration information of an MCU system, and the control configuration information is used for carrying out configuration control on acquisition and transfer processing of different groups or channels;

the packet/channel arbitration control unit is used for determining a channel selection signal and a channel sampling trigger signal of each channel based on the received global sampling and switching trigger signal, the control configuration information and a pre-programmed processing sequence or priority rule for each channel, wherein the channel selection signal is used for making a selection instruction for the channel, and the channel sampling trigger signal is used for making a starting instruction of current AD processing for the AD circuit;

the incremental accumulator is used for carrying out incremental accumulation updating on the working clock period of each analog-to-digital converter under the driving of the working clock of the analog-to-digital converter so as to provide a time reference for capturing sampling time;

and the sampling time registering unit is used for capturing and registering a real-time value of the incremental accumulator based on the channel sampling trigger signal to serve as a sampling time, and combining the sampling time and the content of a channel conversion result and then providing the combined sampling time and the content of the channel conversion result to the MCU system.

2. The analog-to-digital converter according to claim 1,

the global sampling and conversion trigger signal is generated by other circuit logics outside the analog-to-digital converter and/or by some circuit logics inside the ADC circuit, and is used for starting sequential sampling and conversion processes of analog signals of a plurality of channels;

and when the incremental accumulator is in an absolute counting mode, the incremental accumulator is used for regarding the global sampling and rotation trigger signal as a time zero point, starting incremental accumulation from a corresponding zero point value, and returning to the zero point value when the incremental accumulator is increased to the maximum value or meets the reset of the MCU system.

3. The analog-to-digital converter according to claim 1,

and when the incremental accumulator is in a relative counting mode, the incremental accumulator is used for regarding the global sampling and rotating trigger signal and the sampling trigger signal of any channel as a time zero point, starting incremental accumulation from a corresponding zero point value, capturing a real-time value of the incremental accumulator when the next sampling and rotating is started, and returning to the zero point value.

4. The analog-to-digital converter according to claim 2, wherein the sampling time register unit is configured to represent a sampling time start time value of each channel when the incremental accumulator is in an absolute count mode.

5. The analog-to-digital converter according to claim 3, wherein the sampling time register unit is configured to represent a time-consuming value of completion of the sampling process of the latest historical channel when the incremental accumulator is in the relative count mode.

6. The analog-to-digital converter according to claim 3, wherein after a valid global sampling trigger signal occurs, the first sampling time captured by the sampling time register unit represents a time difference between the valid global sampling trigger signal and a first valid channel sampling trigger signal.

7. The analog-to-digital converter according to claim 3, wherein the MCU system is configured to calculate a sampling start time point of each channel according to the sampling time captured by the sampling time register unit.

8. The ADC of claim 3, wherein said accumulator increment, sample time register unit is in idle state without MCU system knowing sample time information of each channel.

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