CN218602073U - LED display device - Google Patents

Abstract

An LED display device comprises an LED array and a driving system thereof. The LED display device is configured such that the LEDs in the LED array can be switched between receiving a scanning signal at the anode or receiving a scanning signal at the cathode.

Description

LED display device

Technical Field

The utility model provides a LED array with crisscross topology and use crisscross LED array provides the display panel who is shaded.

Background

High end hand-held displays such as iPAD and iMac use liquid crystal displays ("LCDs") with Light Emitting Diode (LED) backlight panels. U.S. application Ser. No. 17/398,603 (US' 603), filed on 8/10/2021, describes the characteristics of an LCD display. For example, the response time of the LCD pixels is slow and are updated sequentially, resulting in a delay in updating all LCD pixels on the display. US'603 proposes a general retardation method for LCD backlighting using an array of LEDs, the entire contents of which are incorporated herein.

The LED backlight array has a large number of micro LEDs. The size of the white LED pitch may be less than 2mm. Light emitted from each LED illuminates the LCD through the diffuser. Each LCD pixel receives light not only from the LED directly behind it, but also from adjacent LEDs. This cross-talk between nearby LED pixels may lead to blooming effects.

In operation, LCD displays have different requirements for displaying different content. High speed video requires motion blur free video images, which can be achieved by the universal delay scheme disclosed in US patent application US' 918. On the other hand, when displaying still images, it is important to reduce or eliminate flicker and blooming.

To obtain a flicker free screen one can light up using high frequency leds, for example 100 hz. As long as one LED around an LCD pixel is lit frequently enough, the viewer may not see flicker. For example, in a 2x2 LED pixel group, if each LED pixel can light up once per frame, the LCD pixel located in front of the LED pixel group receives 4 separate light pulses in a frame, so that flicker can be eliminated. On the other hand, to reduce the blooming effect, it is necessary to reduce stray light from adjacent LEDs. One way to achieve the blooming effect is to allow fewer leds in a group of leds to emit light. For example, lighting only one LED in a 3 x3 or 4x4 array of LEDs will reduce blooming.

Furthermore, a screen with no motion blur requires that each frame has a short and bright pulse, and the adjacent light emitting diodes should not be lit after this short pulse period. Thus, two different schemes are required to achieve flicker-free and blur-free. It is desirable for LCD displays to be able to implement both, which requires complex driver structures and new driving schemes.

Furthermore, one of the challenges of complex LED backlight systems is that the driver chip does not have enough space to accommodate the large number of connections required to drive the LED array. Although the number of connections can be reduced by providing a plurality of LEDs with one connection, for example 12 LEDs arranged in a small 3 x4 array, this driving method does not allow control of a single LED pixel. Therefore, new methods and apparatus are needed to drive LED arrays to backlight display panels.

SUMMERY OF THE UTILITY MODEL

The present invention provides systems and methods that allow the same driver to switch between an anti-blur light scan mode that reduces vignetting and a strobe co-delay mode that reduces motion blur. In particular, the proposed system for driving an LED array has a connection pin that is switchable between a current source (or sink) and a scan line. This design is called channel scan switching and this switching device/circuit is called channel scan switch or CSS, which can drive a large LED array with a significantly smaller number of connections and achieve a highlight-free and motion blur-free display.

An LED display device comprises an LED array and a driving system thereof. The configuration of the LED display device enables the LEDs in the LED array to switch between receiving a scan signal at their anodes or at their cathodes.

According to some embodiments, the LED display device comprises at least one display cell, each cell of the at least one display cell further comprising an LED array of LxMxN LEDs driven by N cores of a channel scan switch, an anode side switching circuit for an anode side channel scan switch having MxN current source analog inputs and MxN digital scan inputs, the anode side switching circuit being switchably connected to MxN current sources and MxN scan lines; cathode side switching circuitry for a cathode side channel scan switch having MxN current sink analog inputs and MxN digital scan inputs, the cathode side switching circuitry switchably connected to MxN current sinks and MxN scan lines, first selection circuitry connected to MxN current sources and MxN scan lines, the first selection circuitry configured to select at least one current source from the MxN current sources, at least one scan line from the MxN scan lines in the anode side switching circuitry; connected to the MxN current sinks and the MxN scan lines is a second selection circuit configured to select at least one current sink from the MxN current sinks and at least one scan line from the MxN scan lines in the cathode side switching circuit.

According to some embodiments, one of the at least two modes of the controller of the LED display device is a static anti-blur scanning mode. The other of the at least two modes of the controller of the LED display device is a stroboscopic motion blur removal mode. When the first selection circuit and the second selection circuit are switched to the static anti-fuzzy scanning mode, all the anodes of the LED display device are driven by the scanning control input. When both the first selection circuit and the second selection circuit are switched to the stroboscopic motion blur removal mode, all anodes of the LED display device are driven by the current source control input. When the first selection circuit and the second selection circuit are switched to the static anti-fuzzy scanning mode, the CoreX cathodes are connected to corresponding CoreX channel current sinks in an interlaced mode. When the first selection circuit and the second selection circuit are simultaneously switched to the stroboscopic motion blur removal mode, the CoreX cathodes are interleaved to the corresponding CoreX scanning signals. When the first selection circuit and the second selection circuit are switched to the static anti-fuzzy scanning mode, all cathodes of the LED display device are driven by the current sink control input. When the first selection circuit and the second selection circuit are both switched to the stroboscopic motion blur removal mode, all cathodes of the LED display device are driven by a scanning control input. The LED display device, the LED display device common anode configuration. The LED display device, a common cathode configuration.

The utility model discloses a method for being directed at to the switchable LED display device between at least two kinds of modes and controlling. According to some embodiments, the method includes configuring at least one display cell, wherein each cell of the at least one display cell further includes an LED array of LxMxN LEDs driven by N cores of a channel scan switch, configuring an anode side switch circuit for an anode side channel scan switch having MxN current source analog inputs and MxN digital scan inputs by at least switchably connecting the anode side switch circuit with MxN current sources and MxN scan lines; configuring a cathode side switching circuit for a cathode side channel scan switch having MxN current sink analog inputs and MxN digital scan inputs by at least switchably connecting the cathode side switching circuit with MxN current sinks and MxN scan lines; a first selection circuit connected to the MxN current sources and the MxN scan lines is configured by selecting at least one current source from the MxN current sources and at least one scan line from the MxN scan lines in the anode side switching circuit, and a second selection circuit connected to the MxN current sinks and the MxN scan lines is configured by selecting at least one current sink from the MxN current sinks and at least one scan line from the MxN scan lines in the cathode side switching circuit.

According to some embodiments, the method for controlling the LED display device further comprises configuring the LED display device in a common anode configuration. The method also includes configuring the LED display devices in a common cathode configuration. The method also includes driving all anodes using the scan control input when both the first selection circuit and the second selection circuit are switched to the static anti-blooming scan mode. The method further comprises driving all anodes using the current source control input when both the first selection circuit and the second selection circuit are switched to the stroboscopic motion blur removal mode. The method also includes alternately connecting the CoreX cathodes to respective CoreX channel current sinks when both the first selection circuit and the second selection circuit are switched to the static anti-blooming scanning mode. The method further includes connecting the CoreX cathodes to respective CoreX scan signals in an interleaved manner when both the first selection circuit and the second selection circuit are switched to the strobed motion blur removal mode. The method also includes driving all cathodes using the current sink control input when both the first selection circuit and the second selection circuit are switched to the static anti-blooming scan mode. The method further includes driving all of the cathodes using the scan control input when both the first selection circuit and the second selection circuit are switched to the stroboscopic motion blur removal mode.

Drawings

The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.

Fig. 1-8 illustrate system topologies with LED arrays arranged in a common cathode configuration. In contrast, fig. 9-14B show a system topology with an array of LEDs arranged in a common anode configuration. Typically, an LED array has rows and columns of LED lamps. As used herein, an LED may refer to a white LED. However, the device and driving method of the present invention are applicable to any single color LED. In a common cathode configuration, the cathode of each LED in a row is connected to a single cathode node, which may be further connected to one or more scan switches, while the anodes of the LEDs in a channel are connected to a power supply. In contrast, in a common anode configuration, the anodes of the LEDs in a row are connected to a common power supply, while the cathodes of the LEDs in a column are connected to a current sink, such as ground or "GND".

Fig. 1 and 9 show two similar topologies, except that fig. 1 is a common cathode configuration, while fig. 9 is a common anode configuration. Similarly, fig. 2A, 2B and fig. 10A, 10B show similar structures, except that fig. 2A, 2B are in a common cathode configuration, while fig. 10A and 10B are in a common anode configuration. Likewise, fig. 3-5, 7A and 7B correspond to fig. 11-13, 14A and 14B, respectively. Components in the common anode configuration are sometimes named with the suffix "CA" or "_ CA" appended to the name of the corresponding component in the common cathode configuration.

Fig. 1 shows an embodiment of an LED array arranged in a common cathode configuration.

Fig. 2A and 2B illustrate embodiments of anode side channel scan switches on the 32x32 cores core0 through core3 in the common cathode configuration shown in fig. 1.

Fig. 3 shows an embodiment of a CSS _32x32x4 LED block in the common cathode configuration shown in fig. 1.

Fig. 4A and 4B show an embodiment of a CSS _32x4 common cathode interleaved structure.

Fig. 5 shows an embodiment of a CSS _32x1 common cathode interleaved switching element.

Fig. 6 shows an embodiment of a channel scan switch for 8 anode pins in the common cathode configuration shown in fig. 1.

Fig. 7A and 7B illustrate embodiments of cathode side channel scan switches on 32x32 cores core0 through core3 in the common cathode configuration shown in fig. 1.

Fig. 8 shows an embodiment of a channel scan switch for 8 cathode pins in the common anode configuration shown in fig. 1.

Fig. 9 shows an embodiment of an LED array arranged in a common anode configuration.

Fig. 10A and 10B illustrate embodiments of cathode side channel scan switches on 32x32 cores core0 through core3 in the common anode configuration shown in fig. 9.

Fig. 11 shows an embodiment of a CSS _32x32x4 LED block in the common anode configuration shown in fig. 9.

Fig. 12A and 12B show a common anode staggered structure.

FIG. 13 shows an embodiment of a CSS _32x1 common anode interleaved switching element.

Fig. 14A and 14B illustrate embodiments of cathode side channel scan switches on 32x32 cores core0 through core3 in the common anode configuration shown in fig. 9.

Detailed Description

The following detailed description is provided to assist the reader in a thorough understanding of the methods, apparatus, and/or systems described herein. However, various changes, modifications, and equivalents of the systems, devices, and/or methods described herein will be apparent to those of ordinary skill in the art. For example, the terms "connect" and "pin" are used interchangeably throughout this specification and both refer to and/or on a physical link between two devicesA point. "driver chip" and "driver circuit" may be used interchangeably. In addition, I _source ("Isrouce") refers to a current source, and I _sink ("Isink") refers to the current sink in the driver circuit. "scan" or "scan line" both refer to a scan line in a driver circuit. The term "core" as used herein refers to a driver circuit disposed on a driver chip. A driver chip may have one or more cores.

Detailed Description

The features described herein may be embodied in different forms and should not be construed as limited to the examples set forth herein. Rather, the examples described herein are shown to complete the disclosure and to convey the full scope of the disclosure to those skilled in the art.

Fig. 1 shows three interconnected blocks, an LxMxN LED array block 1200, an anode block 1100 (CSSP _ LxMxN) with 128 anode pins, a cathode block 1300 (CSSN _ LxMxN) with 128 cathode pins connected to the LED array block 1200 (CSS _ LxMxN). According to some embodiments, L = M, according to other embodiments, L ≠ M. In the example of fig. 1, L = M =32,n =4. The drive system 1000 also includes a controller 1400 (CSS _ SEL), a voltage supply (VCC), and Ground (GND).

The anode block 1100 has 32x4 current source analog inputs and 32x4 digital scan inputs. For example, 32 × 4 current source analog inputs are as follows: isource0<31 >, isource1<31 >, isource2<31 >, isource3<31 >; isource0<30 >, isource1<30 >, isource2<30 >, isource3<30 >; isource0<29 >, isource1<29 > and Isource2<29 > and Isource3< 29; \8230: [ 8230 ] <1 ], isource1< 1>, isource2< 1> and Isource3< 1; isource0< 0>, isource1< 0>, isource2< 0>, isource3< 0>.32x4 digital SCAN inputs are SCAN _ P0<31 >, SCAN _ P1<31 >, SCAN _ P2<31 > and SCAN _ P3<31 > respectively; SCAN _ P0<30 >, SCAN _ P1<30 >, SCAN _ P2<30 > and SCAN _ P3<30 >; SCAN _ P0<29 >, SCAN _ P1<29 >, SCAN _ P2<29 > and SCAN _ P3<29 >; \8230The \8230, SCAN _ P0< 1>, SCAN _ P1< 1>, SCAN _ P2< 1> and SCAN _ P3< 1; SCAN _ P0< 0>, SCAN _ P1< 0>, SCAN _ P2< 0>, SCAN _ P3< 0>.

The cathode block 1300 is a cathode side channel switch block having 32x4 current sink analog inputs and 32x4 digital scan inputs. 32x4 current sink analog inputs, respectively: isink0<31 >, isink1<31 >, isink2<31 >, isink3<31 >; isink0<30 >, isink1<30 >, isink2<30 >, isink3<30 >; isink0<29 >, isink1<29 >, isink2<29 >, isink3<29 >; \8230 \ 8230

Isink0< 1>, isink1< 0>, isink2< 1>, isink3<1 >; isink0< 0>, isink1< 0>, isink2< 0>, isink3< 0>. The 32x4 digital SCAN inputs are SCAN _ N0<31 >, SCAN _ N1<31 >, SCAN _ N2<31 >, SCAN _ N3<31 > respectively; SCAN _ N0<30 >, SCAN _ N1<30 >, SCAN _ N2<30 > and SCAN _ N3<30 >; SCAN _ N0<29 >, SCAN _ N1<29 >, SCAN _ N2<29 > and SCAN _ N3<29 >; \8230: [ 8230 ], [ SCAN _ N0< 1> and [ SCAN _ N1< 0>, SCAN _ N2< 1> and [ SCAN _ N3<1 ]; SCAN _ N0< 0>, SCAN _ N1< 0>, SCAN _ N2< 0>, SCAN _ N3< 0>.

The driving apparatus 1000 includes an LED array block 1200 having 32 × 128 (i.e., 32 × 32 × 4=4, 096) LEDs, driven by 4 cores of a channel scan switching circuit, each core driving 32 × 32 (32 channel × 32 scan lines) matrices. The LED array block 1200 includes 128 virtual cathode pins, and there are a total of 256 pins to drive 32 × 32 × 4=4096 LEDs.

The controller 1400 is a relay circuit. As described below, the relay circuit 1400 is capable of switching between a static anti-blur scan mode (referred to as "scan mode" for short) and a strobe co-delay mode (or a strobe motion blur removal mode, referred to as "strobe mode" for short). According to an embodiment of the present invention, when CSS _ SEL =1, the drive device 1000 is switched to the scanning mode; when CSS _ SEL =0, the driving apparatus 1000 switches to the strobe mode. This configuration allows the anode pin of the anode block 1100 to be switched between a state connected to a current source (e.g., isource0<31 >, isource1<31 >, isource2<31 > 0, isource3<31 > 0, etc.) and a state connected to a SCAN line (e.g., SCAN _ P0<31, SCAN _ P1<31, SCAN _ P2<31 > 0, SCAN _ P3< 31. Likewise, the cathode pin of the cathode block 1300 is switchably connected to a current sink (e.g., isink0<31 >, isink1<31 >, isink2<31 >, isink3<31 >; etc.) and a SCAN line (SCAN _ N0<31, SCAN _ N1<31 >, SCAN _ N2< 0>, SCAN _ N3<31, etc.). The switching action is properly timed, thus requiring 256 pins to drive 4,096 LED arrays in both scan mode and flash mode. Thus, when each pin is designated to receive either a digital scan signal or an analog current signal, each pin has two functions, thereby reducing the number of pins to half that required in conventional designs.

Fig. 2A and 2B show details of the anode-side CSS control block 1100 of fig. 1. Anode block 1100 or anode side CSS control block 1100 has 4 cores of 32x32 anode side channel scan switches, core0 being designated 2100, core1 being designated 2200, core2 being designated 2300, and core3 being designated 2400, as shown in fig. 2B. Each of the four cores core0 to core3 has substantially the same structure. For example, in FIG. 2A, the first core0,2100 includes a set of 32 digital SCAN inputs SCAN _ P0<31 > to SCAN _ P0< 0>; a set of 32 analog current source control inputs: isource0<31 > to Isource0< 0>; and a set of 32 anode outputs: core0_ Anode <31 > to Core0_ Anode < 0>; they are divided into four subunits 2110, 2120, 2130 and 2140, respectively.

Each subunit 2110 to 2140 includes 8 analog current source control inputs IsourceX < m: n >, where, for example, X =0,1,2,3, m =0-31, n =0-31,8 digital SCAN inputs SCAN _ PX '< m': n '>, where, for example, X' =0,1,2,3, m '=0-31, n' =0-31, and 8 Anode outputs CoreX "_ Anode < m": n ">, each of the 8 analog current source control inputs IsourceX < m: n > of each subunit 2110 to 2140 is connected to any one of the 32 current sources Isource0< 31. Any one of the 8 digital SCAN input signals SCAN _ PX ' < m ': n ' > of each of the sub-units 2110 to 2140 is connected to any one of the 32 SCAN inputs SCAN _ P0<31 >. Each of the sub-units 2110 to 2140 has 8 anode pins, and a total of 32 anode pins are provided in Core0 for connection to the LED array block 1200. All the sub-units 2110 to 2140 are connected to a voltage supply VCC, a current sink GND and an input pin SEL.

The core 2200, the core 2300, and the core 2400 are substantially the same in structure as the core 2100. For example, the input/output of Core1 2200 is correspondingly named Isource1<31 >, SCAN _ P1<31 > and Core1_ Anode <31 > 0. The input/output of Core2 2300 is correspondingly named Isource2<31 >, SCAN _ P2<31 > and Core2_ Anode <31 > 0. For example, the input/output of Core3 2400 is correspondingly named Isource3<31 >, SCAN _ P3<31 > and Core3_ Anode <31 > 0.

To reduce halo, the digital scan inputs are arranged in the manner outlined in table 1 below to illuminate only one LED of the 32 adjacent LED groups in the LED array block 1200 at any given time. In strobe mode, all nodes are driven by current source control inputs. The Anode pin connection sequence is the same as the current source sequence, i.e. CoreX "_ Anode <31 > = IsourceX <31 >.

In the scan mode, the LED anode is driven by a scan control input. The assignment of anode pins in scan mode is detailed below, and table 1 in this patent application.

Core0 static anti-blur scan pin assignment:

Core0_Anode<31>＝SCAN_P0<31>

Core0_Anode<30>＝SCAN_P0<15>

Core0_Anode<29>＝SCAN_P0<23>

Core0_Anode<28>＝SCAN_P0<7>

Core0_Anode<27>＝SCAN_P0<30>

Core0_Anode<26>＝SCAN_P0<14>

Core0_Anode<25>＝SCAN_P0<22>

Core0_Anode<24>＝SCAN_P0<6>

Core0_Anode<23>＝SCAN_P0<29>

Core0_Anode<22>＝SCAN_P0<13>

Core0_Anode<21>＝SCAN_P0<21>

Core0_Anode<20>＝SCAN_P0<5>

Core0_Anode<19>＝SCAN_P0<28>

Core0_Anode<18>＝SCAN_P0<12>

Core0_Anode<17>＝SCAN_P0<20>

Core0_Anode<16>＝SCAN_P0<4>

Core0_Anode<15>＝SCAN_P0<27>

Core0_Anode<14>＝SCAN_P0<11>

Core0_Anode<13>＝SCAN_P0<19>

Core0_Anode<12>＝SCAN_P0<3>

Core0_Anode<11>＝SCAN_P0<26>

Core0_Anode<10>＝SCAN_P0<10>

Core0_Anode<9>＝SCAN_P0<18>

Core0_Anode<8>＝SCAN_P0<2>

Core0_Anode<7>＝SCAN_P0<25>

Core0_Anode<6>＝SCAN_P0<9>

Core0_Anode<5>＝SCAN_P0<17>

Core0_Anode<4>＝SCAN_P0<1>

Core0_Anode<3>＝SCAN_P0<24>

Core0_Anode<2>＝SCAN_P0<8>

Core0_Anode<1>＝SCAN_P0<16>

Core0_Anode<0>＝SCAN_P0<0>.

core1 static anti-blur scan pin assignment:

Core1_Anode<31>＝SCAN_P0<25>

Core1_Anode<30>＝SCAN_P0<9>

Core1_Anode<29>＝SCAN_P0<1>

Core1_Anode<28>＝SCAN_P0<17>

Core1_Anode<27>＝SCAN_P0<24>

Core1_Anode<26>＝SCAN_P0<8>

Core1_Anode<25>＝SCAN_P0<0>

Core1_Anode<24>＝SCAN_P0<16>

Core1_Anode<23>＝SCAN_P0<23>

Core1_Anode<22>＝SCAN_P0<7>

Core1_Anode<21>＝SCAN_P0<31>

Core1_Anode<20>＝SCAN_P0<15>

Core1_Anode<19>＝SCAN_P0<22>

Core1_Anode<18>＝SCAN_P0<6>

Core1_Anode<17>＝SCAN_P0<30>

Core1_Anode<16>＝SCAN_P0<14>

Core1_Anode<15>＝SCAN_P0<21>

Core1_Anode<14>＝SCAN_P0<5>

Core1_Anode<13>＝SCAN_P0<29>

Core1_Anode<12>＝SCAN_P0<13>

Core1_Anode<11>＝SCAN_P0<20>

Core1_Anode<10>＝SCAN_P0<4>

Core1_Anode<9>＝SCAN_P0<28>

Core1_Anode<8>＝SCAN_P0<12>

Core1_Anode<7>＝SCAN_P0<19>

Core1_Anode<6>＝SCAN_P0<3>

Core1_Anode<5>＝SCAN_P0<27>

Core1_Anode<4>＝SCAN_P0<11>

Core1_Anode<3>＝SCAN_P0<18>

Core1_Anode<2>＝SCAN_P0<2>

Core1_Anode<1>＝SCAN_P0<26>

Core1_Anode<0>＝SCAN_P0<10>.

core2 static anti-blur scan pin assignment:

Core2_Anode<31>＝SCAN_P0<19>

Core2_Anode<30>＝SCAN_P0<3>

Core2_Anode<29>＝SCAN_P0<11>

Core2_Anode<28>＝SCAN_P0<27>

Core2_Anode<27>＝SCAN_P0<18>

Core2_Anode<26>＝SCAN_P0<2>

Core2_Anode<25>＝SCAN_P0<10>

Core2_Anode<24>＝SCAN_P0<26>

Core2_Anode<23>＝SCAN_P0<17>

Core2_Anode<22>＝SCAN_P0<1>

Core2_Anode<21>＝SCAN_P0<9>

Core2_Anode<20>＝SCAN_P0<25>

Core2_Anode<19>＝SCAN_P0<16>

Core2_Anode<18>＝SCAN_P0<0>

Core2_Anode<17>＝SCAN_P0<8>

Core2_Anode<16>＝SCAN_P0<24>

Core2_Anode<15>＝SCAN_P0<15>

Core2_Anode<14>＝SCAN_P0<31>

Core2_Anode<13>＝SCAN_P0<7>

Core2_Anode<12>＝SCAN_P0<23>

Core2_Anode<11>＝SCAN_P0<14>

Core2_Anode<10>＝SCAN_P0<30>

Core2_Anode<9>＝SCAN_P0<6>

Core2_Anode<8>＝SCAN_P0<22>

Core2_Anode<7>＝SCAN_P0<13>

Core2_Anode<6>＝SCAN_P0<29>

Core2_Anode<5>＝SCAN_P0<5>

Core2_Anode<4>＝SCAN_P0<21>

Core2_Anode<3>＝SCAN_P0<12>

Core2_Anode<2>＝SCAN_P0<28>

Core2_Anode<1>＝SCAN_P0<4>

Core2_Anode<0>＝SCAN_P0<20>.

core3 static anti-blur scan pin assignment:

Core3_Anode<31>＝SCAN_P0<13>

Core3_Anode<30>＝SCAN_P0<29>

Core3_Anode<29>＝SCAN_P0<21>

Core3_Anode<28>＝SCAN_P0<5>

Core3_Anode<27>＝SCAN_P0<12>

Core3_Anode<26>＝SCAN_P0<28> Core3_Anode<25>＝SCAN_P0<20> Core3_Anode<24>＝SCAN_P0<4> Core3_Anode<23>＝SCAN_P0<11> Core3_Anode<22>＝SCAN_P0<27> Core3_Anode<21>＝SCAN_P0<19> Core3_Anode<20>＝SCAN_P0<3> Core3_Anode<19>＝SCAN_P0<10> Core3_Anode<18>＝SCAN_P0<26> Core3_Anode<17>＝SCAN_P0<18> Core3_Anode<16>＝SCAN_P0<2> Core3_Anode<15>＝SCAN_P0<9> Core3_Anode<14>＝SCAN_P0<25> Core3_Anode<13>＝SCAN_P0<17> Core3_Anode<12>＝SCAN_P0<1> Core3_Anode<11>＝SCAN_P0<8> Core3_Anode<10>＝SCAN_P0<24> Core3_Anode<9>＝SCAN_P0<16> Core3_Anode<8>＝SCAN_P0<0> Core3_Anode<7>＝SCAN_P0<7> Core3_Anode<6>＝SCAN_P0<23> Core3_Anode<5>＝SCAN_P0<15> Core3_Anode<4>＝SCAN_P0<31> Core3_Anode<3>＝SCAN_P0<6> Core3_Anode<2>＝SCAN_P0<22> Core3_Anode<1>＝SCAN_P0<14> Core3_Anode<0>＝SCAN_P0<30>.

the 32 pins in each CoreX "_ Anode <31 > are connected to a matrix of 32x32 LEDs, only one pin at a time receiving the scan digital signal, so that only one of the 32 LEDs is illuminated at any given time, thereby reducing vignetting.

Fig. 3 illustrates an embodiment of an LED array block 1200 in the common cathode configuration shown in fig. 1. It comprises 32x4 sub-blocks CSS _32x4, namely 3001, 3002, \ 8230;, 3031 and 3032, 128 anode pins from 4 cores (2100, 2200, 2300 and 2400) are connected to each sub-block in a staggered manner, 4 cathode pins (4 cores from CSSN _32x32x4, respectively) are connected to each sub-block, for a total of 128 cathode pins. Note that "staggered manner", "staggered" or "staggered" refers to an arrangement in which a plurality of connections are assigned to a group of receiving means out of order, rather than being arranged in a continuous manner. For example, four pins A, B, C, D would be connected to lines 1-16 arranged side by side in a sequence of 4 lines per pin. Pin a may be connected to lines 1-4, pin B to lines 5-8, pin C to lines 9-12, and pin D to lines 13-16. In a staggered manner, pin a may be connected to lines 1, 5, 9, 13, pin B to lines 2, 6, 10, 14, pin C to lines 3, 7, 11, and 15, and pin D to lines 4, 8, 12, and 16. As shown in fig. 3, each of 32 Anode outputs of Core0_ Anode <31 > is connected to any one row of each of the subblocks 3001 to 3032.

In the cathode side strobe common delay mode, the CoreX cathodes are interleaved with the CoreX scan signal. In the cathode side static reactance blurring scanning mode, the CoreX cathode is connected with the CoreX channel current sink signals in an interleaving mode.

The CSS-32 x4 common cathode channel scan switch array comprises 32 blocks of 32x4 interleaved sub-arrays. The same anodes of each block are connected together by a total of 128 connection points. Each block has four cathode pins, with different cathodes interleaved driven by different magnetic cores. A total of 128 cathode connections are used to drive a total of 32 blocks. Thus, the entire LED array includes a total of 4096 LEDs controlled by a total of 256 signals.

Fig. 4A shows an example of base LED array 4100 (CSS _32x 1), and fig. 4B shows four base LED arrays 4100, 4200, 4300, and 4400. The base LED arrays have substantially the same structure. Fig. 4A shows further details of the sub-block 3001 of fig. 3. Base LED array 4100 has 32 rows of LEDs receiving 32 anode inputs, each of the 8 inputs from core0-3_anode, forming a total of 32 anode connections, AR0_0, AR1_0, AR2_0, AR3_0, AR0_1, AR1_1, AR2_1, AR3_1, and as.

Further, as shown in fig. 4A, the base LED array 4100 is connected to 4 cathode pins: cathode 0, cathode 1, cathode 2, and cathode 3. In practice, each base LED array, i.e. 4100, 4200, 4300 and 4400, is connected to a cathode lead: cathode 0, cathode 1, cathode 2, and cathode 3, as shown in fig. 4B.

Fig. 5 shows an embodiment of the base LED array shown in fig. 4A or 4B, consisting of 32 LEDs arranged in 4 rows, i.e. rows 5100, 5200, 5300 and 5400. In each row, 8 LEDs are arranged, with 8 anode connections and one common cathode connection. Specifically, the 8 anodes of the 8 LEDs in the first row 5100 receive AR0_0, AR0_1, AR0_2, AR0_3, AR0_4, AR0_5, AR0_6, and AR0_7, respectively, from Core0_ Anode, while the common cathode of the 8 LEDs in the first row 5100 is cathode 0. The 8 anodes of the 8 LEDs in the second row 5200 receive AR1_0, AR1_1, AR1_2, AR1_3, AR1_4, AR1_5, AR1_6, and AR1_7, respectively, from Core1_ ANode, while the common cathode of the 8 LEDs in the second row 5200 is cathode 1. The 8 anodes of the 8 LEDs in the third row 5300 receive AR2_0, AR2_1, AR2_2, AR2_3, AR2_4, AR2_5, AR2_6, and AR2_7, respectively, from Core3_ Anode, while the common cathode of the 8 LEDs in the third row 5300 is cathode 2, and so on. In the above driving circuits of the CSSP _32x32x4 block 1100 and the CSSN _32x32x4 block 1300 shown in fig. 1, the quad control signals implement the scan mode and the flash mode operations through the channel scan switches.

In other words, one base LED array is arranged in 4 rows 5100, 5200, 5300 and 5400, each row having 8 LEDs, e.g., AR0_0 to AR0_7 in the first row 5100, AR1_0 to AR1_7 in the second row 5200, AR2_0 to AR2_7 in the third row 5300, AR3_0 to AR3_7 in the fourth row 5400. The cathodes of the LEDs in each row are connected to a common cathode pin, for example cathode 0 to cathode 4. The anodes of the LEDs in four rows (designated as Anode rows ARX _ Y, X =0,1 or 3, Y = 0-7) are connected to four different Anode cores, namely Core0 \ u Anode, core1_ Anode, core2_ Anode, core3_ Anode, in an interleaved manner. The anodes of the first row of LEDs (AR 0_ Y) are connected to Core0_ Anode <0-7>; anodes of the second row of LEDs (AR 1_ n) are connected to Core1_Anode & lt 0-7>; anodes of LEDs (AR 2_ n) in a third row are connected to Core2 u Anode & lt 0-7>; and the Anode of the fourth row of LEDs (AR 3_ n) is connected to Core3_ Anode <0-7>.

Similarly, the other three base LED arrays in the sub-arrays of FIGS. 4A and 4B are connected to CoreX <8-15>, coreX <16-23>, and CoreX <23-31>, respectively. In strobe mode, cathodeX is driven by the cathode CoreX Scan signal (Scan _ NX <31 >), while anode ARX _ Y is driven by a corresponding current source IsourceX <31 >. In Scan mode, cathodeX is driven by the cathode CoreX current sink (IsinkX <31 >), while ARX _ Y is driven by the anode CoreX Scan signal (Scan _ PX <0 >).

Fig. 6 shows details of the anode-side sub-block CSSP _ AD8X1 6000 connected between VCC and CSSP _32X 4. CSSP _ AD8x1 includes 8 AD modules 6001, 6002, \8230;, 6007, and 6008. Each of the 8 anode pins (P _0 to P _ 7) of the AD modules 6001-6008 is connected to the same voltage supply VCC. Each also connected to a respective analog input a _ IN and digital input D _ IN. The SEL input pin enables the output of the submodule to select between an analog current source and a digital scan signal. Only one of the analog input and the digital input is connected to the anode pin at any given time. According to one embodiment, the anode-side sub-block CSSP _ AD8x1 6000 is a part of the anode-side channel scanning switch block 1100 shown in fig. 1, where VCC is connected to VCC of the anode-side channel scanning switch block 1100, and SEL is connected to CSS _ SEL of the controller 1400.

Fig. 7A and 7B show details of the cathode side channel switch block 1300 shown in fig. 1. Block 1300 contains 4 cores, 7100, 7200, 7300, and 7400 of a 32x32 cathode side channel scan switch. Each core includes four subunits. As shown in fig. 7A, the first core 7100 includes four subunits 7110, 7120, 7130, and 7140. Each core receives 32 digital scan input signals, 32 analog current sink control input signals, and 32 cathode output signals. Since the anode block 1100 enables the scan exchange arrangement to perform an anti-blur function, the digital scan sequence is identical to the current sink signal sequence. The configuration of the four cores 7100, 7200, 7300, and 7400 reflects the configuration of the four cores 2100, 2200, 2300, and 2400 as shown in FIG. 2B. By analogy, the configuration of the sub-units 7110, 7120, 7130, and 7140 is also a mirror image of the configuration of the sub-units 2110, 2120, 2130, and 2140 as shown in fig. 2A, with some important differences.

In cathode side channel scan switch block 1300 shown in fig. 7A and 7B, there are four cathode cores 7100, 7200, 7300, and 7400. Each core is connected to 32 current sinks IsinkX <0>, 32 Cathode Scan lines Scan _ PX <0> and 32 Cathode pins via CoreX _ Cathode <31 >. In scan mode, all cathodes are driven by the current sink control input. The Cathode connection sequence is identical to the current sink sequence, i.e. CoreX _ Cathode <31 > = IsinkX <31 >. In strobe mode, all cathodes are driven by the scan control input, and the Cathode connection sequence is the same as the scan sequence, i.e. CoreX _ Cathode <31 > = ScanX <31 >.

Fig. 8 shows an example of a channel scan switch CSSN _ AD8x1 8000 for 8 cathode pins in the common anode configuration shown in fig. 1. Fig. 8 shows how the cathode pins are switched between scan mode and flash mode. The channel scan switch for the 8 cathode pins includes 8 AD blocks 8001, 8002, \8230; \8230, 8007, and 8008. Each of the 8 cathode pins (N _0 to N _ 7) of the AD blocks 8001-8008 is connected to ground GND and to an analog input a _ IN and a digital input D _ IN. Only one of the analog input and the digital input is connected to the anode pin at any given time. Fig. 8 shows how the cathode pins (N _0 to N _ 7) are switched from receiving the digital scan input D _ IN and receiving the analog channel current sink input a _ IN. According to one embodiment, the cathode side sub-block CSSN _ AD8x1 8000 is a part of the cathode side channel scanning switch block 1300 shown in fig. 1, wherein GND is connected to GND of the cathode side channel scanning switch block 1300 and SEL is connected to CSS _ SEL of the controller 1400.

Fig. 1 to 8 show LED devices arranged in a common cathode configuration, while fig. 9 to 14B respectively show LED devices arranged in a common anode configuration. For example, fig. 1 and 9 show similar structures, except that fig. 1 is in a common cathode configuration, while fig. 9 is in a common anode configuration. By analogy, fig. 2A, 2B and fig. 10A, 10B show similar structures, except that fig. 2A, 2B are in a common cathode configuration, while fig. 10A and 10B are in a common anode configuration. The remainder of fig. 3-5, 7A and 7B correspond to fig. 11-13, 14A and 14B, respectively.

Table 1 shows the manner in which the LEDs in the four anode cores of fig. 2B are lit, also referred to as the scan assignment or lighting sequence. Each core _ Anode <31 > has 32 pins connected to a 32x32 matrix of LEDs, only one pin receiving the scan digital signal at a time, so that only one of the 32 LEDs is lit at any given time, thereby reducing the ambiguity. Furthermore, the scan assignment algorithm in this embodiment creates a pattern in which the LEDs are illuminated continuously, but are dispersed in different areas of the LED array. The algorithm ensures that LEDs in one small cluster do not light up continuously in one area, while LEDs in another area remain dark for a long time. For example, LEDs in the first 8 columns (Y = 0-7) are lit in order from 0 to 31. Even numbers in columns 0 to 3 and odd numbers in columns 4 to 7, which ensures that one LED in columns 0 to 3 is lit, followed by lighting one LED in columns 4 to 7. The LEDs in columns 0-3 are lit with each column having one lit LED in one cycle, e.g., 0,2, 4, 6, then 8, 10, 12, 14. The algorithm can be adjusted to accomplish the scan assignment to optimize the visual effect.

TABLE 1

TABLE 1 (continue)

TABLE 1 (continue)

TABLE 2

Table 2 shows an example of the illumination sequence of the LEDs in two 4x8 base LED arrays. Fig. 5 shows one such 4x8 base array. Fig. 4A shows one row of the 4-base array of fig. 5, while fig. 3 shows 32 rows of fig. 4B from top to bottom. The two base arrays shown in table 2 are located in the upper left hand corner of the arrangement in fig. 3. CoreX _ a <0> represents the LED column connected to the anode kernel number X, channel 0. Core0_ Cathode <0> represents the row of LEDs connected to the Cathode Core number 0, line 0.

The total of 64 LEDs is divided into four groups of 4x4 LEDs. Each base array is arranged such that the left two sets of 4x4 LEDs receive a scanning signal only when the scanning duty is even (hence "even LEDs"), while the right two sets of 4x4 LEDs receive a scanning signal only when the scanning duty is odd (hence "odd LEDs"). During one image frame, the even LEDs and the odd LEDs are sequentially driven and alternately lit. Thus, at any given time, only one LED of two adjacent 4 × 4LED groups is illuminated, one of the 4 × 4 even LEDs is illuminated, followed by one of the 4 × 4 odd LEDs. Thus, only one of the 32 LEDs emits light at any given time, thereby reducing the blooming effect.

Requiring only the LEDs in a local area (e.g., 4x 4) to be lit at a sufficiently high frequency (e.g., 60Hz or higher) can reduce flicker. However, when more than one LED is on in a local area (e.g., 4x 4), there may be a blooming effect. The embodiment of the utility model provides a make only one LED light in local area, consequently not only reduced the scintillation, still reduced the blur.

The embodiment of fig. 1-7B has a 32 scan x32 channel configuration. Other configurations are also possible. For example, the scan number and channel number need not be the same, e.g., 16 scans by 32 channels. However, in this configuration, some pins would have to be allocated to connect only to scan lines or channels, providing only one function. Further, the number of scans or channels may be greater or less than 32. A smaller number of scans/channels will enable finer control of the LEDs, which will also increase the cost and footprint of the driver, since more pins and connections are required to drive the same number of LEDs. A larger number of scans/channels will further reduce the pin count but require higher frequency switches to be configured.

In other embodiments of the present invention, the base LED arrays in the LED blocks may employ a common anode configuration. In such an embodiment, the connections of the cathode and anode blocks are changed accordingly. The CSSN _32x32x4 module internal pin sequence in the common anode configuration is the same as the CSSP _32x32x4 module internal pin sequence in the common cathode configuration. The CSSP _32x32x4 module internal pin sequence in the common anode configuration is the same as the CSSN _32x32x4 module internal pin sequence in the common cathode configuration. As described above, fig. 9-14B show the common anode configuration in detail. For example, fig. 1 and 9 show similar structures, except that fig. 1 is in a common cathode configuration, while fig. 9 is in a common anode configuration. By analogy, fig. 2A, 2B and fig. 10A, 10B show similar structures, except that fig. 2A, 2B are in a common cathode configuration, while fig. 10A and 10B are in a common anode configuration. The remainder of fig. 3-5, 7A and 7B correspond to fig. 11-13, 14A and 14B, respectively. Components in a common anode configuration are sometimes named with the suffix "CA" or "_ CA" appended to the name applied to similar components in a common cathode configuration.

In the common anode configuration, the anode side CSS sub-block CSSP _ AD8x1 of fig. 6 is connected to CSSP _32x32x4_ ca in fig. 1 and 2A, 2B. By analogy, the cathode-side CSS sub-block CSSN _ AD8x1 in fig. 13 is connected to CSSN _32 × 32 × 4_ca, as shown in fig. 9 and 10A, 10B.

Fig. 10A and 10B show details of the anode-side CSS control block (CSSP _32 × 32 × 4\ ca) 8100 of the common anode configuration in fig. 9. In strobe common delay mode, all cathodes are driven by a current sink control input, and the Cathode connection sequence is the same as the current sink sequence, core _ Cathode <31 > = IsinkX <31 >. In the static anti-blooming scan mode, all cathodes are driven by scan control inputs, and to ensure that only one LED is on in adjacent LEDs, each sequence of kernel scan inputs is grouped differently to ensure that only one LED is on at any given time in the 8x4 LED array.

The assignment of cathode pins in scan mode is detailed below:

core0 static anti-blur scan pin assignment:

Core0_Cathode<31>＝SCAN_N0<31>

Core0_Cathode<30>＝SCAN_N0<15>

Core0_Cathode<29>＝SCAN_N0<23>

Core0_Cathode<28>＝SCAN_N0<7>

Core0_Cathode<27>＝SCAN_N0<30>

Core0_Cathode<26>＝SCAN_N0<14>

Core0_Cathode<25>＝SCAN_N0<22>

Core0_Cathode<24>＝SCAN_N0<6>

Core0_Cathode<23>＝SCAN_N0<29>

Core0_Cathode<22>＝SCAN_N0<13>

Core0_Cathode<21>＝SCAN_N0<21>

Core0_Cathode<20>＝SCAN_N0<5>

Core0_Cathode<19>＝SCAN_N0<28>

Core0_Cathode<18>＝SCAN_N0<12>

Core0_Cathode<17>＝SCAN_N0<20>

Core0_Cathode<16>＝SCAN_N0<4>

Core0_Cathode<15>＝SCAN_N0<27>

Core0_Cathode<14>＝SCAN_N0<11>

Core0_Cathode<13>＝SCAN_N0<19>

Core0_Cathode<12>＝SCAN_N0<3>

Core0_Cathode<11>＝SCAN_N0<26>

Core0_Cathode<10>＝SCAN_N0<10>

Core0_Cathode<9>＝SCAN_N0<18>

Core0_Cathode<8>＝SCAN_N0<2>

Core0_Cathode<7>＝SCAN_N0<25>

Core0_Cathode<6>＝SCAN_N0<9>

Core0_Cathode<5>＝SCAN_N0<17>

Core0_Cathode<4>＝SCAN_N0<1>

Core0_Cathode<3>＝SCAN_N0<24>

Core0_Cathode<2>＝SCAN_N0<8>

Core0_Cathode<1>＝SCAN_N0<16>

Core0_Cathode<0>＝SCAN_N0<0>.

core1 static anti-blur scan pin assignment:

Core1_Cathode<31>＝SCAN_N0<25>

Core1_Cathode<30>＝SCAN_N0<9>

Core1_Cathode<29>＝SCAN_N0<1>

Core1_Cathode<28>＝SCAN_N0<17>

Core1_Cathode<27>＝SCAN_N0<24>

Core1_Cathode<26>＝SCAN_N0<8>

Core1_Cathode<25>＝SCAN_N0<0>

Core1_Cathode<24>＝SCAN_N0<16>

Core1_Cathode<23>＝SCAN_N0<23>

Core1_Cathode<22>＝SCAN_N0<7>

Core1_Cathode<21>＝SCAN_N0<31>

Core1_Cathode<20>＝SCAN_N0<15>

Core1_Cathode<19>＝SCAN_N0<22>

Core1_Cathode<18>＝SCAN_N0<6>

Core1_Cathode<17>＝SCAN_N0<30>

Core1_Cathode<16>＝SCAN_N0<14>

Core1_Cathode<15>＝SCAN_N0<21>

Core1_Cathode<14>＝SCAN_N0<5>

Core1_Cathode<13>＝SCAN_N0<29>

Core1_Cathode<12>＝SCAN_N0<13>

Core1_Cathode<11>＝SCAN_N0<20>

Core1_Cathode<10>＝SCAN_N0<4>

Core1_Cathode<9>＝SCAN_N0<28>

Core1_Cathode<8>＝SCAN_N0<12>

Core1_Cathode<7>＝SCAN_N0<19>

Core1_Cathode<6>＝SCAN_N0<3>

Core1_Cathode<5>＝SCAN_N0<27>

Core1_Cathode<4>＝SCAN_N0<11>

Core1_Cathode<3>＝SCAN_N0<18>

Core1_Cathode<2>＝SCAN_N0<2>

Core1_Cathode<1>＝SCAN_N0<26>

Core1_Cathode<0>＝SCAN_N0<10>.

core2 static anti-blur scan pin assignment:

Core2_Cathode<31>＝SCAN_N0<19> Core2_Cathode<30>＝SCAN_N0<3> Core2_Cathode<29>＝SCAN_N0<11> Core2_Cathode<28>＝SCAN_N0<27> Core2_Cathode<27>＝SCAN_N0<18> Core2_Cathode<26>＝SCAN_N0<2> Core2_Cathode<25>＝SCAN_N0<10> Core2_Cathode<24>＝SCAN_N0<26> Core2_Cathode<23>＝SCAN_N0<17> Core2_Cathode<22>＝SCAN_N0<1> Core2_Cathode<21>＝SCAN_N0<9> Core2_Cathode<20>＝SCAN_N0<25> Core2_Cathode<19>＝SCAN_N0<16> Core2_Cathode<18>＝SCAN_N0<0> Core2_Cathode<17>＝SCAN_N0<8> Core2_Cathode<16>＝SCAN_N0<24> Core2_Cathode<15>＝SCAN_N0<15> Core2_Cathode<14>＝SCAN_N0<31> Core2_Cathode<13>＝SCAN_N0<7> Core2_Cathode<12>＝SCAN_N0<23> Core2_Cathode<11>＝SCAN_N0<14> Core2_Cathode<10>＝SCAN_N0<30> Core2_Cathode<9>＝SCAN_N0<6> Core2_Cathode<8>＝SCAN_N0<22> Core2_Cathode<7>＝SCAN_N0<13> Core2_Cathode<6>＝SCAN_N0<29> Core2_Cathode<5>＝SCAN_N0<5> Core2_Cathode<4>＝SCAN_N0<21> Core2_Cathode<3>＝SCAN_N0<12>

Core2_Cathode<2>＝SCAN_N0<28>

Core2_Cathode<1>＝SCAN_N0<4>

Core2_Cathode<0>＝SCAN_N0<20>.

core3 static anti-blur scan pin assignment:

Core3_Cathode<31>＝SCAN_N0<13>

Core3_Cathode<30>＝SCAN_N0<29>

Core3_Cathode<29>＝SCAN_N0<21>

Core3_Cathode<28>＝SCAN_N0<5>

Core3_Cathode<27>＝SCAN_N0<12>

Core3_Cathode<26>＝SCAN_N0<28>

Core3_Cathode<25>＝SCAN_N0<20>

Core3_Cathode<24>＝SCAN_N0<4>

Core3_Cathode<23>＝SCAN_N0<11>

Core3_Cathode<22>＝SCAN_N0<27>

Core3_Cathode<21>＝SCAN_N0<19>

Core3_Cathode<20>＝SCAN_N0<3>

Core3_Cathode<19>＝SCAN_N0<10>

Core3_Cathode<18>＝SCAN_N0<26>

Core3_Cathode<17>＝SCAN_N0<18>

Core3_Cathode<16>＝SCAN_N0<2>

Core3_Cathode<15>＝SCAN_N0<9>

Core3_Cathode<14>＝SCAN_N0<25>

Core3_Cathode<13>＝SCAN_N0<17>

Core3_Cathode<12>＝SCAN_N0<1>

Core3_Cathode<11>＝SCAN_N0<8>

Core3_Cathode<10>＝SCAN_N0<24>

Core3_Cathode<9>＝SCAN_N0<16>

Core3_Cathode<8>＝SCAN_N0<0>

Core3_Cathode<7>＝SCAN_N0<7>

Core3_Cathode<6>＝SCAN_N0<23>

Core3_Cathode<5>＝SCAN_N0<15>

Core3_Cathode<4>＝SCAN_N0<31>

Core3_Cathode<3>＝SCAN_N0<6>

Core3_Cathode<2>＝SCAN_N0<22>

Core3_Cathode<1>＝SCAN_N0<14>

fig. 11 shows an example of a CSS _32x32x4 LED block in the common anode configuration shown in fig. 9. In cathode side strobe common delay mode, the CoreX cathodes are interleaved to the CoreX current sink signal. In the cathode side static anti-blooming mode, the CoreX cathodes are connected to the CoreX channel scan signal interleaved. In the anode side strobe common delay mode, the CoreX anodes are connected to the CoreX scan signal in an interleaved manner. In the anode side static anti-blooming mode the CoreX anodes are cross-connected to the CoreX channel current source signals.

The CSS _32x32x4 common anode channel scan switch array includes 32 blocks of 32x4 _cainterleaved sub-arrays. The same cathodes of each block are connected together by a total of 128 connection points. Each module has four anodes connected, with different anodes being driven by different cores in an interleaved manner. A total of 128 anode connections drive a total of 32 blocks. The array includes a total of 4096 LEDs controlled by a total of 256 signals.

Fig. 12A and 12B show an example of a common anode staggered structure. The CSS _32x4 _CAcommon anode interleaved structure includes four CSS _32x1 _CAblocks that share the same anode lead, but differ in the cathode lead. Each core provides one anode connection and 32 cathode connections.

Fig. 13 shows an example of a CSS _32x1 common anode interleaved switching element. In strobe common delay mode, the anode is driven by the CoreX scan signal and the cathode is driven by the CoreX current sink signal. In static anti-blooming mode, anodeX is driven by a CoreX current source and CathodeX is driven by a CoreX scan signal, with only one LED on at any given time, with each core providing 4 even and 4 odd scans, 16 different even scans on the left and 16 different odd scans on the right.

Fig. 14A and 14B show examples of cathode side channel scan switches on 32x32 cores core0 through core3 in the common anode configuration shown in fig. 9. Fig. 14A and 14B show details of the cathode side channel scan switch control block (CSSN _32 × 32 × 4 _ca) 9300 shown in fig. 9, which is composed of 4 cores of the 32 × 32 cathode side channel scan switch, i.e., 14100, 14200, 14300, and 14400. In the static anti-blur scanning mode, all anodes are driven by a current source control input, and the Anode connection sequence is the same as the current source sequence, coreX _ Anode <31 > = IsoourceX <31 >. In strobe common delay mode, all anodes are driven by Scan control input, and the Anode connection sequence is the same as the Scan sequence, coreX _ Anode <31 > = Scan _ NX <31 >.

The components in the common anode configuration are similar or identical to the components in the common cathode configuration. The significant difference is that the LEDs are connected to a common anode node instead of a common cathode node. For example, the base array in fig. 12A still has a 4 × 8 LED array. On the other hand, the anodes of the 8 LEDs in a row are connected to a common anode node.

In other embodiments, the number of channels and the number of scan lines may be different from 32, such as 16, and the number of pins will vary accordingly. In addition, the channel number and scan number may be different.

In other embodiments, the circuitry that enables the connection switch between the analog input (current source or sink) and the digital scan input may be different.

In summary, the present invention provides an LED display device wherein the connection pins can be switched between receiving digital scan input and receiving analog input. In addition, the LED system has a plurality of anode cores (anodes of the module driving LEDs), a plurality of cathode cores (cathodes of the module driving LEDs), and an LED array composed of a plurality of base arrays. Each base array contains staggered rows of LEDs controlled by different cores. The multi-kernel and interleaved functionality allows one LED in a small group of LEDs to be lit at any given time, thus reducing not only flicker, but also blur.

Claims (11)

1. An LED display device, comprising:

at least one display unit, wherein each of the at least one display unit further comprises an LED array of LxMxN LEDs driven by the N cores of the channel scan switch;

an anode side switching circuit for an anode side channel scan switch having MxN current source analog inputs and MxN digital scan inputs, wherein the anode side switching circuit is switchably connected to the MxN current sources and the MxN scan lines;

a cathode side switching circuit for a cathode side channel scan switch having MxN current sinks analog inputs and MxN digital scan inputs, wherein the cathode side switching circuit is switchably connected to the MxN current sinks and the MxN scan lines; and

a controller, comprising:

a first selection circuit connected to the MxN current sources and the MxN scan lines, wherein the first selection circuit is configured to select at least one current source from the MxN current sources and at least one scan line from the MxN scan lines in the anode side switching circuit; and

a second selection circuit connected to the MxN current sinks and the MxN scan lines, wherein the second selection circuit is configured to select at least one current sink from the MxN current sinks in the cathode side switching circuit and at least one scan line from the MxN scan lines.

2. The LED display device of claim 1, wherein one of the at least two modes of the controller is a static anti-blur scanning mode.

3. The LED display device of claim 1, wherein another of the at least two modes of the controller is a strobed motion blur removal mode.

4. The LED display device of claim 2, wherein when both the first selection circuit and the second selection circuit are switched to a static anti-blooming scan mode, all anodes are driven by a scan control input.

5. The LED display device of claim 3, wherein all anodes are driven by a current source control input when both the first selection circuit and the second selection circuit are switched to a strobed motion blur removal mode.

6. The LED display device of claim 2, wherein when both the first selection circuit and the second selection circuit are switched to the static anti-blooming scan mode, the CoreX cathodes are alternately connected to respective CoreX channel current sink signals.

7. The LED display device of claim 3, wherein when both the first and second selection circuits switch to the strobed motion blur removal mode, coreX cathodes are alternately connected to respective CoreX scan signals.

8. The LED display device of claim 2, wherein all cathodes are driven by the current sink control input when both the first selection circuit and the second selection circuit are switched to a static anti-blooming scan mode.

9. The LED display device of claim 3, wherein when both the first selection circuit and the second selection circuit are switched to the stroboscopic motion blur removal mode, all cathodes are driven by a scan control input.

10. The LED display device of claim 1, wherein the LED display device employs a common anode configuration.

11. The LED display device of claim 1, wherein the LED display device employs a common cathode configuration.

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