CN218587163U - Logic control circuit with two-bit input - Google Patents
Logic control circuit with two-bit input Download PDFInfo
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- CN218587163U CN218587163U CN202222159453.1U CN202222159453U CN218587163U CN 218587163 U CN218587163 U CN 218587163U CN 202222159453 U CN202222159453 U CN 202222159453U CN 218587163 U CN218587163 U CN 218587163U
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Abstract
The utility model discloses a logic control circuit of two inputs, this circuit includes: logic circuit, logic circuit includes first opto-coupler to fifth opto-coupler, first MOS pipe, second MOS pipe and first stabilivolt, through being connected of opto-coupler and MOS pipe and stabilivolt, realizes four kinds of outputs of both ends input, compares the cost lower with the logic control circuit of four kinds of outputs of software control's both ends input, and the utility model discloses a logic control circuit only realizes logic control through hardware and need not set up through the software, and it is more simple and convenient to maintain and use, and then stability is higher.
Description
Technical Field
The utility model relates to an electronic circuit technical field especially relates to a logic control circuit of two inputs.
Background
For a two-bit input four-output logic control circuit, the prior art generally uses software to control. The software-controlled logic control circuit has high research and development cost, and the instability of the circuit is increased due to the difficulty in later maintenance and the complex use.
SUMMERY OF THE UTILITY MODEL
The utility model provides a logic control circuit of two inputs to solve the logic control circuit of four kinds of outputs of current two inputs with high costs and unstable technical problem.
In order to solve the above technical problem, an embodiment of the present invention provides a two-bit input logic control circuit, including a logic circuit;
the logic circuit includes: the circuit comprises a first optical coupler, a second optical coupler, a third optical coupler, a fourth optical coupler, a fifth optical coupler, a first MOS (metal oxide semiconductor) tube, a second MOS tube and a first voltage regulator tube;
the first end of the first optical coupler is electrically connected with a first input signal, the second end of the first optical coupler is connected with an output negative end, the third end of the first optical coupler is connected with the fourth end of the second optical coupler, and the fourth end of the first optical coupler is connected with a first port;
a first end of the second optocoupler is electrically connected with the second input signal, a second end of the second optocoupler is connected with the output negative end, and a third end of the second optocoupler is connected with a second port;
the first end of the third optocoupler is electrically connected with the second input signal, the second end of the third optocoupler is connected with the first end of the fourth optocoupler, the third end of the third optocoupler is connected with the output negative end, and the fourth end of the third optocoupler is connected with the voltage port, the negative electrode of the first voltage-regulator tube and the fourth end of the fifth optocoupler;
a second end of the fourth optical coupler is electrically connected with the first input signal, a third end of the fourth optical coupler is connected with a grid electrode of the first MOS transistor, and a fourth end of the fourth optical coupler is connected with the voltage port;
a first end of the fifth optocoupler is electrically connected with the first input signal, a second end of the fifth optocoupler is electrically connected with the second input signal, and a third end of the fifth optocoupler is connected with the output negative end;
the anode of the first voltage-stabilizing tube is connected with the grid electrode of the second MOS tube;
the drain electrode of the second MOS tube is connected with the third port, and the source electrode of the second MOS tube is connected with the fourth port;
the drain electrode of the first MOS tube is connected with the fifth port, and the source electrode of the first MOS tube is connected with the fourth port.
In the logic circuit of the utility model, when the first input signal and the second input signal are suspended, the grid electrode of the second MOS transistor is connected with the voltage interface through the first voltage-regulator tube, and the grid source voltage of the second MOS transistor meets the starting voltage, so that the third port and the fourth port are in short circuit to obtain a first output result; similarly, when the first input signal and the second input signal are both 0, the second MOS transistor is connected with the voltage interface through the first voltage regulator transistor, and is conducted to form a first output result; when the first input signal is 1 and the second input signal is 0, the secondary side of the fifth optical coupler is conducted, the grid of the second MOS tube is connected with the fourth end of the fifth optical coupler, the grid of the second MOS tube is pulled to a low potential, the second MOS tube is cut off, the secondary sides of the second optical coupler, the third optical coupler and the fourth optical coupler are cut off, and the first port, the second port, the third port, the fourth port and the fifth port are all suspended to obtain a second output result; when the first input signal is 0 and the second input signal is 1, the secondary sides of the third optocoupler and the fourth optocoupler are conducted, other optocouplers are cut off, the second MOS transistor is pulled to a low potential due to the fact that the grid electrode of the second MOS transistor is connected with the fourth end of the third optocoupler through the first voltage stabilizing tube, the second MOS transistor is cut off, the grid electrode of the first MOS transistor is connected with the third end of the fourth optocoupler, the grid electrode of the first MOS transistor is in short circuit with the voltage port to obtain a high potential, the first MOS transistor is conducted, the fifth port is in short circuit with the fourth port, and a third output result is obtained; when the first input signal and the second input signal are both 1, the secondary side of the first optical coupler and the secondary side of the second optical coupler are switched on, other optical couplers are cut off, the first port and the second port are in short circuit, and a fourth output result is obtained. Therefore, the utility model discloses an opto-coupler, MOS pipe and stabilivolt can realize four kinds of outputs of both ends input, compare the cost lower with the logic control circuit of four kinds of outputs of both ends input of software control, and the utility model discloses a logic control circuit only realizes logic control through hardware and need not set up through software, and it is more simple and convenient to maintain and use, and then stability is higher.
Further, the logic circuit further comprises: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a ninth resistor;
a first end of the first resistor is electrically connected with the first input signal, and a second end of the first resistor is connected with a first end of the first optocoupler;
a first end of the second resistor is electrically connected with the second input signal, and a second end of the second resistor is connected with a first end of the second optocoupler;
the first end of the third resistor is electrically connected with the second input signal, and the second end of the third resistor is connected with the first end of the third optocoupler;
a first end of the fourth resistor is connected with the voltage port, and a second end of the fourth resistor is connected with a fourth end of the third optocoupler, a negative electrode of the first voltage regulator tube and a fourth end of the fifth optocoupler;
a first end of the fifth resistor is connected with the voltage port, and a second end of the fifth resistor is connected with a fourth end of the fourth optocoupler;
the first end of the sixth resistor is connected with the grid electrode of the first MOS tube, and the second end of the sixth resistor is connected with the source electrode of the first MOS tube and the fourth port;
the first end of the seventh resistor is connected with the grid electrode of the second MOS tube and the anode of the first voltage regulator tube, and the second end of the seventh resistor is connected with the source electrode and the fourth port of the second MOS tube;
a first end of the eighth resistor is connected with a first end of the fifth optocoupler, and a second end of the eighth resistor is electrically connected with the first input signal;
and the first end of the ninth resistor is connected with the negative output terminal, and the second end of the ninth resistor is connected with the fourth port.
The first resistor, the second resistor, the third resistor and the eighth resistor in the utility model are respectively connected with the corresponding optocouplers and input signals, so as to realize the shunting effect, further prevent the primary side of a certain optocoupler in the logic circuit from being pulled to a low potential when the first input signal and the second input signal are different potentials, and ensure the working stability of the logic circuit; the fourth resistor and the fifth resistor are respectively connected with the fourth ends of the third optocoupler and the fourth optocoupler and the voltage port, so that the current limiting effect is realized, the secondary sides of the third optocoupler and the fourth optocoupler can be completely conducted, and the working stability of the logic circuit is improved; the sixth resistor and the seventh resistor are respectively connected in parallel between the gate and the source of the first MOS transistor and the gate and the source of the second MOS transistor, so that the MOS transistors can be stably cut off, and the working stability of the logic circuit is improved.
Furthermore, the two-bit input logic control circuit also comprises an output conversion circuit;
the output conversion circuit includes: the circuit comprises a first chip, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor and a fourteenth resistor;
a first input pin of the first chip is connected with a first input power supply;
a second input pin of the first chip is connected with the second port and a second input power supply;
the enabling pin of the first chip is connected with the first port;
a first output pin of the first chip is connected with a first end and an output positive end of a tenth resistor;
a second output pin of the first chip is connected with a first end of an eleventh resistor and the output negative end;
the forward adjusting pin of the first chip is connected with the second end of the tenth resistor and the first end of the twelfth resistor;
a third output pin of the first chip is connected with a second end of the twelfth resistor, a first end of the thirteenth resistor and a first end of the fourteenth resistor;
a reverse adjustment pin of the first chip is connected with the fourth port and a second end of the eleventh resistor;
a second end of the thirteenth resistor is connected with the fifth port;
a second terminal of the fourteenth resistor is connected to the third port.
The output conversion circuit in the utility model, when the logic circuit forms the first output result, the third port and the fourth port are short-circuited, and the fourteenth resistor is connected in series between the third output pin and the reverse regulation pin of the first chip, so that the output voltage of the first output pin of the first chip is reduced to obtain the first output voltage; when the logic circuit forms a second output result, the first port to the fifth port are suspended, and only the twelfth resistor is connected in series between the forward direction adjusting pin and the third output pin, so that the first output pin of the first chip outputs a second output voltage; when the logic circuit forms a third output result, the thirteenth resistor is connected in series between the third output pin and the reverse regulation pin of the first chip, so that the output voltage of the first output pin of the first chip is reduced, and a third output voltage is obtained; when the logic circuit forms a third output result, the enabling pin of the first chip is in short circuit with the second input pin due to the fact that the first port is in short circuit with the second port, the first chip stops working, and a fourth output voltage or 0 voltage is output. The utility model discloses an output conversion circuit is connected with first chip through making tenth resistance to fourteenth resistance, realizes turning into four kinds of output voltage results with logic circuit's four kinds of output results.
Further, the output conversion circuit further includes: a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, and a nineteenth resistor;
a first end of the fifteenth resistor is connected with a second end of the tenth resistor, a first end of the twelfth resistor and a forward adjustment pin of the first chip;
a second end of the fifteenth resistor is connected with a third output pin of the first chip, a first end of the sixteenth resistor, a first end of the seventeenth resistor, a first end of the eighteenth resistor and a first end of the nineteenth resistor;
a second end of the sixteenth resistor is connected with a first end of the thirteenth resistor and a second end of the seventeenth resistor;
a second end of the eighteenth resistor is connected to a first end of the fourteenth resistor and a second end of the nineteenth resistor.
This use neotype fifteenth resistance to nineteenth resistance and twelfth resistance to fourteenth resistance to be parallelly connected or concatenate, make the voltage regulation resistance of connecting between the forward regulation pin of first chip and third output pin and the voltage regulation resistance between reverse regulation pin and the third output pin can be set for different numerical values, realize the output different output voltage results of first output pin output of first chip.
Further, the output conversion circuit further includes: the first capacitor, the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor;
the first end of the first capacitor is connected with the enabling pin of the first chip and the first port;
the second end of the first capacitor is connected with the second input pin of the first chip, the second port and a second input power supply;
the first end of the second capacitor is connected with the first end of the tenth resistor, the first output pin of the first chip, the positive output terminal, the first end of the third capacitor, the first end of the fourth capacitor and the first end of the fifth capacitor;
the second end of the second capacitor is connected with the first end of the eleventh resistor, the second output pin of the first chip, the output negative terminal, the second end of the third capacitor, the second end of the fourth capacitor and the second end of the fifth capacitor.
The utility model provides a first electric capacity concatenates between the enable pin and the second input pin of first chip, and the peak of the signal of the first port transmission of filtering prevents that the module mistake from opening or the mistake is turn-offed, improves the stability of circuit work.
Further, the output conversion circuit further includes: the first inductor, the sixth capacitor, the seventh capacitor and the eighth capacitor;
a first end of the sixth capacitor is connected with the first input power supply and a first end of the first inductor;
the second end of the first inductor is connected with the first end of the seventh capacitor, the first end of the eighth capacitor and the first input pin of the first chip;
and a second end of the sixth capacitor is connected with the second input power supply, a second end of the seventh capacitor, a second end of the eighth capacitor, the second port and a second input pin of the first chip.
The utility model provides a first inductance is connected with sixth electric capacity to eighth electric capacity, constitutes filter circuit to make the first input pin and the second input pin of first chip receive stable signal.
Furthermore, the logic control circuit with the two-bit input also comprises a power supply circuit;
the power supply circuit includes: the second chip, the twentieth resistor, the twenty-first resistor and the ninth capacitor;
a first input pin of the second chip is connected with the first input power supply;
a second input pin of the second chip is connected with the second input power supply;
a first output pin of the second chip is connected with a first end of the twentieth resistor, a first end of the ninth capacitor and the voltage port;
a second output pin of the second chip is connected with a first end of the twenty-first resistor, a second end of the ninth capacitor and the output negative end;
and a third output pin of the second chip is connected with a second end of the twentieth resistor and a second end of the twenty-first resistor.
In this embodiment, the third output pin of the second chip is connected to the first output pin and the second output pin of the second chip through the twentieth resistor and the twenty-first resistor, respectively, and therefore the first output pin outputs a stable voltage to the voltage port, thereby improving the stability of the logic circuit.
Further, the power supply circuit further includes: a second inductor, a tenth capacitor and an eleventh capacitor;
the first end of the second inductor is connected with the first input power supply and the first end of the tenth capacitor;
a second end of the second inductor is connected with a first input pin of the second chip and a first end of the eleventh capacitor;
a second end of the tenth capacitor is connected to the second input power supply, the second input pin of the second chip, and a second end of the eleventh capacitor.
The utility model provides a second inductance is connected with tenth electric capacity and eleventh electric capacity, constitutes filter circuit to make the first input pin and the second input pin of second chip receive stable signal, and then promote the stability of logic circuit work.
Further, the output negative terminal is connected with circuit ground.
Drawings
Fig. 1 is a schematic diagram illustrating a connection relationship of an embodiment of a logic circuit provided by the present invention;
fig. 2 is a schematic diagram of a connection relationship of an embodiment of an output conversion circuit provided by the present invention;
fig. 3 is a schematic connection diagram of an embodiment of the power supply circuit provided by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Example one
Fig. 1 is a schematic diagram of a connection relationship of an embodiment of a logic circuit according to the present invention.
The utility model provides a two-bit input logic control circuit, which comprises a logic circuit;
the logic circuit includes: the circuit comprises a first optical coupler U1, a second optical coupler U4, a third optical coupler U2, a fourth optical coupler U5, a fifth optical coupler U3, a first MOS (metal oxide semiconductor) tube Q2, a second MOS tube Q1 and a first voltage regulator tube V1;
a first end of the first optocoupler U1 is electrically connected with a first input signal S1, a second end of the first optocoupler U1 is connected with an output negative end VO-, a third end of the first optocoupler U1 is connected with a fourth end of the second optocoupler U4, and the fourth end of the first optocoupler U1 is connected with a first port CTR;
a first end of the second optocoupler U4 is electrically connected with the second input signal S2, a second end of the second optocoupler U4 is connected with the output negative end VO-, and a third end of the second optocoupler U4 is connected with a second port G2;
a first end of the third optocoupler U2 is electrically connected with the second input signal S2, a second end of the third optocoupler U2 is connected with a first end of the fourth optocoupler U5, a third end of the third optocoupler U2 is connected with the output negative end VO-, and a fourth end of the third optocoupler U2 is connected with a voltage port VCC, a negative electrode of the first voltage regulator tube V1 and a fourth end of the fifth optocoupler U3;
a second end of the fourth optocoupler U5 is connected with the first input signal S1, a third end of the fourth optocoupler U5 is connected with a grid electrode of the first MOS transistor Q2, and a fourth end of the fourth optocoupler U5 is connected with the voltage port VCC;
a first end of the fifth optocoupler U3 is electrically connected with the first input signal S1, a second end of the fifth optocoupler is electrically connected with the second input signal S2, and a third end of the fifth optocoupler is connected with the output negative end VO-;
the anode of the first voltage-regulator tube V1 is connected with the grid of the second MOS tube Q1;
the drain electrode of the second MOS tube Q1 is connected with a third port 24VTZ, and the source electrode of the second MOS tube Q1 is connected with a fourth port S-;
the drain of the first MOS transistor Q2 is connected to a fifth port 28VTZ, and the source of the first MOS transistor Q2 is connected to the fourth port S-.
In the logic circuit of the present invention, when the first input signal S1 and the second input signal S2 are suspended, the gate of the second MOS transistor Q1 is connected to the voltage interface VCC through the first voltage regulator V1, and the gate-source voltage of the second MOS transistor Q1 satisfies the turn-on voltage, so that the third port 24VTZ and the fourth port S-are short-circuited to obtain a first output result; similarly, when the first input signal S1 and the second input signal S2 are both 0, the second MOS transistor Q1 is connected to the voltage interface VCC through the first regulator transistor V1, and is turned on to form a first output result; when the first input signal S1 is 1 and the second input signal S2 is 0, the secondary side of the fifth optocoupler U3 is turned on, the gate of the second MOS transistor Q1 connected to the fourth end of the fifth optocoupler U3 is pulled to a low potential to cut off the second MOS transistor Q1, and the secondary sides of the second optocoupler U4, the third optocoupler U2 and the fourth optocoupler U5 are cut off, so that the first port CTR, the second port G2, the third port 24VTZ, the fourth port S-and the fifth port 28VTZ are all suspended, and a second output result is obtained; when the first input signal S1 is 0 and the second input signal S2 is 1, the secondary sides of the third optocoupler U2 and the fourth optocoupler U5 are conducted, other optocouplers are cut off, the second MOS transistor Q1 is pulled to a low potential due to the fact that a grid electrode is connected with the fourth end of the third optocoupler U2 through the first voltage stabilizing tube V1, then the second MOS transistor Q2 is cut off, the grid electrode of the first MOS transistor Q2 is in short circuit with the voltage port VCC due to the fact that the grid electrode is connected with the third end of the fourth optocoupler, high potential is obtained, then the first MOS transistor Q2 is conducted, then the fifth port 28VTZ is in short circuit with the fourth port S-, and a third output result is obtained; when the first input signal S1 and the second input signal S2 are both 1, the auxiliary sides of the first optocoupler U1 and the second optocoupler U4 are switched on, other optocouplers are switched off, the first port CTR and the second port G2 are in short circuit, and a fourth output result is obtained. Therefore, the utility model discloses an opto-coupler, MOS pipe and stabilivolt can realize four kinds of outputs of both ends input, compare the cost lower with the logic control circuit of four kinds of outputs of software control's both ends input, and the utility model discloses a logic control circuit only realizes logic control through hardware and need not set up through software, and it is more simple and convenient to maintain and use, and then stability is higher.
Further, the logic circuit further comprises: a first resistor R15, a second resistor R20, a third resistor R17, a fourth resistor R14, a fifth resistor R19, a sixth resistor R22, a seventh resistor R16, an eighth resistor R18, and a ninth resistor R21;
a first end of the first resistor R15 is electrically connected to the first input signal S1, and a second end of the first resistor R15 is connected to a first end of the first optocoupler U1;
a first end of the second resistor R20 is electrically connected to the second input signal S2, and a second end of the second resistor R20 is connected to a first end of the second optocoupler U4;
a first end of the third resistor R17 is electrically connected to the second input signal S2, and a second end of the third resistor R17 is connected to a first end of the third optocoupler U2;
a first end of the fourth resistor R14 is connected to the voltage port VCC, and a second end of the fourth resistor R14 is connected to a fourth end of the third optocoupler U2, a negative electrode of the first voltage regulator tube V1, and a fourth end of the fifth optocoupler U3;
a first end of the fifth resistor R19 is connected to the voltage port VCC, and a second end of the fifth resistor R19 is connected to a fourth end of the fourth optocoupler U5;
a first end of the sixth resistor R22 is connected to the gate of the first MOS transistor Q2, and a second end of the sixth resistor R22 is connected to the source of the first MOS transistor Q2 and the fourth port S-;
a first end of the seventh resistor R16 is connected to the gate of the second MOS transistor Q1 and the anode of the first voltage regulator V1, and a second end of the seventh resistor R16 is connected to the source of the second MOS transistor Q1 and the fourth port S-;
a first end of the eighth resistor R18 is connected to a first end of the fifth optocoupler U3, and a second end of the eighth resistor R18 is electrically connected to the first input signal S1;
the first end of the ninth resistor R21 is connected with the output negative terminal VO-, and the second end of the ninth resistor R21 is connected with the fourth port S-.
In this embodiment, the ninth resistor R21 may be a 0 ohm resistor.
The first resistor R15, the second resistor R20, the third resistor R17 and the eighth resistor R18 in the utility model are respectively connected with the corresponding optical couplers and input signals, so that the shunting effect is realized, and when the first input signal S1 and the second input signal S2 are different potentials, the primary side of a certain optical coupler in the logic circuit is prevented from being pulled to a low potential, and the working stability of the logic circuit is ensured; the fourth resistor R14 and the fifth resistor R19 are respectively connected with the fourth end of the third optocoupler U2, the fourth end of the fourth optocoupler U5 and a voltage port VCC, so that the current limiting effect is realized, the secondary sides of the third optocoupler U2 and the fourth optocoupler U5 can be completely conducted, and the working stability of the logic circuit is improved; the sixth resistor R22 and the seventh resistor R16 are respectively connected in parallel between the gate and source electrodes of the first MOS transistor Q2 and the gate and source electrode of the second MOS transistor Q1, so that the MOS transistors can be stably cut off, and the working stability of the logic circuit is improved.
Furthermore, the two-bit input logic control circuit further comprises an output conversion circuit;
the output conversion circuit includes: a first chip MA24, a tenth resistor R2, an eleventh resistor R11, a twelfth resistor R3, a thirteenth resistor R9, and a fourteenth resistor R10;
a first input pin of the first chip MA24 is connected with a first input power supply VI +;
a second input pin of the first chip MA24 is connected with the second port G2 and a second input power supply VI-;
an enable pin of the first chip MA24 is connected to the first port CTR;
a first output pin of the first chip MA24 is connected with a first end of a tenth resistor R2 and an output positive terminal VO +;
the second output pin of the first chip MA24 is connected to the first end of the eleventh resistor R11 and the negative output terminal VO —;
a forward adjustment pin of the first chip MA24 is connected to a second end of the tenth resistor R2 and a first end of the twelfth resistor R3;
a third output pin of the first chip MA24 is connected to the second end of the twelfth resistor R3, the first end of the thirteenth resistor R9, and the first end of the fourteenth resistor R10;
a reverse regulation pin of the first chip MA24 is connected to the fourth port S-and a second end of the eleventh resistor R11;
a second end of the thirteenth resistor R9 is connected to the fifth port 28 VTZ;
a second end of the fourteenth resistor R10 is connected to the third port 24 VTZ.
The utility model provides an output conversion circuit, when logic circuit formed first output result, third port 24VTZ and fourth port S-short circuit, fourteenth resistance R10 establishes ties between first chip MA24 ' S third output pin and reverse regulation pin, makes first chip MA24 ' S first output pin ' S output voltage reduced, obtains first output voltage; when the logic circuit forms a second output result, the first port CTR to the fifth port 28VTZ are suspended, and only the twelfth resistor R3 is connected in series between the forward direction adjustment pin and the third output pin, so that the first output pin of the first chip MA24 outputs a second output voltage; when the logic circuit forms a third output result, the thirteenth resistor R9 is connected in series between the third output pin of the first chip MA24 and the reverse adjustment pin, so that the output voltage of the first output pin of the first chip MA24 is reduced to obtain a third output voltage; when the logic circuit forms a third output result, the first port CTR and the second port G2 are short-circuited, and the enable pin of the first chip MA24 is short-circuited with the second input pin, so that the first chip MA24 stops working and outputs a fourth output voltage or 0 voltage. The utility model discloses an output conversion circuit is connected with first chip MA24 through making tenth resistance R2 to fourteenth resistance R10, realizes turning into four kinds of output voltage results with logic circuit's four kinds of output results.
Further, the output conversion circuit further includes: a fifteenth resistor R4, a sixteenth resistor R5, a seventeenth resistor R6, an eighteenth resistor R7, and a nineteenth resistor R8;
a first end of the fifteenth resistor R4 is connected to a second end of the tenth resistor R2, a first end of the twelfth resistor R3 and a forward adjustment pin of the first chip MA 24;
a second end of the fifteenth resistor R4 is connected to the third output pin of the first chip MA24, the first end of the sixteenth resistor R5, the first end of the seventeenth resistor R6, the first end of the eighteenth resistor R7, and the first end of the nineteenth resistor R8;
a second end of the sixteenth resistor R5 is connected to a first end of the thirteenth resistor R9 and a second end of the seventeenth resistor R6;
a second end of the eighteenth resistor R7 is connected to a first end of the fourteenth resistor R10 and a second end of the nineteenth resistor R8.
This use neotype fifteenth resistance R4 to nineteenth resistance R8 and twelfth resistance R3 to fourteenth resistance R10 to connect in parallel or concatenate, make the voltage regulating resistance who connects between the forward direction regulation pin of first chip MA24 and third output pin and the voltage regulating resistance between reverse direction regulation pin and the third output pin can be set for different numerical values, realize that the first output pin of first chip MA24 exports different output voltage results.
In this embodiment, the twelfth resistor R3 and the fifteenth resistor R4 are disposed in parallel between the forward adjustment pin and the third output pin of the first chip MA24 to serve as voltage regulation resistors, and the smaller the resistances of the twelfth resistor R3 and the fifteenth resistor R4 are, the larger the output voltage rising amplitude is, and the voltage rising limit can be adjusted to the upper limit of the voltage output by the first chip M24. The voltage regulating resistor between the third port 24VTZ and the third output pin of the first chip MA24 and the voltage regulating resistor between the fifth port 28VTZ and the third output pin of the first chip MA24 are connected to the reverse regulation pin of the first chip MA24 through the second end of the thirteenth resistor R9 and the second end of the fourteenth resistor R10, so that the smaller the resistance values of the two types of voltage regulating resistors are, the larger the down-regulation amplitude of the output voltage is; if the output second output voltage is set to be 32V, namely the output voltage of 32V is taken as an initial state, the voltage regulating resistor corresponding to the third port 24VTZ and the voltage regulating resistor corresponding to the fifth port 28VTZ both regulate the first output voltage and the third output voltage to be below 32V. In addition, if the reverse regulation pin is changed to be the forward regulation pin, the twelfth resistor R3 and the fifteenth resistor R4 can be connected in parallel to be connected to the reverse regulation pin, and any voltage output from the first chip MA24 can be used as an initial state.
Further, the output conversion circuit further includes: a first capacitor C8, a second capacitor C3, a third capacitor C4, a fourth capacitor C5 and a fifth capacitor C6;
a first terminal of the first capacitor C8 is connected to an enable pin of the first chip MA24 and the first port CTR;
a second terminal of the first capacitor C8 is connected to a second input pin of the first chip MA24, the second port G2, and a second input power VI-;
a first end of the second capacitor C3 is connected to a first end of the tenth resistor R2, the first output pin of the first chip MA24, the positive output terminal VO +, a first end of the third capacitor C4, a first end of the fourth capacitor C5, and a first end of the fifth capacitor C6;
a second end of the second capacitor C3 is connected to a first end of the eleventh resistor R11, the second output pin of the first chip MA24, the negative output terminal VO-, a second end of the third capacitor C4, a second end of the fourth capacitor C5, and a second end of the fifth capacitor C6.
The utility model provides a first electric capacity C8 concatenates between the enable pin and the second input pin of first chip MA24, and the peak of the signal that can the transmission of the first port CTR of filtering prevents that the module mistake from opening or the mistake from turn-offeing, improves the stability of circuit work.
Further, the output conversion circuit further includes: a first inductor L1, a sixth capacitor C7, a seventh capacitor C1 and an eighth capacitor C2;
a first end of the sixth capacitor C7 is connected to the first input power VO + and a first end of the first inductor L1;
a second end of the first inductor L1 is connected to a first end of the seventh capacitor C1, a first end of the eighth capacitor C2, and a first input pin of the first chip MA 24;
a second terminal of the sixth capacitor C7 is connected to the second input power VO-, a second terminal of the seventh capacitor C1, a second terminal of the eighth capacitor C2, the second port G2, and a second input pin of the first chip MA 24.
The utility model provides a first inductance L1 is connected with sixth electric capacity C7 to eighth electric capacity C2, constitutes filter circuit to make first chip MA 24's first input pin and second input pin receive stable signal.
Furthermore, the logic control circuit with the two-bit input also comprises a power supply circuit;
the power supply circuit includes: the second chip KA24, a twentieth resistor R1, a twenty-first resistor R12 and a ninth capacitor C11;
a first input pin of the second chip KA24 is connected with the first input power supply VI +;
a second input pin of the second chip KA24 is connected with the second input power supply VI < - >;
a first output pin of the second chip KA24 is connected with a first end of the twentieth resistor R1, a first end of the ninth capacitor C11 and the voltage port VCC;
a second output pin of the second chip KA24 is connected with a first end of the twenty-first resistor R12, a second end of the ninth capacitor C11 and the output negative terminal VO-;
the third output pin TRM of the second chip KA24 is connected to the second end of the twentieth resistor R1 and the second end of the twenty-first resistor R12.
In this embodiment, the third output pin of the second chip KA24 is connected to the first output pin and the second output pin of the second chip KA24 through the twentieth resistor R1 and the twenty-first resistor R12, and therefore the first output pin outputs a stable voltage to the voltage port VCC, thereby improving the working stability of the logic circuit.
In this embodiment, the output voltage of the first output pin of the second chip KA24 can be stabilized at 5V.
Further, the power supply circuit further includes: a second inductor L2, a tenth capacitor C9 and an eleventh capacitor C10;
a first end of the second inductor L2 is connected to the first end of the first input power VI + and the first end of the tenth capacitor C9;
a second end of the second inductor L2 is connected to a first input pin of the second chip KA24 and a first end of the eleventh capacitor C10;
a second end of the tenth capacitor C9 is connected to the second input power VI-, the second input pin of the second chip KA24, and a second end of the eleventh capacitor C10.
The utility model provides a second inductance L2 is connected with tenth electric capacity C9 and eleventh electric capacity C10, constitutes filter circuit to make second chip KA 24's first input pin and second input pin receive stable signal, and then promote the stability of logic circuit work.
Further, the output negative terminal VO-is connected to circuit ground.
In this embodiment, the two-bit input four output results are logically controlled by an optocoupler, an MOS transistor and a stabilivolt in the logic circuit, and in each output result, each port realizes different states, including: suspended and short-circuited with other ports; the logic circuit in the embodiment realizes the logic control circuit with two-bit input through hardware, has lower cost than a software-controlled logic circuit, is simple and convenient to use, and further has higher stability; a first chip MA24 in the output conversion circuit is connected with the voltage regulating resistor, and converts different states of each port into output voltage results or outputs four different voltages; the second chip KA24 in the power supply circuit is connected with the filter circuit, the twentieth resistor R1 and the twenty-first resistor R12, stable voltage is provided for the logic circuit, and the working stability of the circuit is improved.
The above-mentioned embodiments further describe the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and are not intended to limit the scope of the present invention. It should be understood that any modification, equivalent replacement, or improvement made by those skilled in the art without departing from the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A logic control circuit with two-bit input is characterized by comprising a logic circuit;
the logic circuit includes: the circuit comprises a first optical coupler, a second optical coupler, a third optical coupler, a fourth optical coupler, a fifth optical coupler, a first MOS (metal oxide semiconductor) tube, a second MOS tube and a first voltage regulator tube;
the first end of the first optical coupler is electrically connected with a first input signal, the second end of the first optical coupler is connected with an output negative end, the third end of the first optical coupler is connected with the fourth end of the second optical coupler, and the fourth end of the first optical coupler is connected with a first port;
a first end of the second optocoupler is electrically connected with a second input signal, a second end of the second optocoupler is connected with the output negative end, and a third end of the second optocoupler is connected with a second port;
the first end of the third optical coupler is electrically connected with the second input signal, the second end of the third optical coupler is connected with the first end of the fourth optical coupler, the third end of the third optical coupler is connected with the output negative end, and the fourth end of the third optical coupler is connected with the voltage port, the negative electrode of the first voltage-regulator tube and the fourth end of the fifth optical coupler;
a second end of the fourth optical coupler is electrically connected with the first input signal, a third end of the fourth optical coupler is connected with a grid electrode of the first MOS transistor, and a fourth end of the fourth optical coupler is connected with the voltage port;
a first end of the fifth optocoupler is electrically connected with the first input signal, a second end of the fifth optocoupler is electrically connected with the second input signal, and a third end of the fifth optocoupler is connected with the output negative end;
the anode of the first voltage-stabilizing tube is connected with the grid electrode of the second MOS tube;
the drain electrode of the second MOS tube is connected with the third port, and the source electrode of the second MOS tube is connected with the fourth port;
the drain electrode of the first MOS tube is connected with the fifth port, and the source electrode of the first MOS tube is connected with the fourth port.
2. The two-bit input logic control circuit according to claim 1, wherein the logic circuit further comprises: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a ninth resistor;
a first end of the first resistor is electrically connected with the first input signal, and a second end of the first resistor is connected with a first end of the first optocoupler;
a first end of the second resistor is electrically connected with the second input signal, and a second end of the second resistor is connected with a first end of the second optocoupler;
the first end of the third resistor is electrically connected with the second input signal, and the second end of the third resistor is connected with the first end of the third optocoupler;
a first end of the fourth resistor is connected with the voltage port, and a second end of the fourth resistor is connected with a fourth end of the third optocoupler, a negative electrode of the first voltage regulator tube and a fourth end of the fifth optocoupler;
a first end of the fifth resistor is connected with the voltage port, and a second end of the fifth resistor is connected with a fourth end of the fourth optocoupler;
the first end of the sixth resistor is connected with the grid electrode of the first MOS tube, and the second end of the sixth resistor is connected with the source electrode of the first MOS tube and the fourth port;
the first end of the seventh resistor is connected with the grid electrode of the second MOS tube and the anode of the first voltage regulator tube, and the second end of the seventh resistor is connected with the source electrode and the fourth port of the second MOS tube;
a first end of the eighth resistor is connected with a first end of the fifth optocoupler, and a second end of the eighth resistor is electrically connected with the first input signal;
and the first end of the ninth resistor is connected with the negative output terminal, and the second end of the ninth resistor is connected with the fourth port.
3. The two-bit input logic control circuit according to claim 1, further comprising an output switching circuit;
the output conversion circuit includes: the circuit comprises a first chip, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor and a fourteenth resistor;
a first input pin of the first chip is connected with a first input power supply;
a second input pin of the first chip is connected with the second port and a second input power supply;
the enabling pin of the first chip is connected with the first port;
a first output pin of the first chip is connected with a first end and an output positive end of a tenth resistor;
a second output pin of the first chip is connected with a first end of an eleventh resistor and the output negative end;
the forward adjusting pin of the first chip is connected with the second end of the tenth resistor and the first end of the twelfth resistor;
a third output pin of the first chip is connected with a second end of the twelfth resistor, a first end of the thirteenth resistor and a first end of the fourteenth resistor;
a reverse adjustment pin of the first chip is connected with the fourth port and a second end of the eleventh resistor;
a second end of the thirteenth resistor is connected with the fifth port;
a second terminal of the fourteenth resistor is connected to the third port.
4. The two-bit input logic control circuit of claim 3, wherein the output switching circuit further comprises: a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, and a nineteenth resistor;
a first end of the fifteenth resistor is connected with a second end of the tenth resistor, a first end of the twelfth resistor and a forward adjustment pin of the first chip;
a second end of the fifteenth resistor is connected with a third output pin of the first chip, a first end of the sixteenth resistor, a first end of the seventeenth resistor, a first end of the eighteenth resistor and a first end of the nineteenth resistor;
a second end of the sixteenth resistor is connected with a first end of the thirteenth resistor and a second end of the seventeenth resistor;
a second end of the eighteenth resistor is connected to a first end of the fourteenth resistor and a second end of the nineteenth resistor.
5. The two-bit input logic control circuit of claim 4, wherein the output switching circuit further comprises: the first capacitor, the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor;
the first end of the first capacitor is connected with the enabling pin of the first chip and the first port;
a second end of the first capacitor is connected with a second input pin of the first chip, the second port and a second input power supply;
the first end of the second capacitor is connected with the first end of the tenth resistor, the first output pin of the first chip, the positive output terminal, the first end of the third capacitor, the first end of the fourth capacitor and the first end of the fifth capacitor;
the second end of the second capacitor is connected with the first end of the eleventh resistor, the second output pin of the first chip, the output negative terminal, the second end of the third capacitor, the second end of the fourth capacitor and the second end of the fifth capacitor.
6. The two-bit input logic control circuit of claim 3, wherein the output switching circuit further comprises: the first inductor, the sixth capacitor, the seventh capacitor and the eighth capacitor;
a first end of the sixth capacitor is connected with the first input power supply and a first end of the first inductor;
the second end of the first inductor is connected with the first end of the seventh capacitor, the first end of the eighth capacitor and the first input pin of the first chip;
and a second end of the sixth capacitor is connected with the second input power supply, a second end of the seventh capacitor, a second end of the eighth capacitor, the second port and a second input pin of the first chip.
7. The two-bit input logic control circuit according to any one of claims 3 to 5, further comprising a power supply circuit;
the power supply circuit includes: the second chip, the twentieth resistor, the twenty-first resistor and the ninth capacitor;
a first input pin of the second chip is connected with the first input power supply;
a second input pin of the second chip is connected with the second input power supply;
a first output pin of the second chip is connected with a first end of the twentieth resistor, a first end of the ninth capacitor and the voltage port;
a second output pin of the second chip is connected with a first end of the twenty-first resistor, a second end of the ninth capacitor and the output negative end;
and a third output pin of the second chip is connected with a second end of the twentieth resistor and a second end of the twenty-first resistor.
8. The two-bit input logic control circuit of claim 7, wherein the power supply circuit further comprises: a second inductor, a tenth capacitor and an eleventh capacitor;
a first end of the second inductor is connected with the first input power supply and a first end of the tenth capacitor;
a second end of the second inductor is connected with a first input pin of the second chip and a first end of the eleventh capacitor;
a second end of the tenth capacitor is connected to the second input power supply, the second input pin of the second chip, and a second end of the eleventh capacitor.
9. The two-input logic control circuit according to claim 7, wherein the output negative terminal is connected to circuit ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222159453.1U CN218587163U (en) | 2022-08-16 | 2022-08-16 | Logic control circuit with two-bit input |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222159453.1U CN218587163U (en) | 2022-08-16 | 2022-08-16 | Logic control circuit with two-bit input |
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| Publication Number | Publication Date |
|---|---|
| CN218587163U true CN218587163U (en) | 2023-03-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222159453.1U Active CN218587163U (en) | 2022-08-16 | 2022-08-16 | Logic control circuit with two-bit input |
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| Country | Link |
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| CN (1) | CN218587163U (en) |
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2022
- 2022-08-16 CN CN202222159453.1U patent/CN218587163U/en active Active
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