CN218470966U

CN218470966U - Detection device for transimpedance amplifier chip, photoelectric receiving device and laser radar

Info

Publication number: CN218470966U
Application number: CN202222621587.0U
Authority: CN
Inventors: 崔少华; 夏冰冰; 石拓
Original assignee: Zvision Technologies Co Ltd
Current assignee: Zvision Technologies Co Ltd
Priority date: 2022-09-29
Filing date: 2022-09-29
Publication date: 2023-02-10
Anticipated expiration: 2032-09-29

Abstract

The application discloses detection device, optoelectronic receiving arrangement of trans-impedance amplifier (TIA) chip, the detection device of TIA chip includes: the circuit comprises a TIA chip, a first sampling resistor, an analog-to-digital converter (ADC) for sampling voltage of the TIA chip and a Field Programmable Gate Array (FPGA) for detecting abnormity of the TIA chip; the first power output end of the TIA chip, the first end of the first sampling resistor and the first input end of the ADC are connected to a first node, the second power output end of the TIA chip, the second end of the first sampling resistor and the second input end of the ADC are connected to a second node, and the first output end of the ADC is connected with the FPGA. According to the application, the abnormity detection of the TIA chip can be realized.

Description

Detection device for transimpedance amplifier chip, photoelectric receiving device and laser radar

Technical Field

The present application relates to, but not limited to, the field of laser radar technology, and in particular, to a detection apparatus for a trans-impedance amplifier (TIA) chip, a photoelectric receiving apparatus, and a laser radar.

Background

In the ranging process of the laser radar, in order to obtain a more accurate ranging result, a TIA chip is used for amplifying a current signal output by a photoelectric detector to obtain a voltage signal convenient to measure. Therefore, in the optoelectronic system of the laser radar, the TIA chip plays an important role, and directly affects the processing of the subsequent circuit.

In the current photoelectric system, the TIA chip is used as an open-loop device, and the situation that when the TIA chip breaks down, a post-stage circuit of the laser radar can stably output a ranging result cannot be guaranteed.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a detection device of a TIA chip, so as to realize abnormal detection of the TIA chip.

In a first aspect, the present application provides a TIA chip detection apparatus, including: a first sampling resistor, an analog-to-digital converter (ADC) for sampling voltage of the TIA chip, and a Field Programmable Gate Array (FPGA) for performing anomaly detection on the TIA chip; the first power output end of the TIA chip, the first end of the first sampling resistor and the first input end of the ADC are connected to a first node, the second power output end of the TIA chip, the second end of the first sampling resistor and the second input end of the ADC are connected to a second node, and the first output end of the ADC is connected with the FPGA.

In some possible embodiments, the FPGA is connected to a first output of the ADC; the FPGA is configured to calculate a first current value of the TIA chip according to the first voltage value sampled by the ADC, and determine whether the TIA chip is abnormal or not according to the first current value.

In some possible embodiments, the TIA chip further includes a reset interface, and the FPGA is connected with the TIA chip through the reset interface; the FPGA is further configured to determine that the TIA chip is abnormal when the first current value of the TIA chip is larger than a preset current value, and send a reset signal to the TIA chip through the reset interface, wherein the reset signal is used for indicating the reset restart of the TIA chip.

In some possible embodiments, the TIA chip further includes a configuration interface; the FPGA is further configured to determine whether the TIA chip is abnormal according to the first current value after the TIA chip is abnormal; and when the first current value of the TIA chip is smaller than or equal to the preset current value, sending a configuration signal to the TIA chip, wherein the configuration signal is used for configuring the TIA chip.

In some possible embodiments, the FPGA is connected to the upper computer; and the FPGA is also configured to determine that the times of abnormity of the TIA chip are greater than a preset threshold value, and send alarm information to the upper computer through a fifth output end of the FPGA, wherein the alarm information is used for indicating that the TIA chip is damaged.

In some possible implementations, the first power output and the second power output of the TIA chip are power outputs at a first power value.

In some possible embodiments, the detection apparatus of the TIA chip further includes: and a first end of the second sampling resistor, a third power output end of the TIA chip and a third input end of the ADC are connected to a third node, a second end of the second sampling resistor, a fourth power output end of the TIA chip and a fourth input end of the ADC are connected to a fourth node, and the third power output end and the fourth power output end of the TIA chip are power output ends under a second power value.

In some possible embodiments, the detection apparatus of the TIA chip further includes: and a first end of the third sampling resistor, a fifth power output end of the TIA chip and a fifth input end of the ADC are connected to a fifth node, a second end of the third sampling resistor, a sixth power output end of the TIA chip and a sixth input end of the ADC are connected to a sixth node, and the fifth power output end and the sixth power output end of the TIA chip are power output ends under a third power value.

In some possible embodiments, the detection apparatus of the TIA chip further includes a Multiplexer (MUX), and the MUX is respectively connected to the ADC and the FPGA; and the MUX is configured to receive the second voltage value sampled by the ADC at the second power supply value through the second output end of the ADC, receive the third voltage value sampled by the ADC at the third power supply value through the third output end of the ADC, receive a control instruction from the FPGA through the seventh input end of the MUX, and output a target voltage value to the FPGA through the fourth output end of the MUX according to the control instruction, wherein the target voltage value corresponds to the control instruction.

In some possible embodiments, the first output terminal, the second output terminal, and the third output terminal of the ADC are Serial Peripheral Interface (SPI).

In a second aspect, the present application provides a photoelectric receiving apparatus, for use in a laser radar, the photoelectric receiving apparatus comprising: a detection apparatus for a TIA chip as in the first aspect and any possible implementation thereof.

In a third aspect, the present application provides a lidar comprising: a detection apparatus for a TIA chip as in the first aspect and any possible implementation thereof.

Compared with the prior art, the technical scheme provided by the application has the beneficial effects that:

in this application, through set up ADC in the detection device of TIA chip and carry out voltage sampling to the TIA chip and set up FPGA and carry out abnormal detection to the TIA chip, can in time discover TIA chip unusual, avoid leading to laser radar range finding result to appear the mistake because TIA chip is unusual to FPGA has the fast advantage of reaction time as the master control device in the TIA chip.

In addition, the abnormity detection function, the reset function and the configuration function are all configured in the FPGA, so that the detection device of the TIA chip does not need to be provided with other devices for configuring extra information transmission and handshake signals, and the detection device of the TIA chip has a simpler structure and is easier to operate.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the scope of the application.

Drawings

Fig. 1 is a schematic structural diagram of a lidar in the related art;

fig. 2 is a first structural diagram of a detection apparatus of a TIA chip in an embodiment of the present application;

fig. 3 is a second structural diagram of a detection apparatus for a TIA chip in an embodiment of the present application;

fig. 4 is a schematic diagram of a third structure of a detection apparatus for a TIA chip in an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

In order to explain the technical means of the present application, the following description will be given by way of specific examples.

LiDAR (light detection and ranging) is a target detection technology. The laser radar emits laser beams through the laser, the laser beams are subjected to diffuse reflection after encountering a target object, the reflected beams are received through the detector, and characteristic quantities such as the distance, the direction, the height, the speed, the posture and the shape of the target object are determined according to the emitted beams and the reflected beams.

The application field of laser radars is very wide. In addition to military applications, it is now widely used in the field of life, including but not limited to: the field of intelligent piloted vehicles, intelligent piloted aircraft, three-dimensional (3D) printing, virtual reality, augmented reality, service robots, and the like. Taking the intelligent driving technology as an example, a laser radar is arranged in an intelligent driving vehicle, and the laser radar can scan the surrounding environment by rapidly and repeatedly emitting laser beams to acquire point cloud data and the like reflecting the appearance, position and motion of one or more target objects in the surrounding environment.

The intelligent driving technology may refer to unmanned driving, automatic driving, assisted driving, and the like.

Fig. 1 is a schematic structural diagram of a lidar in the related art. As shown in fig. 1, lidar 10 may include: a light emitting device 101, a light receiving device 102, and a processor 103. The light emitting device 101 and the light receiving device 102 are both connected to the processor 103.

The connection relationship among the above devices may be electrical connection or optical fiber connection. More specifically, in the light emitting device 101 and the light receiving device 102, it is also possible to include a plurality of optical devices, respectively, and the connection relationship between these optical devices may also be spatial light transmission connection.

The processor 103 is used to implement control of the light emitting device 101 and the light receiving device 102 so that the light emitting device 101 and the light receiving device 102 can operate normally. For example, the processor 103 may provide driving voltages for the light emitting device 101 and the light receiving device 102, respectively, and the processor 103 may also provide control signals for the light emitting device 101 and the light receiving device 102.

Illustratively, the processor 103 may be a general-purpose processor, such as a Central Processing Unit (CPU), a Network Processor (NP), or the like; the processor 103 may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like.

A light source (not shown in fig. 1) is also included in the light emitting device 101. It is understood that the light source may refer to a laser, and the number of lasers may be one or more. Alternatively, the laser may specifically include a Pulsed Laser Diode (PLD), a semiconductor laser, a fiber laser, and the like. The light source is used for emitting laser beams. In particular, the processor 103 may send an emission control signal to the light source, thereby triggering the light source to emit the laser beam.

It will be appreciated that the laser beam may also be referred to as a laser pulse, a laser, an emitted beam, etc.

The light receiving device 102 generally employs a photodiode (e.g., an Avalanche Photodiode (APD), a silicon photomultiplier (SiPM), etc.) as a detector to receive the echo light beam and perform photoelectric conversion. In practical application, the laser radar can adopt a detector array to improve the echo receiving efficiency and improve the performance.

Lidar 10 may further include: one or more beam shaping optics and a beam scanning apparatus (not shown in fig. 1). In one aspect, beam shaping optics and a beam scanning device focus and project a laser beam toward a particular location (e.g., a target object) in a surrounding environment. In another aspect, a beam scanning device and one or more beam shaping optics direct and focus the return beam onto a detector. A beam scanning device is employed in the optical path between the beam-shaping optical element and the target object. The beam scanning arrangement actually expands the field of view and increases the sampling density within the field of view of the lidar.

The following briefly describes the detection process of the object 104 to be measured by the lidar, with reference to the structure of the lidar shown in fig. 1.

Referring to fig. 1, the laser beam propagates in the emitting direction, and when the laser beam encounters the object 104 to be measured, the laser beam is reflected on the surface of the object 104 to be measured, and the reflected beam is received by the light receiving device 102 of the laser radar. The beam of the laser beam reflected back by the object 104 to be measured may be referred to herein as an echo beam (the laser beam and the echo beam are indicated by solid lines in fig. 1).

After receiving the echo light, the light receiving device 102 performs photoelectric conversion on the echo light, that is, the echo light is converted into an electrical signal, the light receiving device 102 outputs the electrical signal corresponding to the echo light to the processor 103, and the processor 103 can obtain the point cloud data of the shape, position, motion, and the like of the object 104 to be measured according to the electrical signal of the echo light.

In practical application, a photoelectric receiving device of the laser radar receives a reflected echo light beam, the echo light beam converts an optical signal into a current signal through an APD (avalanche photo diode), an SiPM (silicon oxide semiconductor) and the like, a photoelectric detector outputs the current signal, a TIA (TIA) chip processes the current signal to obtain an amplified voltage signal, and the amplified voltage signal is easy to detect. In the current photoelectric receiving device, the TIA chip is an open-loop device, and there is no corresponding monitoring and protecting device, so when the TIA chip in the photoelectric receiving device is abnormal, the calculation of the subsequent-stage ranging information may be affected, resulting in an error in the final ranging result. For example, when a large signal arrives temporarily, the abnormal TIA chip cannot work normally, and the subsequent circuit still recognizes the signal as a valid small signal, so that the final ranging result is incorrect. Therefore, how to identify the abnormality of the TIA chip is a problem to be solved for ensuring the stable output of the ranging result by the subsequent circuit.

In order to solve the above problem, an embodiment of the present application provides a detection apparatus for a TIA chip, which may be disposed in the laser radar.

Then, fig. 2 is a schematic diagram of a first structure of a detection apparatus for a TIA chip in an embodiment of the present application, and referring to fig. 2, the detection apparatus 20 for a TIA chip may include: a first sampling resistor 22, an analog-to-digital converter (ADC) 23 for sampling a voltage of the TIA chip 21 to be detected, an FPGA24 for performing abnormality detection on the TIA chip 21, a reset interface 25, and a configuration interface 26; the first sampling resistor 22 is connected to the TIA chip 21 and the ADC23, specifically, a first power output terminal of the TIA chip 21, a first end of the first sampling resistor 22 and a first input terminal of the ADC23 are connected to the first node A1, a second power output terminal of the TIA chip 21, a second end of the first sampling resistor 22 and a second input terminal of the ADC23 are connected to the second node A2, and a first output terminal of the ADC23 is connected to the FPGA24, where the first power output terminal and the second power output terminal of the TIA chip are power output terminals under a first power value.

In one possible embodiment, the FPGA is connected to a first output of the ADC; and the FPGA can be configured to calculate a first current value of the TIA chip according to the first voltage value sampled by the ADC, and determine whether the TIA chip is abnormal or not according to the first current value.

As can be appreciated, the FPGA and the ADC are connected to the first output terminal of the ADC, and the FPGA is configured to calculate an operating current (i.e., a first current value) of the TIA chip according to a voltage value (i.e., a first voltage value) of the TIA chip collected by the ADC.

In an embodiment, after the TIA chip converts a current signal of the photodetector into a voltage signal and amplifies the voltage signal, the voltage signal is processed by the first sampling resistor, the ADC receives the voltage signal through the first input terminal and the second input terminal, and converts the voltage signal into a numerical signal (namely, performs voltage sampling on the TIA chip), after the ADC performs voltage sampling, the voltage signal is output to the FPGA through the first output terminal of the ADC, and the FPGA calculates the operating current of the TIA chip according to the voltage signal. The formula (1) for calculating the working current of the TIA chip by the FPGA is as follows:

in the formula, I is the operating current of the TIA chip, VDD1 is the voltage value of the first power output end of the TIA chip, VDD2 is the voltage value of the second power output end of the TIA chip, and R1 is the resistance value of the first sampling resistor.

The VDD1-VDD2 is calculated according to the sampling voltage value of the FPGA and the voltage amplification factor of the TIA chip, and the calculation process is as the formula (2):

in the formula, V _current And T is the voltage amplification factor of the TIA chip.

For example, the first power supply value of the first power supply output end and the second power supply output end of the TIA chip may be 1.8V, the resistance value of the first sampling resistor may be 10 Ω, and the amplification factor of the TIA chip may be 100. Of course, according to different performances of the TIA chip, the resistance value of the first sampling resistor and the amplification factor of the TIA chip may also be other values, which is not specifically limited in this embodiment of the present application.

In a possible implementation manner, the TIA chip may further include a reset interface, and the FPGA is connected to the TIA chip through the reset interface; the FPGA can be further configured to determine that the TIA chip is abnormal when the first current value of the TIA chip is larger than a preset current value, and send a reset signal to the TIA chip through the reset interface, wherein the reset signal is used for indicating the reset restart of the TIA chip.

It will be appreciated that, as shown in figure 2, the TIA chip 21 is connected to the FPGA24 via a reset interface 25. After calculating the working current of the TIA chip 21, the FPGA24 determines whether the working current of the TIA chip 21 is greater than a preset current value (for example, 100 mA), if the working current of the TIA chip 21 is greater than the preset current value, it indicates that the TIA chip 21 has a fault, the FPGA24 sends a reset signal to the TIA chip 21 through the reset interface 25, and after receiving the reset signal, the TIA chip 21 resets and restarts; if the working current of the TIA chip 21 is smaller than the preset current value, it is indicated that the TIA chip 21 does not malfunction.

In a possible implementation manner, the TIA chip may further include a configuration interface, and the FPGA may be further configured to determine whether the TIA chip is abnormal according to the first current value after the TIA chip is abnormal; and when the first current value of the TIA chip is smaller than or equal to the preset current value, the TIA chip sends a configuration signal, and the configuration signal is used for configuring the TIA chip.

It can be understood that, referring to fig. 2, the TIA chip 21 may further be connected to the FPGA24 through a configuration interface 26, where the FPGA24 is configured to perform reset and restart after the TIA chip 21 receives a reset signal sent to the TIA chip 21 through the reset interface 25, and the FPGA24 sends a configuration signal to the TIA chip 21 through the configuration interface 26, where the configuration signal is used to instruct the TIA chip 21 to perform initialization configuration.

In one possible implementation mode, the FPGA is connected with an upper computer; the FPGA can also be configured to determine that the times of abnormity of the TIA chip are larger than a preset threshold value, and send alarm information to the upper computer through a fifth output end of the FPGA, wherein the alarm information is used for indicating that the TIA chip is damaged.

It can be understood that FPGA can also be connected with the host computer, and FPGA is configured as when confirming TIA chip is unusual, records TIA chip's unusual number of times, specifically speaking, FPGA confirms TIA chip is unusual for the first time, and the count is 1, later every time TIA chip takes place unusually, all adds 1 operation to the count value, and when the count value was greater than predetermined threshold value, FPGA sent alarm information to the host computer through the fifth output. It should be noted that after the FPGA sends the alarm information to the upper computer, when it is determined that the TIA chip is abnormal next time, the counting is started from 1.

In some possible embodiments, in the detection device of the TIA chip, one sampling resistor may be used to complete abnormality detection on the TIA chip, and in order to make a detection result more accurate, at least one group of sampling resistors may be further provided in the detection device of the TIA chip to sample other power supply voltages of the TIA chip.

In one possible implementation, the detection apparatus of the TIA chip may further include: and a first end of the second sampling resistor, a third power output end of the TIA chip and a third input end of the ADC are connected to a third node, a second end of the second sampling resistor, a fourth power output end of the TIA chip and a fourth input end of the ADC are connected to a fourth node, and the third power output end and the fourth power output end of the TIA chip are power output ends under a second power value.

It can be understood that fig. 3 is a second structural schematic diagram of the detection apparatus of the TIA chip in the embodiment of the present application, and referring to fig. 3, the detection apparatus 20 of the TIA chip may further include a second sampling resistor 31, where the second sampling resistor 31 is connected to the TIA chip 21 and the ADC23, specifically, a third power output terminal of the TIA chip 21 and a first end of the second sampling resistor 22 and a third input terminal of the ADC23 are connected to a third node A3, and a fourth power output terminal of the TIA chip 21 and a second end of the second sampling resistor 22 and a fourth input terminal of the ADC23 are connected to a fourth node A4.

For example, the second power value of the third power output terminal and the fourth power output terminal of the TIA chip may be 2.5V, and of course, other power values may also be used, which is not specifically limited in this embodiment of the application.

In one possible implementation, the detection apparatus of the TIA chip may further include: and a first end of the third sampling resistor, a fifth power output end of the TIA chip and a fifth input end of the ADC are connected to a fifth node, a second end of the third sampling resistor, a sixth power output end of the TIA chip and a sixth input end of the ADC are connected to a sixth node, and the fifth power output end and the sixth power output end of the TIA chip are power output ends under a third power value.

It can be understood that, referring to fig. 3, the detection apparatus 20 of the TIA chip further includes a third sampling resistor 32, where the third sampling resistor 32 is connected to the TIA chip 21 and the ADC23, specifically, the fifth power output terminal of the TIA chip 21 and the first end of the third sampling resistor 32 and the fifth input terminal of the ADC23 are connected to the fifth node A3, and the sixth power output terminal of the TIA chip 21 and the second end of the third sampling resistor 32 and the sixth input terminal of the ADC23 are connected to the sixth node A6.

For example, the third power supply value of the fifth power supply output end and the sixth power supply output end of the TIA chip may be the large-current drain channel voltage.

It should be noted that, the TIA chip in the embodiment of the present disclosure may include, but is not limited to, the first power output end and the second power output end corresponding to the first power value, the third power output end and the fourth power output end corresponding to the second power value, and the fifth power output end and the sixth power output end corresponding to the third power value, which are described above, and may further include other power output ends corresponding to different power values. Further, the sampling resistors in the embodiments of the present disclosure may also include, but are not limited to, the first sampling resistor, the second sampling resistor, and the third sampling resistor, and may also include other sampling resistors, where different sampling resistors correspond to different power supply values.

In a possible implementation manner, the detection apparatus of the TIA chip may further include a MUX, where the MUX is connected to the ADC and the FPGA, respectively; and the MUX can be configured to receive the second voltage value sampled by the ADC at the second power supply value through the second output end of the ADC, receive the third voltage value sampled by the ADC at the third power supply value through the third output end of the ADC, receive a control instruction from the FPGA through the seventh input end of the MUX, and output a target voltage value to the FPGA through the fourth output end of the MUX according to the control instruction, wherein the target voltage value corresponds to the control instruction.

It can be understood that, in the detection apparatus of a TIA chip including three sampling resistors, a MUX may further be included, fig. 4 is a third schematic structural diagram of the detection apparatus of a TIA chip in this embodiment, referring to fig. 4, a MUX41 may further be connected between the ADC23 and the FPGA24, and the MUX41 is configured to output a target voltage value to the FPGA24 according to a control instruction from the FPGA. Specifically, after receiving the first voltage value of the first sampling resistor 22, the second voltage value of the second sampling resistor 31, and the third voltage value of the third sampling resistor 32, the ADC23 outputs the first voltage value to the FPGA24 through the first output terminal of the ADC23, outputs the second voltage value to the MUX41 through the second output terminal of the ADC23, and outputs the third voltage value to the MUX41 through the third output terminal of the ADC23, and the MUX41 selects one or more of the second voltage value and the third voltage value to be output to the FPGA24 according to a control instruction from the FPGA.

It should be noted that the first output terminal, the second output terminal, and the third output terminal of the ADC are all SPI interfaces.

For example, the clock frequency of the SPI interface in the embodiment of the present application may be, but is not limited to, 20MHz, the sampling data may be, but is not limited to, 16 bits (bits), and the time required for sampling the voltage in one light receiving channel may be, but is not limited to, 800ns, which is not specifically limited in this embodiment of the present application.

The structure of the detection apparatus for a TIA chip and the operation mode of each device in the detection apparatus for a TIA chip will be specifically described below with specific examples.

In an embodiment, it is assumed that the detection device of the TIA chip includes a TIA chip, a sampling resistor, an ADC, and an FPGA, where a first power value of the TIA chip is 1.8v, an amplification factor of the TIA chip is 100, a resistance value of the sampling resistor is 10 Ω, a preset threshold of the FPGA is 50, a number of times of occurrence of an abnormality of the TIA chip is smaller than the preset threshold, and a preset current value is 100mA. This will be explained in detail with reference to fig. 2.

Illustratively, in the working process of the TIA chip 21, a voltage signal amplified by the TIA chip 21 passes through the first sampling resistor 22 (i.e., the sampling resistor corresponding to the first power supply value), and is input into the ADC23 through the first sampling resistor 22, the ADC23 performs voltage sampling on the first sampling resistor 22, and outputs the first voltage value to the FPGA24 through the first output end, and the FPGA24 calculates a first current value (i.e., the working current of the TIA chip 21) corresponding to the first voltage value according to the formula (1) and the formula (2). When the FPGA24 determines that the first current value is greater than 100mA, the FPGA24 determines that the TIA chip 21 is abnormal, further, the number of times that the FPGA24 determines that the TIA chip 21 is abnormal is less than 50, at this time, the FPGA24 sends a reset signal to the TIA chip 21 through the reset interface 25, the TIA chip 21 responds to the reset signal to restart, after the TIA chip 21 is reset and restarted, the FPGA24 sends a configuration signal to the TIA chip 21 through the configuration interface 26, and the configuration signal indicates the TIA chip to be reconfigured.

In another embodiment, it is assumed that the detection device of the TIA chip includes a TIA chip, three sampling resistors, an ADC, a MUX and an FPGA, where a first power value of the TIA chip is 1.8V, a second power value is 2.5V, a third power value is a large-current drain channel voltage, an amplification factor of the TIA chip is 100, the three sampling resistors are all 10 Ω, a preset threshold of the FPGA is 50, the number of times of abnormality occurrence of the TIA chip is greater than the preset threshold, and the preset current value is 100mA. This will be explained in detail with reference to fig. 4.

Illustratively, in the working process of the TIA chip 21, a voltage signal amplified by the TIA chip 21 passes through the first sampling resistor 22 (i.e., the sampling resistor corresponding to the first power value), the second sampling resistor 31 (i.e., the sampling resistor corresponding to the second power value), and the third sampling resistor 32 (i.e., the sampling resistor corresponding to the third power value), and then is input to the ADC23 through the three sampling resistors, respectively, the ADC23 performs voltage sampling on the first sampling resistor 22, the second sampling resistor 31, and the third sampling resistor 32, and directly outputs the first voltage value of the first sampling resistor 22 to the FPGA24 through the first output end, and outputs the second voltage value of the second sampling resistor 31 and the third voltage value of the third sampling resistor 32 to the MUX41 through the second output end and the third output end, respectively. The MUX41 selectively outputs the second voltage value of the second sampling resistor 31 and the third voltage value of the third sampling resistor 32 to the FPGA24 according to a control instruction of the FPGA24. The FPGA24 calculates a first current value, a second current value, and a third current value corresponding to the first voltage value, the second voltage value, and the third voltage value, respectively, according to the formula (1) and the formula (2). When the FPGA24 determines that at least one current value is larger than 100mA, the FPGA24 determines that the TIA chip 21 is abnormal, further, the times that the FPGA24 determines that the TIA chip 21 is abnormal are larger than 50, at the moment, the FPGA24 sends an alarm signal to the upper computer 33, and the alarm signal is used for indicating the replacement of the TIA chip 21.

In the embodiment of the application, the ADC is arranged in the detection device of the TIA chip to perform voltage sampling on the TIA chip and the FPGA is arranged to perform abnormity detection on the TIA chip, so that abnormity of the TIA chip can be found in time, errors of a laser radar ranging result caused by abnormity of the TIA chip can be avoided, and the FPGA serves as a main control device in the TIA chip and has the advantage of being fast in reaction time.

Based on the same inventive concept, the embodiment of the present application provides a photo-electric receiving device, which is applied to a laser radar and includes a detection device of a TIA chip as described in one or more embodiments above.

Based on the same inventive concept, the embodiment of the present application provides a lidar including a detection device of a TIA chip as described in one or more embodiments above.

The FPGA in the TIA chip detection device may be disposed in the optoelectronic receiving device of the laser radar, or may be disposed in the processor of the laser radar.

The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A detection device for a TIA chip of a transimpedance amplifier is characterized by comprising the following components: the device comprises a first sampling resistor, an analog-to-digital converter (ADC) for sampling voltage of a TIA chip and a Field Programmable Gate Array (FPGA) for performing exception detection on the TIA chip; wherein the content of the first and second substances,

the first power output end of the TIA chip, the first end of the first sampling resistor and the first input end of the ADC are connected to a first node, the second power output end of the TIA chip, the second end of the first sampling resistor and the second input end of the ADC are connected to a second node, and the first output end of the ADC is connected with the FPGA.

2. The apparatus of claim 1, wherein the FPGA is coupled to the first output of the ADC;

the FPGA is configured to calculate a first current value of the TIA chip according to the first voltage value sampled by the ADC, and determine whether the TIA chip is abnormal or not according to the first current value.

3. The apparatus of claim 2, wherein the TIA chip further comprises a reset interface;

the FPGA is further configured to determine that the TIA chip is abnormal when the first current value of the TIA chip is larger than a preset current value, and send a reset signal to the TIA chip through the reset interface, wherein the reset signal is used for indicating reset restart of the TIA chip.

4. The apparatus of claim 2, wherein the TIA chip further comprises a configuration interface;

the FPGA is further configured to determine whether the TIA chip is abnormal or not according to the first current value after the TIA chip is abnormal; and when the first current value of the TIA chip is smaller than or equal to a preset current value, sending a configuration signal to the TIA chip, wherein the configuration signal is used for configuring the TIA chip.

5. The device of claim 2, wherein the FPGA is connected to an upper computer;

the FPGA is further configured to determine that the times of abnormity of the TIA chip are larger than a preset threshold value, and send alarm information to the upper computer, wherein the alarm information is used for indicating that the TIA chip is damaged.

6. The apparatus of claim 1, wherein the first power output and the second power output of the TIA chip are power outputs at a first power value.

7. The apparatus of claim 1, further comprising: and a first end of the second sampling resistor, a third power output end of the TIA chip and a third input end of the ADC are connected to a third node, a second end of the second sampling resistor, a fourth power output end of the TIA chip and a fourth input end of the ADC are connected to a fourth node, and the third power output end and the fourth power output end of the TIA chip are power output ends under a second power value.

8. The apparatus of claim 7, further comprising: the first end of the third sampling resistor, the fifth power output end of the TIA chip and the fifth input end of the ADC are connected to a fifth node, the second end of the third sampling resistor, the sixth power output end of the TIA chip and the sixth input end of the ADC are connected to a sixth node, and the fifth power output end of the TIA chip and the sixth power output end are power output ends under a third power value.

9. The apparatus of claim 8, further comprising a multiplexer MUX, wherein the MUX is respectively connected to the ADC and the FPGA;

the MUX is configured to receive a second voltage value sampled by the ADC at a second power supply value through a second output end of the ADC, receive a third voltage value sampled by the ADC at a third power supply value through a third output end of the ADC, receive a control instruction from the FPGA through a seventh input end of the MUX, and output a target voltage value to the FPGA through a fourth output end of the MUX according to the control instruction, wherein the target voltage value corresponds to the control instruction.

10. The apparatus of claim 9, wherein the first output, the second output, and the third output of the ADC are a Serial Peripheral Interface (SPI).

11. A photoelectric receiving device applied to a laser radar is characterized by comprising: a detection apparatus for a transimpedance amplifier, TIA, chip as claimed in any of claims 1 to 10.

12. A lidar, comprising: the detection device of a TIA chip as claimed in any of claims 1 to 10.