CN218450105U - IO signal conversion circuit and IO data acquisition card - Google Patents
IO signal conversion circuit and IO data acquisition card Download PDFInfo
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- CN218450105U CN218450105U CN202122198489.6U CN202122198489U CN218450105U CN 218450105 U CN218450105 U CN 218450105U CN 202122198489 U CN202122198489 U CN 202122198489U CN 218450105 U CN218450105 U CN 218450105U
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Abstract
The utility model discloses a IO signal conversion circuit and IO data acquisition card, this IO signal conversion circuit includes: the input interface is used for accessing external equipment; the input end of the FPGA control chip is connected with the input interface; the PCIE interface is connected with the FPGA control chip and used for accessing an upper computer; the FPGA control chip is used for converting an IO signal input by external equipment through the input interface into a PCIE signal and outputting the PCIE signal to an upper computer through the PCIE interface; the output interface is connected with the output end of the FPGA control chip and used for accessing external equipment; the FPGA control chip is also used for converting a PCIE signal input by the upper computer through the PCIE interface into an IO signal and outputting the IO signal to external equipment through the output interface; the utility model discloses data acquisition card's time delay can be reduced.
Description
Technical Field
The utility model relates to an industrial automation technical field, in particular to IO signal conversion circuit and IO data acquisition card.
Background
Industrial automation has been rapidly developed in recent years, and the automation level of a factory is regarded as a key capability of an enterprise, so that the productivity of a unit person can be greatly improved, the requirement on skills of people can be reduced, and the safety operation level can be improved through the robot and the auxiliary operation of the machine. Data acquisition is an important part in industrial automation, and refers to automatically acquiring analog or digital signals to be measured of equipment and sending the analog or digital signals to an upper computer for analysis and processing, the modern industry requires that the delay of a digital quantity acquisition card is low, the delay of a traditional IO acquisition card is within 1ms, and the traditional IO acquisition card still cannot meet the requirements of some special industrial control scenes.
SUMMERY OF THE UTILITY MODEL
The utility model mainly aims at providing an IO signal conversion circuit, aim at reducing data acquisition card's time delay.
In order to achieve the above object, the utility model provides an IO signal conversion circuit, include:
the input interface is used for accessing external equipment;
the input end of the FPGA control chip is connected with the input interface;
the PCIE interface is connected with the FPGA control chip and used for accessing an upper computer;
the FPGA control chip is used for converting the IO signal input by the input interface into a PCIE signal and outputting the PCIE signal to an upper computer through the PCIE interface;
the output interface is connected with the output end of the FPGA control chip and is used for accessing external equipment;
the FPGA control chip is also used for converting PCIE signals input by the PCIE interface into IO signals and outputting the IO signals to external equipment through the output interface.
Optionally, the input interface includes:
the isolation input interface is used for accessing external equipment;
and the non-isolated input interface is used for accessing external equipment.
Optionally, the IO signal conversion circuit further includes:
and the isolation input circuit is arranged between the isolation input interface and the input end of the FPGA control chip in series and used for isolating the IO signal input by the external equipment and outputting the IO signal to the FPGA control chip.
Optionally, the IO signal conversion circuit further includes:
and the non-isolated input signal buffer is arranged between the non-isolated input interface and the input end of the FPGA control chip in series and is used for amplifying the IO signal input by the external equipment and outputting the IO signal to the FPGA control chip.
Optionally, the output interface includes:
the isolation output interface is used for accessing external equipment;
and the non-isolated output interface is used for accessing external equipment.
Optionally, the IO signal conversion circuit further includes:
and the isolation output circuit is serially arranged between the isolation output interface and the output end of the FPGA control chip and is used for isolating the IO signal output by the FPGA control chip and outputting the IO signal to external equipment.
Optionally, the IO signal conversion circuit further includes:
and the non-isolated output signal buffer is serially arranged between the non-isolated output interface and the output end of the FPGA control chip and is used for amplifying the IO signal output by the FPGA control chip and outputting the IO signal to external equipment.
Optionally, the IO signal conversion circuit further includes:
the input end of the first power supply conversion circuit is connected with the first power supply output end of the PCIE interface, the output end of the first power supply conversion circuit is connected with the power supply end of the FPGA control chip, and the first power supply conversion circuit is used for converting a first power supply output by an upper computer into a first power supply and supplying power to the FPGA control chip.
Optionally, the IO signal conversion circuit further includes:
and the input end of the second power conversion circuit is connected with the second power output end of the PCIE interface, the output end of the second power conversion circuit is respectively connected with the non-isolated input signal buffer and the non-isolated output signal buffer, and the second power conversion circuit is used for converting a second power output by an upper computer into a second power supply and supplying power to the non-isolated input signal buffer and the non-isolated output signal buffer.
The utility model also provides an IO data acquisition card, IO data acquisition card includes circuit board and the above-mentioned IO signal conversion circuit;
the IO signal conversion circuit is integrated on the circuit board.
The technical scheme of the utility model is through setting up input interface, output interface, FPGA control chip and PCIE interface, FPGA control chip converts the IO signal that external equipment input through input interface into the PCIE signal to export to the host computer through the PCIE interface, and convert the PCIE signal that the host computer passes through the PCIE interface input into the IO signal, and pass through output interface exports to external equipment; the utility model discloses a set up input interface, output interface, FPGA control chip and PCIE interface, realized the data transmission between host computer and the external equipment, reduced data acquisition card's time delay.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic diagram of functional modules of an embodiment of the IO signal conversion circuit of the present invention;
fig. 2 is a schematic diagram of a functional module according to an embodiment of the IO signal conversion circuit of the present invention.
The reference numbers illustrate:
the objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without making creative efforts belong to the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description relating to "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a IO signal conversion circuit.
At present, the modern industry requires low delay of a digital quantity acquisition card, the delay of a traditional I/O card is within 1ms, and the requirement of some special industrial control scenes cannot be met.
To solve the above problem, referring to fig. 1 and fig. 2, in an embodiment, the IO signal conversion circuit includes:
an input interface 30 for accessing an external device;
the input end of the FPGA control chip 10 is connected with the input interface 30;
the PCIE interface 20 is connected with the FPGA control chip 10 and used for accessing an upper computer;
the FPGA control chip 10 is configured to convert an IO signal input by an external device through the input interface 30 into a PCIE signal, and output the PCIE signal to an upper computer through the PCIE interface 20;
the output interface 40 is connected with the output end of the FPGA control chip 10, and is used for accessing an external device;
the FPGA control chip 10 is further configured to convert a PCIE signal input by the upper computer through the PCIE interface 20 into an IO signal, and output the IO signal to an external device through the output interface 40.
The data acquisition is a process of properly converting various parameters (physical quantity, chemical quantity, biomass and the like) of a measured object (outside and on site) through various sensing elements, then carrying out the steps of conditioning, sampling, quantifying, encoding, transmitting and the like, and finally sending the converted parameters to an upper computer for data processing or storage recording. In the process of communication between the data acquisition equipment and the upper computer, because the communication protocols used by the data acquisition equipment and the upper computer are different, conversion between the communication protocols is required during data transmission. In this embodiment, the communication protocol used by the upper computer is a PCIE protocol, and in this embodiment, the conversion of the communication protocol between the external device and the upper computer is implemented by the FPGA control chip 10. Specifically, the input interface 30 and the output interface 40 are used for connecting with an external device, for example, a data acquisition device such as a temperature acquisition module and a pressure acquisition module, and the data acquisition device samples and holds a temperature, voltage or current signal through a sensor, and sends the temperature, voltage or current signal to an a/D converter in the device to convert the signal into a digital signal, that is, an IO signal. The external data acquisition equipment sends the IO signal to the FPGA control chip 10 through the input interface 30, the FPGA control chip 10 converts the obtained IO signal into a PCIE signal, and then the PCIE signal is output to the upper computer through the PCIE interface 20, so that the upper computer receives the data acquired by the external data acquisition equipment and analyzes and processes the data. Conversely, the PCIE signal may also be converted into an IO signal through the FPGA control chip 10, so as to send the data or the instruction of the upper computer to the external data acquisition device, so as to implement data transmission between the upper computer and the external data acquisition device.
The traditional digital quantity acquisition card has the delay of about 1ms due to the limitation of a processor clock, but the requirement of some special industrial control scenes cannot be met. In this embodiment, the FPGA control chip 10 may adopt a XILINX Spartan-6FPGA, the clock frequency of the FPGA is 62.5MHz, the reference clock is nS level, the delay is as low as 1us, and the requirement of low delay in some special industrial control scenarios can be met. Meanwhile, the transmission rate of the FPGA control chip 10 can reach 2.5GT/S, an uplink end can meet the bandwidth requirement, a user can use 250 IO ports, logic units are ten thousand levels, and the requirements of practical application function modules such as an IO module, an interrupt module, a filtering module and a relay holding module on FPGA resources can be met. Besides meeting the most important low-delay requirement, the FPGA has the advantages of being reprogrammable, customizable, easy to maintain, convenient to transplant, upgrade or expand, capable of customizing rich peripheral interfaces and performing hardware function configuration according to different practical application requirements due to the flexibility of the FPGA. The FPGA control chip 10 can control the switching of the acquisition channels, so that the input interface 30 and the output interface 40 can be provided in plurality to realize multi-channel acquisition.
The utility model discloses a set up FPGA control chip 10, PCIE interface 20, input interface 30 and output interface 40 for FPGA control chip 10 can be converted external equipment's IO signal into PCIE signal and export to the host computer, perhaps converts the PCIE signal of host computer into IO signal output to external equipment, has realized the data interaction between external equipment and the host computer, makes the host computer can carry out analysis, processing to the data that external equipment gathered. The utility model discloses a set up FPGA control chip 10, realized the data acquisition and the processing of host computer, greatly reduced data acquisition's time delay, simultaneously, input interface 30 and output interface 40's interface quantity can set up to a plurality ofly, has realized multichannel collection, can satisfy the application demand of different scenes, has improved the practicality.
Referring to fig. 1 and 2, in an embodiment, the input interface 30 includes:
an isolated input interface 31 for accessing an external device;
a non-isolated input interface 32 for accessing external devices.
Further, the output interface 40 includes:
an isolated output interface 41 for accessing an external device;
and a non-isolated output interface 42 for accessing an external device.
The input interface 30 and the output interface 40 are used for accessing external devices, and external data acquisition devices are usually equipped with power supplies and are often far away, so that when being connected with the external data acquisition devices, measures of electrical isolation are needed to ensure physical safety, and the isolation can protect the system from high voltage and large current damage caused by line surge, and can reduce signal distortion. In this embodiment, the input interface 30 and the output interface 40 may be divided into an isolated interface and a non-isolated interface, where the isolated interface is mainly used for accessing external data acquisition devices not belonging to the same power supply group, and the non-isolated interface is mainly used for connecting other devices belonging to the same power supply group in the host. In this embodiment, the number of the isolated input interface 31, the non-isolated input interface 32, the isolated output interface 41, and the non-isolated output interface 42 may be multiple, so as to access and monitor multiple devices simultaneously, thereby implementing multi-channel acquisition. The number of the input interfaces 30 and the output interfaces 40 can be adjusted according to the actual application scenario to meet the application requirements of different scenarios. The utility model discloses an input, output interface 40 and non-isolation input, output interface 40 are kept apart in the setting for the host computer can realize the data interaction through different interfaces and different external equipment, has satisfied the application demand of different scenes, has improved security and practicality.
Referring to fig. 1 and 2, in an embodiment, the IO signal conversion circuit further includes:
and the isolation input circuit 33 is arranged between the isolation input interface 31 and the input end of the FPGA control chip 10 in series, and is used for isolating the IO signal input by the external equipment and outputting the IO signal to the FPGA control chip 10.
Further, the IO signal conversion circuit further includes:
and the isolation output circuit 43 is arranged between the isolation output interface 41 and the output end of the FPGA control chip 10 in series, and is used for isolating the IO signal output by the FPGA control chip 10 and outputting the IO signal to an external device.
In this embodiment, when the isolated input interface 31 and the isolated output interface 41 are connected to external data acquisition devices that do not belong to the same power supply pack, the distance from the external data acquisition devices is often long, so that it is necessary to take measures for electrical isolation to ensure physical safety, and the isolation can protect the system from high voltage and large current damage caused by line surge, and can also reduce signal distortion. In this embodiment, the isolation input interface 31 and the isolation output interface 41 are connected to the FPGA control chip 10 through the isolation input circuit 33 and the isolation output circuit 43, and the isolation input circuit 33 and the isolation output circuit 43 can use an optocoupler to electrically isolate the input/output part of the external device from the control part of the FPGA control chip 10, thereby reducing signal crosstalk between circuits and improving the stability of data acquisition.
Referring to fig. 1 and 2, in an embodiment, the IO signal conversion circuit further includes:
and the non-isolated input signal buffer 34 is arranged between the non-isolated input interface 32 and the input end of the FPGA control chip 10 in series, and is used for amplifying the IO signal input by the external equipment and outputting the IO signal to the FPGA control chip 10.
Further, the IO signal conversion circuit further includes:
and the non-isolated output signal buffer 44 is arranged between the non-isolated output interface 42 and the output end of the FPGA control chip 10 in series, and is used for amplifying the IO signal output by the FPGA control chip 10 and outputting the IO signal to an external device.
In this embodiment, signal buffers are disposed between the non-isolated input interface 32 and the non-isolated output interface 42 and the FPGA control chip 10, and the signal buffers can perform a signal amplification function, so as to prevent mutual interference influence on the input signal and the output signal caused by a great difference in the voltage of the power supply in the circuit, and reduce signal distortion. The signal buffer can also play a role in impedance conversion, can well meet the requirements of preceding-stage voltage amplification and low-impedance output of a load, can solve the problem that a signal source with high input impedance cannot drive the load with low input impedance, and improves the stability of data acquisition.
Referring to fig. 1 and 2, in an embodiment, the IO signal conversion circuit further includes:
the input end of the first power conversion circuit 50 is connected to the first power output end of the PCIE interface 20, the output end of the first power conversion circuit 50 is connected to the power end of the FPGA control chip 10, and the first power conversion circuit 50 is configured to convert the first power output by the upper computer into a first power supply and supply power to the FPGA control chip 10.
Further, the IO signal conversion circuit further includes:
the input end of the second power conversion circuit 60 is connected to the second power output end of the PCIE interface 20, the output end of the second power conversion circuit 60 is connected to the non-isolated input signal buffer 34 and the non-isolated output signal buffer 44, respectively, and the second power conversion circuit 60 is configured to convert the second power output by the upper computer into a second power supply and supply power to the non-isolated input signal buffer 34 and the non-isolated output signal buffer 44.
In this embodiment, the PCIE interface 20 is further provided with a first power output end and a second power output end, and is configured to output a first power and a second power when accessing the upper computer, where the first power is 3.3V, and the first power conversion circuit 50 converts the 3.3V power into 1.2V and outputs the 1.2V power to the FPGA control chip 10 for power supply. The second power supply is 12V, and the second power conversion circuit 60 converts the 12V power supply into 5V power supply and outputs the 5V power supply to the non-isolated input signal buffer 34 and the non-isolated output signal buffer 44 for power supply.
The utility model discloses still provide an IO data acquisition card, this IO data acquisition card include circuit board and foretell IO signal conversion circuit, and this IO signal conversion circuit's concrete structure refers to above-mentioned embodiment, because this motor element has adopted the whole technical scheme of above-mentioned all embodiments, consequently has all beneficial effects that the technical scheme of above-mentioned embodiment brought at least, no longer gives unnecessary details here one by one.
The IO signal conversion circuit is integrated on the circuit board.
The above only is the preferred embodiment of the present invention, not so limiting the patent scope of the present invention, all under the inventive concept of the present invention, the equivalent structure transformation made by the contents of the specification and the drawings is utilized, or the direct/indirect application in other related technical fields is included in the patent protection scope of the present invention.
Claims (10)
1. An IO signal conversion circuit, comprising:
the input interface is used for accessing external equipment;
the input end of the FPGA control chip is connected with the input interface;
the PCIE interface is connected with the FPGA control chip and used for accessing an upper computer;
the FPGA control chip is used for converting the IO signal input by the input interface into a PCIE signal and outputting the PCIE signal to an upper computer through the PCIE interface;
the output interface is connected with the output end of the FPGA control chip and used for accessing external equipment;
the FPGA control chip is also used for converting PCIE signals input by the PCIE interface into IO signals and outputting the IO signals to external equipment through the output interface.
2. The IO signal conversion circuit of claim 1, wherein the input interface comprises:
the isolation input interface is used for accessing external equipment;
and the non-isolated input interface is used for accessing external equipment.
3. The IO signal conversion circuit according to claim 2, further comprising:
and the isolation input circuit is arranged between the isolation input interface and the input end of the FPGA control chip in series and used for isolating the IO signal input by the external equipment and outputting the IO signal to the FPGA control chip.
4. The IO signal conversion circuit according to claim 2, further comprising:
and the non-isolated input signal buffer is serially arranged between the non-isolated input interface and the input end of the FPGA control chip and is used for amplifying an IO signal input by external equipment and outputting the IO signal to the FPGA control chip.
5. The IO signal conversion circuit of claim 1, wherein the output interface comprises:
the isolation output interface is used for accessing external equipment;
and the non-isolated output interface is used for accessing external equipment.
6. The IO signal conversion circuit according to claim 5, further comprising:
and the isolation output circuit is serially arranged between the isolation output interface and the output end of the FPGA control chip and is used for isolating the IO signal output by the FPGA control chip and outputting the IO signal to external equipment.
7. The IO signal conversion circuit according to claim 5, further comprising:
and the non-isolated output signal buffer is serially arranged between the non-isolated output interface and the output end of the FPGA control chip and is used for amplifying the IO signal output by the FPGA control chip and outputting the IO signal to external equipment.
8. The IO signal conversion circuit according to claim 1, further comprising:
the input end of the first power supply conversion circuit is connected with the first power supply output end of the PCIE interface, the output end of the first power supply conversion circuit is connected with the power supply end of the FPGA control chip, and the first power supply conversion circuit is used for converting a first power supply output by an upper computer into a first power supply and supplying power for the FPGA control chip.
9. The IO signal conversion circuit according to claim 4, further comprising:
and the input end of the second power conversion circuit is connected with the second power output end of the PCIE interface, the output end of the second power conversion circuit is respectively connected with the non-isolated input signal buffer and the non-isolated output signal buffer, and the second power conversion circuit is used for converting a second power output by an upper computer into a second power supply and supplying power to the non-isolated input signal buffer and the non-isolated output signal buffer.
10. An IO data acquisition card, comprising a circuit board and an IO signal conversion circuit according to any one of claims 1 to 9;
the IO signal conversion circuit is integrated on the circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122198489.6U CN218450105U (en) | 2021-09-10 | 2021-09-10 | IO signal conversion circuit and IO data acquisition card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122198489.6U CN218450105U (en) | 2021-09-10 | 2021-09-10 | IO signal conversion circuit and IO data acquisition card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218450105U true CN218450105U (en) | 2023-02-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122198489.6U Active CN218450105U (en) | 2021-09-10 | 2021-09-10 | IO signal conversion circuit and IO data acquisition card |
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| CN (1) | CN218450105U (en) |
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