CN218449507U

CN218449507U - Buck-boost circuit with double channels for independently and automatically identifying battery load

Info

Publication number: CN218449507U
Application number: CN202122600834.4U
Authority: CN
Inventors: 班福奎
Original assignee: Shanghai Shiningic Electronic Technology Co ltd
Current assignee: Shanghai Shiningic Electronic Technology Co ltd
Priority date: 2021-10-27
Filing date: 2021-10-27
Publication date: 2023-02-03
Anticipated expiration: 2031-10-27

Abstract

A dual-channel voltage boosting and reducing circuit capable of independently and automatically identifying battery loads comprises a low voltage boosting and reducing control chip, an energy storage inductor, a rechargeable battery, a first battery load and a second battery load; the buck-boost control chip comprises a buck-boost control module, a load detection module, a boost bypass capacitor, a first detection resistor, a second detection resistor, an output port VOUT1, an output port VOUT2, a first detection port VEND1, a second detection port VEND2 and a ground end GND; the rechargeable battery is connected between the port BAT and the ground terminal GND, the first battery load is connected between the output port VOUT1 and the ground terminal GND, and the second battery load is connected between the output port VOUT2 and the ground terminal GND; the first detection resistor is connected between the first detection port VEND1 and the ground terminal GND, and the second detection resistor is connected between the second detection port VEND2 and the ground terminal GND. Therefore, the utility model discloses an increase the voltage that load detection module removed detection output and detection port, realize the independent automatic identification and the syllogic charge management of binary channels battery load.

Description

Buck-boost circuit with double channels for independently and automatically identifying battery load

Technical Field

The utility model belongs to the technical field of power supply circuit design, a lift voltage circuit of independent automatic identification battery load of binary channels is related to.

Background

With the continuous development of integrated circuit technology, the buck-boost direct-current conversion power management products are widely developed and applied, high-efficiency direct-current to direct-current power conversion is realized, and the buck-boost direct-current conversion power management products can be applied to the use environments and occasions of various electronic products.

Referring to fig. 1, fig. 1 is a schematic connection diagram of a buck-boost dc conversion circuit in the prior art. As shown in fig. 1, the control chip 212 has 5 ports VIN, LX, BAT, VOUT1 and GND. The positive electrode of the input capacitor 102 and the USB port of the USB power port are connected to the port VIN, and the negative electrode of the input capacitor 102 is grounded; the energy storage inductor 104 is connected between the port LX and the port BAT, and the battery bypass capacitor 105 is connected between the port BAT and the ground terminal GND; the positive electrode of the rechargeable battery 106 is connected between the port BAT and the ground terminal GND; the port output capacitor 107 and the battery load 108 are connected in parallel between the port VOUT1 and the ground terminal GND.

It is clear to those skilled in the art that in the above circuit, the dc conversion mode, for example, the buck or boost dc conversion mode, can be determined by the voltage value of the port VIN. Specifically, when the port MODE module 401 determines the voltage value of the port VIN to select the power conversion MODE, the following situations may be adopted:

(1) when VIN is more than or equal to 4.7V, the port VIN, the switch PMOS tube 404, the follow current NMOS tube 405 and the inductor 104 form a synchronous voltage reduction structure, the battery 106 is charged in a switch mode, and meanwhile, power supply energy is provided for a battery load of the port VOUT;

(2) when VIN is more than or equal to 4.5 and less than 4.7V, synchronous voltage reduction does not work, and the VIN at the port only provides power supply energy for the battery load;

(3) when VIN is less than 4.5V, the switch NMOS tube 405, the follow current PMOS tube 404 and the energy storage inductor 104 form a synchronous boosting framework, and the battery 106 discharges to provide power supply energy for the battery load 108;

(4) when the VIN port is floated, the battery load 108 connected to the port VOUT charges the battery load 108 by the synchronous boost formed by the control chip 212 and the energy storage inductor 104.

It can be seen from the operation principle of the above circuit that when the VIN port is floated, if the battery load 108 is charged, it is impossible to monitor whether the battery load 108 is fully charged, and even if the battery load 108 is fully charged, the synchronous boost is still in the working state all the time.

SUMMERY OF THE UTILITY MODEL

For the above-mentioned technical problem who solves, the utility model provides a binary channels independent automatic identification battery load's lift piezoelectric circuit, its technical scheme as follows:

a dual-channel voltage boosting and reducing circuit capable of independently and automatically identifying battery loads comprises a voltage boosting and reducing control chip, an energy storage inductor, a rechargeable battery, a first battery load and a second battery load; the buck-boost control chip comprises a buck-boost control module, a load detection module, a boost bypass capacitor, a first detection resistor, a second detection resistor, a power port VIN, an inductance port LX, a charging port BAT, a buck-boost port PMID, an output port VOUT1, an output port VOUT2, a first detection port VEND1, a second detection port VEND2 and a ground terminal GND; the port VIN receives the voltage of the power supply; the energy storage inductor is connected between the port LX and the port BAT, the positive electrode of the rechargeable battery is connected to the port BAT, the negative electrode of the rechargeable battery is connected to the ground end GND, the first battery load is connected between the output port VOUT1 and the ground end GND, and the second battery load is connected between the output port VOUT2 and the ground end GND; the boost bypass capacitor is connected between the boost port PMID and a ground terminal GND; the first detection resistor is connected between the first detection port VEND1 and a ground terminal GND, and the second detection resistor is connected between the second detection port VEND2 and the ground terminal GND; the buck-boost control module is used for performing management selection on a power supply path according to the input voltage of the power supply port VIN; the load detection module respectively detects the output port VOUT1, the output port VOUT2, a first detection port VEND1 and a second detection port VEND2; when the voltage of the output port VOUT1 is greater than or equal to V11 and less than V12, and when the voltage of the first detection port VEND1 is less than a predetermined threshold V1, the charging of the first battery load is ended; or when the voltage of the output port VOUT2 is greater than or equal to V21 and less than or equal to V22, and when the voltage of the second detection port VEND1 is less than a predetermined threshold V1, the charging of the second battery load is ended.

Further, the load detection module comprises a load controller, a first charging channel PMOS tube, a first charging sampling PMOS tube, a second charging channel PMOS tube and a second charging sampling PMOS tube; the load controller respectively outputs different signals VGT1 and VGT2 according to feedback signals of an output port VOUT1, a first detection port VEND1, an output port VOUT2 and a second detection port VEND2, and controls a first charging channel PMOS tube, a first charging sampling PMOS tube 503, a second charging channel PMOS tube and a second charging sampling PMOS tube so as to realize three-stage charging of battery loads connected to the output port VOUT1 and the output port VOUT 2; charging in a first stage: when the load detector detects that the output port VOUT1 is less than V13, the first charging channel PMOS tube is in a trickle charging mode, and the voltage value of the first detection port VEND1 is V2; when the load detector detects that the output port VOUT2 is less than V23, the first charging channel PMOS tube is in a trickle charging mode, and the voltage value of the second detection port VEND1 is V2; wherein V13 is less than V12, V23 is less than V22, and V2 is greater than V1; and (3) second-stage charging: when the load detector detects that the output port V13 is not less than VOUT1 and less than V12, the first charging channel PMOS tube is in a constant current charging mode, and the voltage value of the first detection port VEND1 is V3; the charging current is 100% of the set value; similarly, when the load detector detects that VOUT2 is greater than or equal to V23 and less than V22 at the output port, the second charging channel PMOS transistor is in the constant-current charging mode, and the voltage value of the second detection port VEND1 is V3; the charging current is 100% of the set value; wherein V3 is greater than V2; and third stage charging: when the load detector detects that the output port V12 is not less than VOUT1 and less than V11, the first charging channel PMOS tube is in a constant voltage charging mode, the charging current linearly decreases along with the voltage of the output port VOUT1, and the charging is finished when the voltage value of the first detection port VEND1 is a preset threshold value V1; similarly, when the load detector detects that VOUT1 is greater than or equal to the output port V12 and less than V11, the second charging channel PMOS transistor is in the constant voltage charging mode, the charging current linearly decreases with the voltage of the output port VOUT2, and charging is terminated until the voltage of the second detection port is the predetermined threshold V1, where V11 is greater than V12, V21 is greater than V22, and V3 is greater than V2.

Further, V11 and V21 are 4.2 volts; the V12 and V22 are 4.05 volts; the V13 and V23 are 2.9 volts; v1 is 0.1, V2 is 1 volt, and V3 is 0.2 volt.

Furthermore, the dual-channel voltage boosting and reducing circuit capable of independently and automatically identifying the battery load further comprises a high-voltage isolation module; the buck-boost control module comprises a mode selector, and the mode selector is used for performing management selection on a power supply path according to the input voltage of the power supply port VIN; when VIN is more than or equal to V2, a synchronous voltage reduction loop is formed in a loop containing the energy storage inductor to carry out switch-type charging on the rechargeable battery and provide power supply energy for the load; when V41 is more than or equal to VIN and less than V42, the synchronous voltage reduction loop does not work, and the VIN of the power supply port only provides power supply energy for the load; when VIN is less than V41, a synchronous boosting loop is formed in a loop containing the energy storage inductor, the rechargeable battery is discharged, and power supply energy is provided for the load; the voltage increasing and reducing control module and the load have the working voltages of V43 and V43 is greater than V42, wherein V41 is smaller than V42; when VIN is more than or equal to V44 or VIN is less than V41, the input high-voltage isolation module is used for isolating the power supply port VIN from the buck-boost control module and the output port VOUT; wherein V43 < V44.

Furthermore, the high-voltage isolation module comprises an NMOS isolation tube, a power supply regulator and a charge pump; wherein the drain of the NMOS isolation tube is connected to the port VIN, the source thereof is connected to the port VOUT, and the gate thereof is connected to the output of the charge pump; the input of the power supply regulator is connected to a port VIN, and the output of the power supply regulator is used as power supply to the charge pump; the input of the charge pump is connected to the output of the power supply regulator, and the output of the charge pump is connected to the grid electrode of the NMOS isolation tube.

Further, the high-voltage isolation module comprises a power supply adjuster, a grid clamping Zener diode, a PMOS isolation tube, a first substrate switching diode and a second substrate switching diode; wherein the source of the PMOS isolation tube is connected to a port VIN, the drain thereof is connected to a port VOUT, and the gate thereof is connected to an output node ENB of the power supply regulator; the input of the power regulator is connected to port VIN, and the output thereof is connected to output node ENB; the anode of the gate-clamp zener diode is connected to the output node ENB, and the cathode thereof is connected to the source of the PMOS isolator; the anode of the first substrate switching diode is connected to a port VIN, and the cathode of the first substrate switching diode is connected to the substrate of the PMOS isolation tube; the anode of the second substrate switching diode is connected to VOUT, and the cathode of the second substrate switching diode is connected to the substrate of the PMOS isolation tube.

Furthermore, the buck-boost control module comprises a PMOS tube, an NMOS tube, a mode selector, a substrate selector and a buck-boost controller. Wherein: the source electrode of the PMOS tube is connected to VOUT, the drain electrode of the PMOS tube is connected to LX, and the grid electrode of the PMOS tube is connected to the VPG output end of the buck-boost controller; the source electrode of the NMOS tube is connected to the ground, the drain electrode of the NMOS tube is connected to the LX, and the gate electrode of the NMOS tube is connected to the VNG output end of the buck-boost controller; the input connection end of the mode selector is connected to VIN, and the output end of the mode selector is connected to the input end VMOD of the buck-boost controller; two input ends of the substrate selector are respectively VOUT and BAT, and an output end is VSUB and is connected to the input end of the buck-boost controller; the 4 inputs of the buck-boost controller are VOUT, VMOD, VSUB and BAT, respectively, and the two outputs are VPG and VNG, respectively.

Further, V41 is 4.5 volts, V42 is 4.7 volts, V43 is 5 volts, and V44 is 6.5 volts.

Further, the chip with the functional timing circuit further comprises an input capacitor and a battery bypass capacitor, wherein the input capacitor is connected between the port VIN and a ground terminal GND; the battery bypass capacitor is connected between the anode of the rechargeable battery and a ground end GND.

Furthermore, the dual-channel voltage boosting and reducing circuit capable of independently and automatically identifying the battery load further comprises a first output capacitor and a second output capacitor, wherein the first output capacitor is connected between the first battery load and a ground terminal GND; the second output capacitor is connected between the second battery load and a ground terminal GND.

According to the above technical scheme, the utility model discloses a two-channel independent automatic identification battery load's buck-boost circuit based on above-mentioned circuit realizes two-channel battery load's independent automatic identification and syllogic charge management.

Drawings

FIG. 1 is a schematic diagram of a buck-boost DC conversion circuit in the prior art

Fig. 2 is a schematic diagram of the buck-boost circuit for two-channel independent automatic identification of battery load in the embodiment of the present invention

FIG. 3 is a schematic diagram of the dual-channel load detection waveform in the embodiment of the present invention

FIG. 4 is a schematic diagram of the embodiment of the present invention, illustrating an input high voltage isolation module

FIG. 5 is a schematic diagram of power path management according to an embodiment of the present invention

Description of the element reference

101. Control chip

102. Input capacitance

103. Boost bypass capacitor

104. Energy storage inductor

105. Battery bypass capacitor

106. Rechargeable battery

107. First output capacitor

108. A first battery load

109. A first detection resistor

110. Second output capacitor

111. Second battery load

112. Second detection resistor

201. High-voltage isolation module

202. Boost-buck control module

203. Load detection module

501. Load controller

502. PMOS tube with first charging channel

503. First charging sampling PMOS tube

504. PMOS tube of second charging channel

505. Second charging sampling PMOS tube

Detailed Description

The following description will be made in detail with reference to the accompanying fig. 2-3.

It should be noted that, the utility model discloses an among the lift voltage circuit of the independent automatic identification battery load of binary channels, it increases load detection module, first detection port VEND1, second detection port VEND2, first detection resistance and second detection resistance, through the voltage that detects output and detection port, realizes the independent automatic identification battery load of binary channels and carries out the control of charged state.

Referring to fig. 2, fig. 2 is a schematic diagram of a voltage step-up/step-down circuit for a dual-channel independent automatic battery load identification according to an embodiment of the present invention. As shown in fig. 2, the buck-boost circuit for two-channel independent automatic identification of battery load includes: the boost-buck circuit comprises a boost-buck control chip 101, an input capacitor 102, an energy storage inductor 104, a battery bypass capacitor 105, a rechargeable battery 106, a boost bypass capacitor 103, a first output capacitor 107, a first battery load 108, a first detection resistor 109, a second output capacitor 110, a second battery load 111 and a second detection resistor 112.

The buck-boost control chip 101 includes an input high-voltage isolation module 201, a buck-boost control module 202, a load detection module 203, a power port VIN, an inductor port LX, a charging port BAT, a boost output port PMID, a first output port VOUT1, a first detection port VEND1, a second output port VOUT2, a second detection port VEND2, and a ground terminal GND.

In embodiments of the present invention, the port VIN may be connected to a charger (e.g., USB port). The port LX is connected to one end of the energy storage inductor 104, and the other end of the energy storage inductor 104 is connected to the port BAT of the control chip 101, the positive electrode of the battery bypass capacitor 105, and the positive electrode of the rechargeable battery 106; the port PMID is connected to the positive pole of the boost bypass capacitor 103; the port VOUT1 is connected to the positive terminal of the first output capacitor 107 and the positive terminal of the first battery load 108; the port VEND1 is connected to one end of the sampling resistor 109, and the other end of the sampling resistor 109 is connected to ground; the port VOUT2 is connected to the positive electrode of the second output capacitor 110 and the positive electrode of the second battery load 111; the port VEND2 is connected to one end of the sampling resistor 112, and the other end of the sampling resistor 112 is connected to ground; the GND end of the port is connected to ground; the cathode of the input capacitor 102, the cathode of the boost bypass capacitor 103, the cathode of the battery bypass capacitor 105, the cathode of the rechargeable battery 106, the cathode of the first output capacitor 107, the cathode of the first battery load, the cathode of the second output capacitor 110, and the cathode of the second battery load 108 are all connected to the ground GND.

The buck-boost control module is used for performing management selection on a power supply path according to the input voltage of the power supply port VIN; the load detection module respectively detects the output port VOUT1, the output port VOUT2, a first detection port VEND1 and a second detection port VEND2; wherein: VOUT1 is a voltage value of a port VOUT1 of the chip 101, VEND1 is a voltage value of a port VEND1 of the chip 101, VGT1 is a signal output by the load controller 501 after processing according to VOUT1 and VEND1 signals and controls the conduction capabilities of the first charge channel PMOS transistor 502 and the first charge sampling PMOS transistor 503, the highest voltage of VGT1 is a voltage value VPMID of the port PMID, and IOUT1 is a current flowing through the first charge channel PMOS transistor.

When the voltage of the output port VOUT1 is greater than or equal to V11 and less than V12, and when the voltage of the first detection port VEND1 is less than a predetermined threshold V1, the charging of the first battery load is ended; or when the voltage of the output port VOUT2 is greater than or equal to V21 and less than or equal to V22, and when the voltage of the second detection port VEND1 is less than a predetermined threshold V1, the charging of the second battery load is ended.

Specifically, in a preferred embodiment of the present invention, the load detection module includes a load controller, a first charging channel PMOS transistor, a first charging sampling PMOS transistor, a second charging channel PMOS transistor, and a second charging sampling PMOS transistor; the load controller respectively outputs different signals VGT1 and VGT2 according to feedback signals of the output port VOUT1, the first detection port VEND1, the output port VOUT2 and the second detection port VEND2, and controls the first charging channel PMOS tube, the first charging sampling PMOS tube 503, the second charging channel PMOS tube and the second charging sampling PMOS tube so as to realize three-stage charging of battery loads connected to the output port VOUT1 and the output port VOUT 2.

Charging in a first stage: when the load detector detects that the output port VOUT1 is less than V13, the first charging channel PMOS tube is in a trickle charging mode, and the voltage value of the first detection port VEND1 is V2; when the load detector detects that the output port VOUT2 is less than V23, the first charging channel PMOS tube is in a trickle charging mode, and the voltage value of the second detection port VEND1 is V2; wherein V13 is less than V12, V23 is less than V22, and V2 is greater than V1.

And (3) second-stage charging: when the load detector detects that the output port V13 is not less than VOUT1 and less than V12, the first charging channel PMOS tube is in a constant current charging mode, and the voltage value of the first detection port VEND1 is V3; the charging current is 100% of the set value; similarly, when the load detector detects that the output port V23 is not less than VOUT2 and less than V22, the second charging channel PMOS tube is in a constant-current charging mode, and the voltage value of the second detection port VEND1 is V3; the charging current is 100% of the set value; wherein V3 is greater than V2.

And third stage charging: when the load detector detects that the output port V12 is not less than VOUT1 and less than V11, the first charging channel PMOS tube is in a constant voltage charging mode, the charging current linearly decreases along with the voltage of the output port VOUT1, and the charging is finished when the voltage value of the first detection port VEND1 is a preset threshold value V1; similarly, when the load detector detects that VOUT1 is greater than or equal to the output port V12 and less than V11, the second charging channel PMOS transistor is in the constant voltage charging mode, the charging current linearly decreases with the voltage of the output port VOUT2, and charging is terminated until the voltage of the second detection port is the predetermined threshold V1, where V11 is greater than V12, V21 is greater than V22, and V3 is greater than V2.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating a dual-channel load detection waveform according to an embodiment of the present invention. In the embodiment of the present invention, it can be assumed that V11 and V21 are 4.2 volts; the V12 and V22 are 4.05 volts; the V13 and V23 are 2.9 volts; v1 is 0.1, V2 is 1 volt, and V3 is 0.2 volt. The first charging path will be described as an example.

As shown in fig. 3, when the load detector 501 detects VOUT1 < 2.9V, the first charging channel PMOS transistor 502 is in the trickle charging mode, the charging current IOUT1 is 20% of the set value, and the voltage value of VEND1 is 0.2V; when the load detector 501 detects that VOUT1 is greater than or equal to 2.9V and less than 4.15V, the first charging channel PMOS transistor 502 is in a constant-current charging mode, the charging current IOUT1 is 100% of a set value, and the voltage value of VEND1 is 1V; when the load detector 501 detects that VOUT1 is greater than or equal to 4.15V and less than 4.2V, the first charging channel PMOS transistor 502 is in a constant-voltage charging mode, and the charging current IOUT1 linearly decreases along with the voltage of VOUT1 until the voltage of VEND1 is 0.1V, so that charging is finished; when the voltage of VOUT1 drops from 4.2V to 4.05V, the constant current charging mode is triggered.

It should be noted that the second charging channel PMOS transistor 504 and the first charging channel PMOS transistor are independent from each other, and the detection is not affected by each other, but the working principle of the two charging channels is the same.

In some preferred embodiments of the present invention, assuming that the buck-boost control module 202 and the load 108 are at 5V, when VIN is at a high voltage (e.g., greater than 6.5V) or VIN is at a low voltage (e.g., less than 4.5V), the input high voltage isolation module 201 isolates the chip port VIN from the buck-boost control module 202 and the output port VOUT, i.e., the load 108 only receives the discharge of the rechargeable battery 106, so that the buck-boost control module 202 and the load 108 connected to the output port VOUT are not damaged, and the rechargeable battery 106 can also avoid the situation of recharging the charger (e.g., USB port).

Referring to fig. 2, in the embodiment, the high voltage isolation module 201 may include an NMOS isolation transistor 303, a power regulator (REG/UVLO/OVP) 301, and a charge PUMP (PUMP) 302. The drain of the NMOS isolation tube 303 is connected to the port VIN, the source thereof is connected to the output terminal VOUT, and the gate thereof is connected to the output of the charge pump 302; the input of the power regulator 301 is connected to VIN, the output of which is supplied as power to the charge pump 302; the input of the charge pump 302 is connected to the output of the power regulator 301, and its output is connected to the gate of the NMOS isolation tube 303.

In another preferred embodiment of the present invention, as shown in fig. 4, the high voltage isolation module 201 may also include a power regulator 304, a gate clamp zener diode 305, a PMOS isolation tube 306, a first substrate switching diode 307, and a second substrate switching diode 308. The source of the PMOS isolation transistor 306 is connected to the port VIN, the drain thereof is connected to the port VOUT, and the gate thereof is connected to the output ENB of the power regulator; the input of the power supply regulator is connected to the port VIN, and the output is ENB; the gate clamp zener diode 305 has its anode connected to ENB and its cathode connected to the source of the PMOS isolation transistor; the anode of the first substrate switching diode 307 is connected to the port VIN, and the cathode thereof is connected to the bulk of the PMOS isolation tube 306; the anode of the second substrate-switching diode 308 is connected to the port VOUT and its cathode is connected to the substrate of the PMOS isolation tube 306.

It should be noted that the buck-boost control module 202 may be any one of those in the art. For example, in an embodiment of the present invention, as shown in fig. 2, the BUCK-BOOST Control module 202 may include a PMOS transistor 404, an NMOS transistor 405, a MODE selector (MODE) 401, a substrate Selector (SUB) 402, and a BUCK-BOOST controller (BUCK-BOOST Control) 403.

Wherein, the source of PMOS transistor 404 is connected to VOUT, its drain is connected to LX, and its gate is connected to VPG output of buck-boost controller 403; NMOS transistor 405 has its source connected to ground, its drain connected to LX, and its gate connected to the VNG output of buck-boost controller 403; an input connection of the mode selector 401 is connected to the port VIN, and an output terminal thereof is connected to an input terminal VMOD of the buck-boost controller 403; two input terminals of the substrate selector 402 are respectively a port VOUT and a port BAT, and an output terminal is VSUB and is connected to an input terminal of the buck-boost controller 403; the 4 inputs of buck-boost controller 403 are port VOUT, port VMOD, port VSUB, and port BAT, respectively, and the two outputs are port VPG and port VNG, respectively.

In this embodiment, since the substrate selector 402 does not play a role in association with the technical solution of the present invention, it is not described herein again.

The principle of the present invention will be described with reference to fig. 5 in conjunction with fig. 2. In this embodiment, as shown in fig. 2, the buck-boost control module 202 includes a mode selector 401, and the mode selector 401 is configured to perform management selection of a power path according to the input voltage of the power port VIN. When VIN is more than or equal to V2, a synchronous voltage reduction loop is formed in a loop containing the energy storage inductor, the rechargeable battery is charged in a switch mode, and meanwhile, power supply energy is provided for the load; when V41 is more than or equal to VIN and less than V42, the synchronous voltage reduction loop does not work, and the VIN of the power supply port only provides power supply energy for the load; when VIN is less than V41, a synchronous boosting loop is formed in a loop containing the energy storage inductor, the rechargeable battery is discharged, and power supply energy is provided for the load; and V41 is smaller than V42, the working voltage of the buck-boost control module and the load is V3, and V3 is larger than V42. When VIN is more than or equal to V44 or VIN is less than V41, the input high-voltage isolation module is used for isolating the power supply port VIN from the buck-boost control module and the output port VOUT; wherein V43 < V44.

Specifically, referring to fig. 3, fig. 3 is a schematic diagram illustrating power path management according to an embodiment of the present invention. In this embodiment, V41, V42, V43, and V44 are all dc voltage values, and V41 < V42 < V43 < V44. As shown in FIG. 3, V41 is 4.5 volts, V42 is 4.7 volts, V43 is 5 volts, and V44 is 6.5 volts. That is, the operating voltage of the buck-boost control module and the load is V3=5 volts.

When the mode selector 401 detects VIN < 4.5V or VIN > 6.5V, the VREG output level of the power regulator 301 is 0, the charge pump 302 does not operate, the output level is 0, i.e. the gate of the NMOS isolation tube 303 is low, the NMOS isolation tube 303 is turned off, the port VIN and the port VOUT are open, and when the mode selector 401 detects VIN < 4.5V or VIN > 6.5V, the output signal VMOD makes the buck-boost controller 403 in the boost operating mode, and the rechargeable battery 106 is discharged to the load 108 through the energy storage inductor 104 and the buck-boost control module 202.

When the mode selector 401 detects that VIN is greater than or equal to 4.5V and less than or equal to 6.5V, VREG output of the power regulator 301 is VIN (4.5V and less than or equal to 5V) or VREG output is 5V (VIN is greater than 5V and less than or equal to 6.5V), the output level of the charge pump 302 is 7V when working, that is, the gate of the NMOS isolation tube 303 is at high level 7V, so the NMOS isolation tube 303 is turned on, and the port VIN and the port VOUT are closed.

When the mode selector 401 detects that VIN is greater than or equal to 4.5V and less than 4.7V, the output signal VMOD makes the buck-boost controller 403 in the standby mode, the buck-boost control module 202 does not charge or discharge the rechargeable battery 106, and VIN directly provides power for VOUT through the NMOS isolation tube 303.

When the mode selector 401 detects that VIN is greater than or equal to 4.7V and less than 6.5V, the output signal VMOD makes the buck-boost controller 403 in the charging mode, VIN charges the rechargeable battery 106 through the NMOS isolation tube 303 and the buck-boost control module 202, and VIN directly provides power for VOUT through the NMOS isolation tube 303.

To sum up, the utility model discloses an among the independent automatic identification battery load's of binary channels lift voltage circuit, it can specifically want to use the earphone in, it increases load detection module, first detection port VEND1, second detection port VEND2, first detection resistance and second detection resistance, through the output that detects left and right earphone and the voltage of detection port, realizes that independent automation detects the charged state of controlling earphone binary channels battery load respectively, whether controls earphone binary channels battery load and charges and accomplish about conveniently monitoring.

What has just been said is the preferred embodiment of the present invention, the embodiment is not used for limiting the patent protection scope of the present invention, therefore all the equivalent structural changes made by the contents of the specification and the drawings of the present invention are utilized, and the same principle should be included in the protection scope of the present invention.

Claims

1. A dual-channel boost-buck circuit capable of independently and automatically identifying battery loads is characterized by comprising a boost-buck control chip, an energy storage inductor, a rechargeable battery, a first battery load and a second battery load; the buck-boost control chip comprises a buck-boost control module, a load detection module, a boost bypass capacitor, a first detection resistor, a second detection resistor, a power port VIN, an inductance port LX, a charging port BAT, a buck-boost port PMID, an output port VOUT1, an output port VOUT2, a first detection port VEND1, a second detection port VEND2 and a ground terminal GND;

the port VIN receives a voltage of a power supply; the energy storage inductor is connected between the port LX and the port BAT, the positive electrode of the rechargeable battery is connected to the port BAT, the negative electrode of the rechargeable battery is connected to the ground terminal GND, the first battery load is connected between the output port VOUT1 and the ground terminal GND, and the second battery load is connected between the output port VOUT2 and the ground terminal GND; the boost bypass capacitor is connected between the boost port PMID and a ground terminal GND; the first detection resistor is connected between the first detection port VEND1 and a ground terminal GND, and the second detection resistor is connected between the second detection port VEND2 and the ground terminal GND;

the buck-boost control module is used for performing management selection on a power supply path according to the input voltage of the power supply port VIN; the load detection module is used for respectively detecting the output port VOUT1, the output port VOUT2, a first detection port VEND1 and a second detection port VEND2;

2. The dual-channel boost-buck circuit for independently and automatically identifying a battery load according to claim 1, wherein the load detection module comprises a load controller, a first charge channel PMOS transistor, a first charge sampling PMOS transistor, a second charge channel PMOS transistor, and a second charge sampling PMOS transistor; the load controller respectively outputs different signals VGT1 and VGT2 according to feedback signals of an output port VOUT1, a first detection port VEND1, an output port VOUT2 and a second detection port VEND2, and controls a first charging channel PMOS tube, a first charging sampling PMOS tube 503, a second charging channel PMOS tube and a second charging sampling PMOS tube so as to realize three-stage charging of battery loads connected to the output port VOUT1 and the output port VOUT 2;

charging in a first stage: when the load detector detects that the output port VOUT1 is less than V13, the first charging channel PMOS tube is in a trickle charging mode, and the voltage value of the first detection port VEND1 is V2; when the load detector detects that the output port VOUT2 is less than V23, the first charging channel PMOS tube is in a trickle charging mode, and the voltage value of the second detection port VEND1 is V2; wherein V13 is less than V12, V23 is less than V22, and V2 is greater than V1;

and (3) second-stage charging: when the load detector detects that the output port V13 is not less than VOUT1 and less than V12, the first charging channel PMOS tube is in a constant current charging mode, and the voltage value of the first detection port VEND1 is V3; the charging current is 100% of the set value; similarly, when the load detector detects that the output port V23 is not less than VOUT2 and less than V22, the second charging channel PMOS tube is in a constant-current charging mode, and the voltage value of the second detection port VEND1 is V3; the charging current is 100% of the set value; wherein V3 is greater than V2;

and (3) third-stage charging: when the load detector detects that the output port V12 is not less than VOUT1 and less than V11, the first charging channel PMOS tube is in a constant-voltage charging mode, the charging current linearly decreases along with the voltage of the output port VOUT1, and the charging is finished when the voltage value of the first detection port VEND1 is a preset threshold value V1; similarly, when the load detector detects that VOUT1 is greater than or equal to the output port V12 and less than V11, the second charging channel PMOS transistor is in the constant voltage charging mode, the charging current linearly decreases with the voltage of the output port VOUT2, and charging is terminated until the voltage of the second detection port is the predetermined threshold V1, where V11 is greater than V12, V21 is greater than V22, and V3 is greater than V2.

3. The dual channel independent auto-id battery load buck-boost circuit of claim 2, wherein said V11 and V21 are 4.2 volts; the V12 and V22 are 4.05 volts; the V13 and V23 are 2.9 volts; v1 is 0.1, V2 is 1 volt, and V3 is 0.2 volt.

4. The dual channel self-contained battery load buck-boost circuit according to any of claims 1-3, further comprising a high voltage isolation module; the buck-boost control module comprises a mode selector, and the mode selector is used for performing management selection on a power supply path according to the input voltage of the power supply port VIN; when VIN is more than or equal to V2, a synchronous voltage reduction loop is formed in a loop containing the energy storage inductor to carry out switch-type charging on the rechargeable battery and provide power supply energy for the load; when V41 is more than or equal to VIN and less than V42, the synchronous voltage reduction loop does not work, and the VIN of the power supply port only provides power supply energy for the load; when VIN is less than V41, a synchronous boosting loop is formed in a loop containing the energy storage inductor, the rechargeable battery is discharged, and power supply energy is provided for the load; wherein, V41 is less than V42, the working voltage of the buck-boost control module and the load is V43, and V43 is greater than V42;

when VIN is more than or equal to V44 or VIN is less than V41, the high-voltage isolation module is used for isolating the power supply port VIN from the buck-boost control module and the output port VOUT; wherein V43 < V44.

5. The dual channel independent auto-id battery load buck-boost circuit of claim 4, wherein said high voltage isolation module includes an NMOS isolation transistor, a power regulator and a charge pump; wherein the drain of the NMOS isolation tube is connected to the port VIN, the source thereof is connected to the port VOUT, and the gate thereof is connected to the output of the charge pump; the input of the power supply regulator is connected to a port VIN, and the output of the power supply regulator is used as power supply to the charge pump; the input of the charge pump is connected to the output of the power supply regulator, and the output of the charge pump is connected to the grid electrode of the NMOS isolation tube.

6. The dual channel independent auto-id battery load buck-boost circuit of claim 4, wherein said high voltage isolation module comprises a power supply regulator, a gate clamp zener diode, a PMOS isolation tube, a first substrate switching diode, and a second substrate switching diode; the source electrode of the PMOS isolation tube is connected to a port VIN, the drain electrode of the PMOS isolation tube is connected to a port VOUT, and the grid electrode of the PMOS isolation tube is connected to an output node ENB of the power supply regulator; the input of the power regulator is connected to port VIN and its output is connected to output node ENB; the anode of the grid clamping Zener diode is connected to the output node ENB, and the cathode of the grid clamping Zener diode is connected to the source electrode of the PMOS isolation tube; the anode of the first substrate switching diode is connected to a port VIN, and the cathode of the first substrate switching diode is connected to the substrate of the PMOS isolation tube; the anode of the second substrate switching diode is connected to VOUT, and the cathode of the second substrate switching diode is connected to the substrate of the PMOS isolation tube.

7. The dual-channel independent automatic battery load identification buck-boost circuit as claimed in claim 1, wherein said buck-boost control module comprises a PMOS transistor, an NMOS transistor, a mode selector, a substrate selector, a buck-boost controller; the source electrode of the PMOS tube is connected to VOUT, the drain electrode of the PMOS tube is connected to LX, and the grid electrode of the PMOS tube is connected to the VPG output end of the buck-boost controller; the source electrode of the NMOS tube is connected to the ground, the drain electrode of the NMOS tube is connected to the LX, and the gate electrode of the NMOS tube is connected to the VNG output end of the buck-boost controller; the input connection end of the mode selector is connected to VIN, and the output end of the mode selector is connected to the input end VMOD of the buck-boost controller; two input ends of the substrate selector are VOUT and BAT respectively, and an output end of the substrate selector is VSUB and is connected to the input end of the buck-boost controller; the 4 inputs of the buck-boost controller are VOUT, VMOD, VSUB and BAT, respectively, and the two outputs are VPG and VNG, respectively.

8. The dual channel independent auto-id battery load buck-boost circuit of claim 7, wherein V41 is 4.5 volts, V42 is 4.7 volts, V43 is 5 volts and V44 is 6.5 volts.

9. The dual-channel independent automatic battery load identification buck-boost circuit according to claim 1, further comprising an input capacitor and a battery bypass capacitor, said input capacitor being connected between said port VIN and ground GND; the battery bypass capacitor is connected between the anode of the rechargeable battery and a ground end GND.

10. The dual-channel independent auto-identification battery load buck-boost circuit of claim 1, further comprising a first output capacitor and a second output capacitor, said first output capacitor being connected between said first battery load and ground GND; the second output capacitor is connected between the second battery load and a ground terminal GND.