CN218415815U - Common mode surge protection circuit of PSE output on floating AP equipment of PD input power supply - Google Patents

Abstract

The utility model relates to a communication terminal equipment field, concretely relates to common mode surge protection circuit of PSE output on the floating ground AP equipment of PD input power supply, including PD port circuit, PSE port circuit, power gating combination and TVS subassembly, PD port circuit connects the one end at the power gating combination, PSE port circuit connects on the other end of power gating combination, TVS unit mount is between PSE port circuit and PD port circuit, the utility model discloses a common mode surge protection circuit of PSE output on the floating ground AP equipment of PD input power supply, through design installation time delay device inductance coil accelerate PSE port circuit to the switch to the ground discharge with to the problem that the NEG end of PSE punctures and cooperation installation TVS subassembly can solve among the prior art PSE port circuit and by common mode voltage, occupy the PCB wiring area little, overall cost is low, especially the cluster does not have extra power loss at the inductance of power negative terminal, does not influence the normal transmission of high-speed ethernet signal.

Description

Common mode surge protection circuit of PSE output on floating AP equipment of PD input power supply

Technical Field

The utility model relates to a communication terminal equipment field, concretely relates to common mode surge protection circuit of PSE output on floating ground AP equipment of PD input power supply.

Background

AP, i.e. WiFi wireless Access Point, wireless AP (Access Point): i.e., a wireless access point, which is used for the wireless switch of the wireless network and is also the core of the wireless network. The wireless AP is an access point for a mobile computer user to enter a wired network, is mainly used in broadband families, buildings and parks, and can cover dozens of meters to hundreds of meters. A wireless AP (also called a session point or an access bridge) is a broad name, and includes not only a simple wireless access point (wireless AP), but also a generic name of devices such as a wireless router (including a wireless gateway and a wireless bridge).

With the development of networks, more and more network devices are provided. This is the POE (Power over Ethernet) technology. The starting point of the Ethernet power supply technology is very simple, namely small network equipment such as an IP telephone, a WLAN access point, a network camera and the like can directly obtain power from an Ethernet line, and a power line does not need to be laid independently so as to simplify system wiring. In a POE system, there are two important components. The Power source is called "Power Sourcing Equipment" (PSE), and the Power source is called "Powered Device" (PD). The PSE is responsible for injecting power into the ethernet cable and implementing power planning and management.

When the PD is connected with a PSE switch connected with the ground, the energy can form a ground discharge channel from the PD to the switch through a network cable, the discharge channel of a long network cable is not smooth, the PSE chip is often damaged, the PSE is subjected to non-online test, and the damaged end is a NEG end which is in a non-conduction state with GND on the PSE chip.

SUMMERY OF THE UTILITY MODEL

The utility model provides a PSE output's common mode surge protection circuit on floating ground AP equipment of PD input power supply, its aim at protection PSE port circuit is not punctured by common mode voltage.

To achieve the purpose, the utility model adopts the following technical proposal:

the common-mode surge protection circuit comprises a PD port circuit, a PSE port circuit, a power gating combination and a TVS component, wherein the PD port circuit is connected to one end of the power gating combination, the PSE port circuit is connected to the other end of the power gating combination, and the TVS component is installed between the PSE port circuit and the PD port circuit.

Furthermore, the PD port circuit comprises a first PD and a second PD, a first POS pin and a first NEG pin of the first PD are respectively connected to one end of the power gating combination through wires, and a second POS pin and a second NEG pin of the second PD are respectively connected to one end of the power gating combination.

Furthermore, the PSE port circuit comprises a PSE chip and an inductance coil, one end of the inductance coil is connected to the NEG of the PSE chip, the pin at the other end of the inductance coil is a NEG0 pin, one end of the inductance coil is connected to the NEG pin of the PSE chip, the power pin of the PSE chip is connected to the 54V pin of the power gating combination, and the GND pin of the PSE chip is connected to the ground pin of the power gating combination.

Further, the TVS subassembly includes TVS, no. two TVS, no. three TVS, no. four TVS and No. five TVS, the POS pin of a PD and No. two PDs links to each other with a TVS and No. two TVS one end pins respectively and a TVS and No. two TVS other end pins all link to each other with the POS pin of PSE chip, the NEG pin of a PD and No. two PDs links to each other with No. three TVS and No. four TVS one end pins respectively and No. three TVS and No. four TVS other end pins all link to each other with inductance coils ' NEG0 pin, the POS pin of PSE chip is connected to No. five TVS's one end, and the other end is connected on inductance coils ' NEG 0.

The utility model has the advantages that:

1. the utility model discloses a PSE port circuit is by the problem that common mode voltage punctures among the prior art can be solved to the PSE port circuit through designing installation time delay device inductance coil to the ground of switch release and to the release of the NEG end of PSE and cooperation installation TVS subassembly on the floating ground AP equipment of PD input power supply.

2. The lightning stroke of positive and negative end on the PSE is swiftly guided to the positive and negative end after two PD polarity discernments with TVS, through far-end PSE switch to ground release, establish ties suitable power inductance for the NEG end of PSE chip simultaneously, utilizes the time delay effect of inductance, blocks that the surge high pressure of PSE net gape adds the NEG end of PSE chip to pass through common mode surge test smoothly. The circuit is simple and effective, easy to implement, small in occupied PCB wiring area and low in overall cost, and particularly, the inductor connected in series at the negative end of the power supply has no extra power loss, so that the normal transmission of high-speed Ethernet signals is not influenced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art description will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive labor.

FIG. 1 is an exploded view of the whole three-dimensional structure of the present invention;

Detailed Description

In order to make the technical means, creation characteristics, achievement purpose and efficacy of the utility model easy to understand and understand, the utility model is further explained by combining with the specific figure below.

Referring to fig. 1, a common mode surge protection circuit at the output end of a PSE on a PD input-powered floating-ground AP device comprises a PD port circuit, a PSE port circuit, a power gating combination and a TVS component, wherein the PD port circuit is connected to one end of the power gating combination, the PSE port circuit is connected to the other end of the power gating combination, the TVS component is installed between the PSE port circuit and the PD port circuit, the PSE switch supplies power to the PD port of the AP, the PD port transfers power to the PSE port of the AP, other devices are connected through an RJ-45 type interface on the port of the AP to obtain power, the TVS component is installed between the PSE port circuit and the PD port circuit to enable the common mode voltage of the PSE port circuit to be discharged to the ground through a far-end PSE switch, the PSE port circuit is prevented from being broken down by voltage due to the common mode voltage, and the power gating combination can provide corresponding current according to the needs of the PSE port device connected with the AP.

Referring to fig. 1, the PD port circuit includes a first PD and a second PD, where a POS pin and a NEG pin of the first PD are respectively connected to one end of a power gating combination by a wire, a POS pin and a NEG pin of the second PD are respectively connected to one end of the power gating combination, other devices are connected to the PSE port of the AP through an RJ-45 interface, the PSE switch supplies power to the PD port of the AP, different PD ports are selected to supply power according to different power demands, and the PD port transmits power to the PSE port of the AP, so that the other devices are supplied with power.

Referring to fig. 1, the PSE port circuit includes a PSE chip and an inductor, one end of the inductor is connected to a NEG of the PSE chip, a pin at the other end is a NEG0 pin, one end of the inductor is connected to the NEG pin of the PSE chip, a power pin of the PSE chip is connected to a 54V pin of a power gating combination, a GND pin of the PSE chip is connected to a ground of the power gating combination, the power inductor is a delay device of a device, the NEG terminal of the PSE chip is connected in series with a suitable power inductor, on one hand, the leakage to the ground of a switch is accelerated as much as possible, on the other hand, the leakage to the NEG terminal of the PSE is blocked by the delay device, so that the common mode high voltage is leaked to the switch, the voltage appearing at the NEG terminal of the PSE chip is only a residual voltage of a low magnitude, the problem that the source S and the drain D of a MOS transistor inside the NEG port break down due to high voltage is solved, the delay device can use a small resistor of a suitable power, so that the power inductor is used, the problem that the impedance of the resistor is not enough to cause additional power consumption is avoided, and the problem that the inductance is generally used for decoupling of a 3mH is preferably selected according to 3.

Referring to fig. 1, the TVS component includes a first TVS, a second TVS, a third TVS, a fourth TVS and a fifth TVS, the POS pins of the first PD and the second PD are respectively connected to one end pins of the first TVS and the second TVS, and the other end pins of the first TVS and the second TVS are both connected to POS pins of the PSE chip, the NEG pins of the first PD and the second PD are respectively connected to one end pins of the third TVS and the fourth TVS, and the other end pins of the third TVS and the fourth TVS are both connected to NEG0 pin of the inductor coil, one end of the fifth TVS is connected to the POS pin of the PSE chip, and the other end of the fifth TVS is connected to NEG0 of the inductor coil, the TVS can select smccj 58CA, the POS and the NEG of the PSE cross a normal working path, the bidirectional TVS is used to manufacture a short and short path connected to the POS and NEG of the PD end, the TVS is quickly guided to two positive and negative ends of the PD identified by polarity, the positive and negative and the NEG passes through a far end protection circuit, and the PSE protection circuit is matched with a common mode switch, and a surge port is obtained.

The foregoing shows and describes the basic principles and principal features of the invention, together with the advantages thereof. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only illustrative of the principles of the present invention, and that various changes and modifications may be made without departing from the spirit and scope of the present invention, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (4)

1. The common-mode surge protection circuit for the PSE output end of the floating-ground AP equipment powered by the PD input is characterized by comprising a PD port circuit, a PSE port circuit, a power gating combination and a TVS component, wherein the PD port circuit is connected to one end of the power gating combination, the PSE port circuit is connected to the other end of the power gating combination, and the TVS component is installed between the PSE port circuit and the PD port circuit.

2. The circuit of claim 1, wherein the PD port circuit comprises a PD I and a PD II, the POS pin I and the NEG pin I of the PD I are respectively connected to one end of the power gating assembly by wires, and the POS pin II and the NEG pin II of the PD II are respectively connected to one end of the power gating assembly.

3. The circuit of claim 2, wherein the PSE port circuit comprises a PSE chip and an inductor, one end of the inductor is connected to a NEG of the PSE chip, a pin at the other end of the inductor is a NEG0 pin, one end of the inductor is connected to the NEG pin of the PSE chip, a power pin of the PSE chip is connected to a 54V pin of the power gating combination, and a GND pin of the PSE chip is connected to a ground pin of the power gating combination.

4. The common-mode surge protection circuit at the output end of the PSE on the PD input-powered floating-ground AP equipment as claimed in claim 3, wherein the TVS component comprises a TVS I, a TVS II, a TVS III, a TVS IV and a TVS V, the POS pins of the PD I and the PD II are respectively connected with one end pin of the TVS I and the TVS II and the other end pin of the TVS I and the TVS II are respectively connected with the POS pin of the PSE chip, the NEG pins of the PD I and the PD II are respectively connected with one end pin of the TVS III and the TVS IV and the other end pin of the TVS III and the TVS II are respectively connected with the NEG0 pin of the inductance coil, one end of the TVS V is connected with the POS pin of the PSE chip and the other end is connected with the NEG0 of the inductance coil.

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