CN218386930U - Novel dual power supply protection circuit - Google Patents
Novel dual power supply protection circuit Download PDFInfo
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- CN218386930U CN218386930U CN202222401741.3U CN202222401741U CN218386930U CN 218386930 U CN218386930 U CN 218386930U CN 202222401741 U CN202222401741 U CN 202222401741U CN 218386930 U CN218386930 U CN 218386930U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/30—Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S20/00—Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
- Y04S20/20—End-user application control systems
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Abstract
A novel dual-power supply protection circuit relates to the technical field of dual-power supply protection circuits. The technical defects that two diodes are connected in parallel, loss is large and efficiency is low in two-way power supply input protection are overcome, wherein a first sampling circuit collects the input voltage state of a main power supply input end, a first MOS tube switching circuit starts and conducts power supply output between the main power supply input end and a power supply output end under the condition that the main power supply input end has the voltage input state, meanwhile, a switching circuit controls a second sampling circuit to be invalid, and a second MOS tube switching circuit disconnects the power supply output between a secondary power supply input end and the power supply output end; no matter be main power input and secondary power input whether there is power input simultaneously, the short circuit condition can not appear in two way powers, compares mechanical switch and switches the power supply structure, the utility model discloses it is little to have to account for the space, compares two diode parallel circuit structures, and it is little to have the loss, uses extensively.
Description
Technical Field
The utility model relates to two electric power supply protection circuit technical field.
Background
At present, electronic circuits basically need power supplies, and some electronic circuits also need two power supplies, and a conventional common method is to add a mechanical switch to switch power supplies, as shown in fig. 1, two power supplies are input, and one power supply is output. However, in modern electronic circuits, space and cost constraints cannot be achieved with mechanical switches. Therefore, an electronic circuit is required to complete the operation, a signal switch is available on the market at present, but no power switch chip is available, and the common method is to connect two diodes in parallel, as shown in fig. 2, the two diodes are connected in parallel to realize dual-voltage power supply, but loss occurs and the efficiency is reduced.
SUMMERY OF THE UTILITY MODEL
To sum up, the utility model discloses a solve and to have now adopted two diodes to connect in parallel, the loss that two way power supply input protection exists is big, and the technique of inefficiency is not enough, and provides a novel dual power supply protection circuit.
For solving the utility model provides a technique is not enough, and the technical scheme of adoption is:
a novel dual-power supply protection circuit comprises a main power supply input end, an auxiliary power supply input end and a power supply output end; the method is characterized in that: a first sampling circuit and a first MOS tube switch circuit are arranged between the main power supply input end and the power supply output end; a switching circuit, a second sampling circuit and a second MOS tube switching circuit are arranged between the auxiliary power supply input end and the power supply output end; the first sampling circuit collects the input voltage state of the main power supply input end, and under the condition that the main power supply input end has voltage input, the first MOS tube switch circuit starts to conduct the power supply output between the main power supply input end and the power supply output end, meanwhile, the switching circuit controls the second sampling circuit to be invalid, and the second MOS tube switch circuit disconnects the power supply output between the auxiliary power supply input end and the power supply output end; under the condition that the input end of the main power supply has no voltage input, the first MOS tube switch circuit is disconnected, the switching circuit fails, the second sampling circuit collects the input voltage state of the input end of the auxiliary power supply, and under the condition that the input end of the auxiliary power supply has voltage input, the second MOS tube switch circuit opens and conducts the power supply output between the input end of the auxiliary power supply and the power supply output end.
As to the technical scheme of the utility model for further limiting includes:
the first sampling circuit comprises a first resistor and a second resistor which are connected between the main power supply input end and the ground in series; the first MOS tube switch circuit comprises a first P-MOS tube for controlling the connection or disconnection between the main power supply input end and the power supply output end, and a fourth N-MOS tube for controlling the connection of the first P-MOS tube according to the high level output by the common end of the first resistor and the second resistor.
The second sampling circuit comprises a sixth resistor and a seventh resistor which are connected between the input end of the secondary power supply and the ground in series; the switching circuit comprises a sixth N-MOS tube connected between the common end of the sixth resistor and the seventh resistor and the ground, and the G pole of the sixth N-MOS tube is connected with the common end of the first resistor and the second resistor.
The second MOS tube switch circuit comprises a third P-MOS tube and a second P-MOS tube which are connected in series between the input end of the auxiliary power supply and the output end of the power supply and prevent the power supply from flowing backwards, and a fifth N-MOS tube which controls the conduction of the third P-MOS tube and the second P-MOS tube according to the high level output by the common end of the sixth resistor and the seventh resistor.
The beneficial effects of the utility model are that: the utility model discloses no matter be whether main power input and secondary power input have power simultaneously input, the short circuit condition can not appear in two way powers, compares mechanical switch and switches the power supply structure, the utility model discloses it is little to have to account for the space, compares two diode parallel circuit structures, and it is little to have the loss, uses extensively.
Drawings
FIG. 1 is a schematic diagram of a dual-voltage power supply circuit for switching power supply of a conventional mechanical switch;
FIG. 2 is a schematic diagram of a conventional dual voltage supply circuit with two diodes connected in parallel;
fig. 3 is a schematic circuit diagram of the present invention.
Detailed Description
The circuit structure of the present invention will be further described with reference to the accompanying drawings and preferred embodiments of the present invention.
Referring to fig. 3, the utility model discloses a novel dual power supply protection circuit, which comprises a main power input terminal VINPUT1, an auxiliary power input terminal VINPUT1 and a power output terminal VOUTPUT; a first sampling circuit and a first MOS tube switch circuit are arranged between the main power supply input end VINPUT1 and the power supply output end VOUTPUT; and a switching circuit, a second sampling circuit and a second MOS tube switching circuit are arranged between the auxiliary power supply input end VINPUT2 and the power supply output end VOUTPUT.
The first sampling circuit comprises a first resistor R1 and a second resistor R2 which are connected between the main power input end VINPUT1 and the ground in series; the first MOS tube switch circuit comprises a first P-MOS tube Q1 for controlling the connection or disconnection between a main power supply input end VINPUT1 and a power supply output end VOUTPUT, and a fourth N-MOS tube Q4 for controlling the connection of the first P-MOS tube Q1 according to a high level output by the common end of a first resistor R1 and a second resistor R2. The first sampling circuit collects the input voltage state of a main power supply input end VINPUT1, when the main power supply input end VINPUT1 has a voltage input state, a G pole of a fourth N-MOS tube Q4 obtains a high level, the fourth N-MOS tube Q4 is conducted, the G pole of a first P-MOS tube Q1 is pulled down to a low level, and the first P-MOS tube Q1 is conducted due to the fact that the first P-MOS tube Q1 is a P-channel MOS tube, namely the first MOS tube switching circuit starts to conduct power supply output between the main power supply input end VINPUT1 and a power supply output end VOUTPUT.
When the power output between the auxiliary power input end VINPUT2 and the power output end VOUTPUT is cut off under the voltage input state of the main power input end VINPUT1, the switching circuit controls the second sampling circuit to be invalid at the same time when the high level output by the common end of the first resistor R1 and the second resistor R2 is output, and the second MOS tube switching circuit cuts off the power output between the auxiliary power input end and the power output end; in this embodiment, the second sampling circuit includes a sixth resistor R6 and a seventh resistor R7 connected in series between the secondary power input terminal VINPUT2 and ground; the switching circuit comprises a sixth N-MOS transistor Q6 connected between the common end of the sixth resistor R6 and the seventh resistor R7 and the ground, and the G pole of the sixth N-MOS transistor Q6 is connected with the common end of the first resistor R1 and the second resistor R2. When the output high level of the common end of the first resistor R1 and the second resistor R2 is high, because the sixth N-MOS transistor Q6 is an N-channel MOS transistor, the sixth N-MOS transistor Q6 is conducted, the resistor R7 is directly short-circuited, which is equivalent to failure of a switching circuit, the common end of the sixth resistor R6 and the seventh resistor R7 is pulled down to be low level, and the second MOS transistor switching circuit is in an off state no matter whether the auxiliary power supply input end VINPUT2 has input of a power supply or not. When the main power input end VINPUT1 has no power input and the auxiliary power input end VINPUT2 has power input, the common end of the first resistor R1 and the second resistor R2 outputs low level, the sixth N-MOS tube Q6 is disconnected, the sixth resistor R6 and the seventh resistor R7 form a second sampling circuit which can collect the power input state of the auxiliary power input end VINPUT2, and the second MOS tube switching circuit starts the power output between the auxiliary power input end VINPUT2 and the power output end VOUTPUT.
In order to avoid that the power of the power output end VOUTPUT flows backwards to the auxiliary power input end VINPUT2 end through the second MOS tube switching circuit, the second MOS tube switching circuit comprises a third P-MOS tube Q3 and a second P-MOS tube Q2 which are connected in series between the auxiliary power input end VINPUT2 and the power output end VOUTPUT in a polarity opposite mode and used for preventing the power from flowing backwards, and a fifth N-MOS tube Q5 which controls the conduction of the third P-MOS tube Q3 and the second P-MOS tube Q2 according to the high level output by the common end of a sixth resistor R6 and a seventh resistor R7. When the sixth resistor R6 and the seventh resistor R7 form a second sampling circuit to acquire a state of power input at the secondary power input terminal VINPUT2, the G of the fifth N-MOS transistor Q5 is at a high level, because the fifth N-MOS transistor Q5 is an N-channel MOS transistor, the fifth N-MOS transistor Q5 is turned on, the G of the third P-MOS transistor Q3 and the second P-MOS transistor Q2 is pulled down to a low level, the third P-MOS transistor Q3 and the second P-MOS transistor Q2 are turned on, and the secondary power input terminal VINPUT2 provides the power output at the power output terminal VOUTPUT.
In summary, if both the main power input terminal VINPUT1 and the secondary power input terminal VINPUT2 have voltage inputs, the output voltage of the power output terminal VOUTPUT is the voltage of the main power input terminal VINPUT 1; if the main power input end VINPUT1 has voltage input and the auxiliary power input end VINPUT2 has no voltage input, the output voltage of the power output end VOUTPUT is the voltage of the main power input end VINPUT 1; if the main power input terminal VINPUT1 has no voltage input and the auxiliary power input terminal VINPUT2 has voltage input, the output voltage of the power output terminal VOUTPUT is the voltage of the auxiliary power input terminal VINPUT 2. The utility model discloses can realize high-efficient automatic switch-over control, the protection control circuit of MOS pipe compares diode protection circuit, low power dissipation, and application scope is wide.
Claims (4)
1. A novel dual-power supply protection circuit comprises a main power supply input end, an auxiliary power supply input end and a power supply output end; the method is characterized in that:
a first sampling circuit and a first MOS tube switch circuit are arranged between the main power supply input end and the power supply output end;
a switching circuit, a second sampling circuit and a second MOS tube switching circuit are arranged between the auxiliary power supply input end and the power supply output end;
the first sampling circuit collects the input voltage state of the main power supply input end, and under the condition that the main power supply input end has voltage input, the first MOS tube switch circuit starts to conduct the power supply output between the main power supply input end and the power supply output end, meanwhile, the switching circuit controls the second sampling circuit to be invalid, and the second MOS tube switch circuit disconnects the power supply output between the auxiliary power supply input end and the power supply output end; under the condition that the input end of the main power supply has no voltage input, the first MOS tube switch circuit is disconnected, the switching circuit fails, the second sampling circuit collects the input voltage state of the input end of the auxiliary power supply, and under the condition that the input end of the auxiliary power supply has voltage input, the second MOS tube switch circuit opens and conducts the power supply output between the input end of the auxiliary power supply and the power supply output end.
2. The novel dual-power-supply protection circuit of claim 1, characterized in that: the first sampling circuit comprises a first resistor and a second resistor which are connected between the main power supply input end and the ground in series; the first MOS tube switch circuit comprises a first P-MOS tube for controlling the connection or disconnection between the main power supply input end and the power supply output end, and a fourth N-MOS tube for controlling the connection of the first P-MOS tube according to the high level output by the common end of the first resistor and the second resistor.
3. The novel dual-power-supply protection circuit of claim 1 or 2, characterized in that: the second sampling circuit comprises a sixth resistor and a seventh resistor which are connected between the input end of the auxiliary power supply and the ground in series; the switching circuit comprises a sixth N-MOS tube connected between the common end of the sixth resistor and the seventh resistor and the ground, and the G pole of the sixth N-MOS tube is connected with the common end of the first resistor and the second resistor.
4. The novel dual-power-supply protection circuit of claim 3, characterized in that: the second MOS tube switch circuit comprises a third P-MOS tube and a second P-MOS tube which are connected in series between the input end of the auxiliary power supply and the output end of the power supply and prevent the power supply from flowing backwards, and a fifth N-MOS tube which controls the conduction of the third P-MOS tube and the second P-MOS tube according to the high level output by the common end of the sixth resistor and the seventh resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222401741.3U CN218386930U (en) | 2022-09-09 | 2022-09-09 | Novel dual power supply protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222401741.3U CN218386930U (en) | 2022-09-09 | 2022-09-09 | Novel dual power supply protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218386930U true CN218386930U (en) | 2023-01-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222401741.3U Active CN218386930U (en) | 2022-09-09 | 2022-09-09 | Novel dual power supply protection circuit |
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| CN (1) | CN218386930U (en) |
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- 2022-09-09 CN CN202222401741.3U patent/CN218386930U/en active Active
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