CN218301453U - Anti 5G signal interference's single output frequency reduction circuit of double polarization single local oscillator - Google Patents
Anti 5G signal interference's single output frequency reduction circuit of double polarization single local oscillator Download PDFInfo
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- CN218301453U CN218301453U CN202221657670.7U CN202221657670U CN218301453U CN 218301453 U CN218301453 U CN 218301453U CN 202221657670 U CN202221657670 U CN 202221657670U CN 218301453 U CN218301453 U CN 218301453U
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Abstract
The invention relates to a dual-polarization single-local-oscillator single-output frequency-reducing circuit capable of resisting 5G signal interference, wherein a signal received by a horizontal signal receiving circuit sequentially passes through a first filter, a first IF (intermediate frequency) mixing amplifying circuit and a first IF filtering circuit and then outputs a horizontal IF signal to an IF (intermediate frequency) mixing circuit, a signal received by a vertical signal receiving circuit sequentially passes through a second filter, a second IF mixing amplifying circuit and a second IF filtering circuit and then outputs a vertical IF signal to the IF mixing circuit, the first IF filtering circuit, the second IF filtering circuit and the IF mixing circuit are respectively connected with a signal switching control circuit, the signal switching control circuit controls the IF mixing circuit to adjust and mix the horizontal IF signal and the vertical IF signal or select one of the horizontal IF signal and the vertical IF signal to adjust and then outputs the signal to a signal output circuit, and the first filter and the second filter adopt a brand new design structure, so that the 5G signal interference can be better prevented, and a frequency-reducing device can normally work and a user can normally watch.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of frequency demultipliers, in particular to a dual-polarized single-local-oscillator single-output frequency demultiplier circuit capable of resisting 5G signal interference.
[ background ] A method for producing a semiconductor device
With the arrival of the 5G era, the interference to satellite signals is increased, and the frequency of the current 5G signals is very close to the frequency input frequency 3.7GE of the current C-band at 3.4-3.6G, so that when the three 5G signals of unicom, telecom and mobile work together at the same time and generate strong interference, a great problem is brought to the normal viewing of the satellite signals. Therefore, the 5G signal frequency causes strong interference to the C-band received signal, the MER value decreases, the LNB oscillates greatly, and the satellite signal cannot be received normally. However, the circuit of the current prior art frequency demultiplier for resisting 5G interference usually adopts the traditional comb-shaped dual-BPF filter, and the interference signal cannot be filtered out completely. For example, chinese utility model patent publication No. CN213186293U discloses a high frequency full bandwidth down converter and down converter, and the filter 400 adopted in the down converter is a simple rectangular structure; also, for example, the chinese patent publication No. CN1272000A discloses a surface wave SAW resonator which adopts a conventional comb structure, and for example, the chinese utility model patent publication No. CN113708029A discloses a three-mode high-temperature superconducting filter which also adopts a conventional filter with a common shape. Therefore, a novel filter-based dual-polarized single-output frequency reduction circuit capable of resisting 5G signal interference needs to be researched to prevent 5G signal interference, so that the frequency reducer can work normally and is not interfered by 5G, and a user can watch television normally.
[ summary of the invention ]
In order to solve the above problems, the invention provides a dual-polarized single-local-oscillator single-output frequency-reducing circuit capable of resisting 5G signal interference, which effectively prevents 5G signal interference, so that the frequency-reducing device can normally work and is not interfered by 5G, and users can normally watch television.
In order to achieve the purpose, the invention provides the following technical scheme:
a dual-polarized single-local-oscillator single-output frequency-reducing circuit resisting 5G signal interference comprises a horizontal signal receiving circuit 1, a vertical signal receiving circuit 2, a first filter 3, a second filter 4, a first IF mixing amplifying circuit 5, a second IF mixing amplifying circuit 6, a first IF filtering circuit 7, a second IF filtering circuit 8, a signal output circuit 9, a power supply circuit 10 for providing working voltage, an IF mixing circuit 11 and a signal switching control circuit 12, wherein signals received by the horizontal signal receiving circuit 1 sequentially pass through the first filter 3, the first IF mixing amplifying circuit 5 and the first IF filtering circuit 7 and then output horizontal IF signals to the IF mixing circuit 11, signals received by the vertical signal receiving circuit 2 sequentially pass through the second filter 4, the second IF mixing amplifying circuit 6 and the second IF filtering circuit 8 and then output vertical IF signals to the IF mixing circuit 11, the first IF filtering circuit 7, the second IF filtering circuit 8 and the vertical IF mixing amplifying circuit 11 are further respectively connected with the signal switching control circuit 12, the signal switching control circuit 12 controls the vertical IF mixing amplifying circuit 12 to output vertical IF signals to the first IF mixing amplifying circuit 308 and the vertical IF signals, the vertical IF amplifying circuit 308 and the vertical signals, the first IF receiving circuit 301 and the vertical signal output to the first IF amplifying circuit 308, the first IF signals to the first IF amplifying circuit 301, the first IF amplifying circuit and the vertical signal receiving circuit 301, the other end of the eighth vertical microstrip line 308 is connected to a sixth short microstrip line 336 facing the first IF mixer-amplifier circuit 5; a plurality of first microstrip line groups and second microstrip line groups which are coupled and connected are distributed in an interval array manner between the first vertical microstrip line 301 and the eighth vertical microstrip line 308.
As a preferred embodiment, further defined as: the first microstrip line group comprises a second vertical microstrip line 302, a third vertical microstrip line 303, a fourth vertical microstrip line 304, a first transverse microstrip line 321, a second transverse microstrip line 322, a second short microstrip line 332 and a third short microstrip line 333; one end of the second vertical microstrip line 302 is connected with one end of the fourth vertical microstrip line 304 through the first transverse microstrip line 321, the inner side of the other end of the second vertical microstrip line 302 is connected with a second short microstrip line 332 deviating from the first vertical microstrip line 301, one end of the third vertical microstrip line 303 is connected with the middle part of the first transverse microstrip line 321 and is positioned between the second vertical microstrip line 302 and the fourth vertical microstrip line 304, the other end of the third vertical microstrip line 303 is connected with the second transverse microstrip line 322, and the other end of the fourth vertical microstrip line 304 is connected with a third short microstrip line 333 facing the third vertical microstrip line 303;
the second microstrip line group comprises a fifth vertical microstrip line 305, a sixth vertical microstrip line 306, a seventh vertical microstrip line 307, a third transverse microstrip line 323, a fourth transverse microstrip line 324, a fourth short microstrip line 334 and a fifth short microstrip line 335; the fifth vertical microstrip line 305 is vertically arranged and coupled with the fourth vertical microstrip line 304, one end of the fifth vertical microstrip line 305 is connected with a fourth short microstrip line 334, the other end of the fifth vertical microstrip line 305 is connected with the other end of the seventh vertical microstrip line 307 through a third transverse microstrip line 323, one end of the seventh vertical microstrip line 307 is connected with a fifth short microstrip line 335, the other end of the sixth vertical microstrip line 306 is connected with the middle part of the third transverse microstrip line 323 and is located between the fifth vertical microstrip line 305 and the seventh vertical microstrip line 307, and one end of the sixth vertical microstrip line 306 is connected with a fourth transverse microstrip line 324.
As a preferred embodiment, further defined is: the number of the first microstrip line groups is 3, the number of the second microstrip line groups is 2, and the second microstrip line group is located between the two first microstrip line groups.
As a preferred embodiment, further defined is: the width of the end of the third vertical microstrip line 303 connected with the first transverse microstrip line 321 is greater than that of the end connected with the second transverse microstrip line 322; the width of the end of the sixth vertical microstrip line 306 connected to the third transverse microstrip line 323 is greater than the width of the end connected to the fourth transverse microstrip line 324.
As a preferred embodiment, further defined as: the third vertical microstrip line 303 is connected with the second transverse microstrip line 322 at a position which is on the left of the middle part of the third vertical microstrip line 303, so that the length of the second transverse microstrip line 322 which is positioned on the right side of the third vertical microstrip line 303 is greater than the length of the third vertical microstrip line 303 on the left side of the third vertical microstrip line 303; the sixth vertical microstrip line 306 is connected to the fourth horizontal microstrip line 324 at a position which is on the left of the middle of the sixth vertical microstrip line 306, so that the length of the fourth horizontal microstrip line 324 on the right side of the sixth vertical microstrip line 306 is greater than the length of the fourth horizontal microstrip line 324 on the left side of the sixth vertical microstrip line 306.
As a preferred embodiment, further defined as: the second filter 4 includes a ninth vertical microstrip 309, a seventh short microstrip 337, a sixteenth vertical microstrip 316, and a twelfth short microstrip 342, one end of the ninth vertical microstrip 309 is connected to the vertical signal receiving circuit 2, the other end of the ninth vertical microstrip 309 is connected to the seventh short microstrip 337 facing the vertical signal receiving circuit 2, one end of the sixteenth vertical microstrip 316 is connected to the second IF mixing and amplifying circuit 6, and the other end of the sixteenth vertical microstrip 316 is connected to the twelfth short microstrip 342 facing the second IF mixing and amplifying circuit 6; a plurality of third microstrip line groups and fourth microstrip line groups which are coupled and connected are distributed in an interval array between the ninth vertical microstrip line 309 and the sixteenth vertical microstrip line 316.
As a preferred embodiment, further defined as: the third microstrip line group comprises a tenth vertical microstrip line 310, an eleventh vertical microstrip line 311, a twelfth vertical microstrip line 312, a fifth transverse microstrip line 325, a sixth transverse microstrip line 326, an eighth short microstrip line 338 and a ninth short microstrip line 339; one end of the tenth vertical microstrip line 310 is connected with one end of the twelfth vertical microstrip line 312 through a fifth transverse microstrip line 325, the inner side of the other end of the tenth vertical microstrip line 310 is connected with an eighth short microstrip line 338 deviating from the ninth vertical microstrip line 309, one end of the eleventh vertical microstrip line 311 is connected with the middle part of the fifth transverse microstrip line 325 and is positioned between the tenth vertical microstrip line 310 and the twelfth vertical microstrip line 312, the other end of the eleventh vertical microstrip line 311 is connected with a sixth transverse microstrip line 326, and the other end of the twelfth vertical microstrip line 312 is connected with a ninth short microstrip line 339 facing the eleventh vertical microstrip line 311;
as a preferred embodiment, further defined as: the fourth microstrip line group comprises a thirteenth vertical microstrip line 313, a fourteenth vertical microstrip line 314, a fifteenth vertical microstrip line 315, a seventh transverse microstrip line 327, an eighth transverse microstrip line 328, a tenth short microstrip line 340 and an eleventh short microstrip line 341; the thirteenth vertical microstrip line 313 is vertically arranged and coupled with the twelfth vertical microstrip line 312, one end of the thirteenth vertical microstrip line 313 is connected with a tenth short microstrip line 340, the other end of the thirteenth vertical microstrip line 313 is connected with the other end of the fifteenth vertical microstrip line 315 through a seventh horizontal microstrip line 327, one end of the fifteenth vertical microstrip line 315 is connected with an eleventh short microstrip line 341, the other end of the fourteenth vertical microstrip line 314 is connected with the middle part of the seventh horizontal microstrip line 327 and is located between the thirteenth vertical microstrip line 313 and the fifteenth vertical microstrip line 315, and one end of the fourteenth vertical microstrip line 314 is connected with an eighth horizontal microstrip line 328.
As a preferred embodiment, further defined is: the number of the third microstrip line groups is 3, the number of the fourth microstrip line groups is 2, and the fourth microstrip line group is located between the two third microstrip line groups.
As a preferred embodiment, further defined as: the width of the end of the eleventh vertical microstrip line 311 connected to the fifth transverse microstrip line 325 is greater than the width of the end of the eleventh vertical microstrip line connected to the sixth transverse microstrip line 326; the width of the end of the fourteenth vertical microstrip line 314 connected to the seventh horizontal microstrip line 327 is greater than the width of the end of the fourteenth vertical microstrip line connected to the eighth horizontal microstrip line 328.
As a preferred embodiment, further defined is: the eleventh vertical microstrip line 311 is connected to a position of the sixth horizontal microstrip line 326, which is slightly to the left of the middle of the eleventh vertical microstrip line 311, so that the length of the sixth horizontal microstrip line 326 on the right side of the eleventh vertical microstrip line 311 is greater than the length of the eleventh vertical microstrip line 311 on the left side of the eleventh vertical microstrip line 311; the fourteenth vertical microstrip line 314 is connected to the eighth horizontal microstrip line 328 at a position which is slightly to the left of the middle portion of the fourteenth vertical microstrip line 314, so that the length of the eighth horizontal microstrip line 328 which is located on the right side of the fourteenth vertical microstrip line 314 is greater than the length of the eighth horizontal microstrip line 328 which is located on the left side of the fourteenth vertical microstrip line 314.
The beneficial effects of the invention are as follows: the first filter and the second filter which are created by the invention adopt a brand new design structure, are different from the traditional simple structure, and can better prevent 5G signal interference, so that the frequency demultiplier can work normally, and a user can watch the television normally.
[ description of the drawings ]
FIG. 1 is a schematic block diagram of the circuit created by the present invention;
FIG. 2 is a circuit diagram of the invention;
FIG. 3 is a circuit diagram of a first filter;
FIG. 4 is a circuit diagram of a second filter;
fig. 5 is a circuit diagram of a horizontal signal receiving circuit, a first filter, and a first IF mixer-amplifier circuit;
fig. 6 is a circuit diagram of the vertical signal receiving circuit, the second filter, the second IF mixing-amplifying circuit, and the second IF filtering circuit;
fig. 7 is a circuit diagram of a first IF filter circuit, a signal output circuit, a power supply circuit, and an IF mixer circuit;
fig. 8 is a circuit diagram of a signal switching control circuit.
[ detailed description ] embodiments
The invention will be described in further detail with reference to the following figures and detailed description:
as shown in fig. 1 to 8, a dual-polarized single-local-oscillator single-output frequency-reducing circuit capable of resisting 5G signal interference includes a horizontal signal receiving circuit 1, a vertical signal receiving circuit 2, a first filter 3, a second filter 4, a first IF mixing amplifying circuit 5, a second IF mixing amplifying circuit 6, a first IF filtering circuit 7, a second IF filtering circuit 8, a signal output circuit 9, a power supply circuit 10 for providing operating voltage, an IF mixing circuit 11, and a signal switching control circuit 12, wherein a signal received by the horizontal signal receiving circuit 1 sequentially passes through the first filter 3, the first IF mixing amplifying circuit 5, and the first IF filtering circuit 7 and then outputs a horizontal IF signal to the IF mixing circuit 11, a signal received by the vertical signal receiving circuit 2 sequentially passes through the second filter 4, the second IF mixing amplifying circuit 6, and the second IF filtering circuit 8 and then outputs an IF vertical signal to the IF mixing circuit 11, the first IF filter circuit 7, the second IF filter circuit 8 and the IF mixer circuit 11 are further respectively connected to the signal switching control circuit 12, the signal switching control circuit 12 controls the IF mixer circuit 11 to adjust and mix the horizontal IF signal and the vertical IF signal and output the adjusted signals to the signal output circuit 9 or select one of the horizontal IF signal and the vertical IF signal and output the adjusted signals to the signal output circuit 9, the signal output circuit 9 adjusts and outputs the horizontal IF signal and the vertical IF signal, and the circuit outputs signals with the frequency of 950 to 2050 MHz after the horizontal IF signal and the vertical IF signal are amplified and filtered by three stages, so that 5G signals are effectively filtered, and the anti-interference performance is high. In addition, the circuit can accept horizontal and vertical signals, can effectively avoid voltage interference when switching the horizontal and vertical signals, and greatly optimizes the performance of the low-noise frequency demultiplier. As shown in fig. 3, the first filter 3 includes a first vertical microstrip line 301, a first short microstrip line 331, an eighth vertical microstrip line 308, and a sixth short microstrip line 336, one end of the first vertical microstrip line 301 is connected to the horizontal signal receiving circuit 1, the other end of the first vertical microstrip line 301 is connected to the first short microstrip line 331 facing the horizontal signal receiving circuit 1, one end of the eighth vertical microstrip line 308 is connected to the first IF mixing and amplifying circuit 5, and the other end of the eighth vertical microstrip line 308 is connected to the sixth short microstrip line 336 facing the first IF mixing and amplifying circuit 5; a plurality of first microstrip line groups and second microstrip line groups which are coupled and connected are distributed in an interval array manner between the first vertical microstrip line 301 and the eighth vertical microstrip line 308.
More specifically, the first microstrip line group includes a second vertical microstrip line 302, a third vertical microstrip line 303, a fourth vertical microstrip line 304, a first transverse microstrip line 321, a second transverse microstrip line 322, a second short microstrip line 332, and a third short microstrip line 333; one end of the second vertical microstrip line 302 is connected with one end of the fourth vertical microstrip line 304 through the first transverse microstrip line 321, the inner side of the other end of the second vertical microstrip line 302 is connected with a second short microstrip line 332 deviating from the first vertical microstrip line 301, one end of the third vertical microstrip line 303 is connected with the middle part of the first transverse microstrip line 321 and is positioned between the second vertical microstrip line 302 and the fourth vertical microstrip line 304, the other end of the third vertical microstrip line 303 is connected with the second transverse microstrip line 322, and the other end of the fourth vertical microstrip line 304 is connected with a third short microstrip line 333 facing the third vertical microstrip line 303;
the second microstrip line group comprises a fifth vertical microstrip line 305, a sixth vertical microstrip line 306, a seventh vertical microstrip line 307, a third transverse microstrip line 323, a fourth transverse microstrip line 324, a fourth short microstrip line 334 and a fifth short microstrip line 335; the fifth vertical microstrip line 305 is vertically arranged and coupled with the fourth vertical microstrip line 304, one end of the fifth vertical microstrip line 305 is connected with a fourth short microstrip line 334, the other end of the fifth vertical microstrip line 305 is connected with the other end of the seventh vertical microstrip line 307 through a third transverse microstrip line 323, one end of the seventh vertical microstrip line 307 is connected with a fifth short microstrip line 335, the other end of the sixth vertical microstrip line 306 is connected with the middle part of the third transverse microstrip line 323 and is located between the fifth vertical microstrip line 305 and the seventh vertical microstrip line 307, and one end of the sixth vertical microstrip line 306 is connected with the fourth transverse microstrip line 324. The first filter 3 can better filter the 5G signal in the horizontal signal, and better prevent the 5G signal in the horizontal signal from interfering, so that the frequency demultiplier can work normally, and a user can watch the video normally.
In this embodiment, the number of the first microstrip line groups is 3, the number of the second microstrip line groups is 2, and the second microstrip line group is located between two first microstrip line groups. In order to achieve a more optimal effect of resisting 5G signal interference, the width of the end of the third vertical microstrip line 303 connected with the first transverse microstrip line 321 is greater than the width of the end connected with the second transverse microstrip line 322; the width of the end of the sixth vertical microstrip line 306 connected to the third transverse microstrip line 323 is greater than the width of the end connected to the fourth transverse microstrip line 324. The third vertical microstrip line 303 is connected to the second transverse microstrip line 322 at a position slightly to the left of the middle part of the third vertical microstrip line 303, so that the length of the second transverse microstrip line 322 on the right side of the third vertical microstrip line 303 is greater than the length of the third vertical microstrip line 303 on the left side of the third vertical microstrip line 303; the sixth vertical microstrip line 306 is connected to the fourth horizontal microstrip line 324 at a position which is on the left of the middle of the sixth vertical microstrip line 306, so that the length of the fourth horizontal microstrip line 324 on the right side of the sixth vertical microstrip line 306 is greater than the length of the fourth horizontal microstrip line 324 on the left side of the sixth vertical microstrip line 306.
As shown in fig. 4, the second filter 4 includes a ninth vertical microstrip 309, a seventh short microstrip 337, a sixteenth vertical microstrip 316 and a twelfth short microstrip 342, one end of the ninth vertical microstrip 309 is connected to the vertical signal receiving circuit 2, the other end of the ninth vertical microstrip 309 is connected to the seventh short microstrip 337 facing the vertical signal receiving circuit 2, one end of the sixteenth vertical microstrip 316 is connected to the second IF mixer-amplifier circuit 6, and the other end of the sixteenth vertical microstrip 316 is connected to the twelfth short microstrip 342 facing the second IF mixer-amplifier circuit 6; a plurality of third microstrip line groups and fourth microstrip line groups which are coupled and connected are distributed in an interval array between the ninth vertical microstrip line 309 and the sixteenth vertical microstrip line 316.
More specifically, the third microstrip line group includes a tenth vertical microstrip line 310, an eleventh vertical microstrip line 311, a twelfth vertical microstrip line 312, a fifth transverse microstrip line 325, a sixth transverse microstrip line 326, an eighth short microstrip line 338 and a ninth short microstrip line 339; one end of the tenth vertical microstrip line 310 is connected with one end of the twelfth vertical microstrip line 312 through a fifth transverse microstrip line 325, the inner side of the other end of the tenth vertical microstrip line 310 is connected with an eighth short microstrip line 338 deviating from the ninth vertical microstrip line 309, one end of the eleventh vertical microstrip line 311 is connected with the middle part of the fifth transverse microstrip line 325 and is positioned between the tenth vertical microstrip line 310 and the twelfth vertical microstrip line 312, the other end of the eleventh vertical microstrip line 311 is connected with a sixth transverse microstrip line 326, and the other end of the twelfth vertical microstrip line 312 is connected with a ninth short microstrip line 339 facing the eleventh vertical microstrip line 311;
the fourth microstrip line group comprises a thirteenth vertical microstrip line 313, a fourteenth vertical microstrip line 314, a fifteenth vertical microstrip line 315, a seventh transverse microstrip line 327, an eighth transverse microstrip line 328, a tenth short microstrip line 340 and an eleventh short microstrip line 341; the thirteenth vertical microstrip line 313 is vertically arranged and coupled with the twelfth vertical microstrip line 312, one end of the thirteenth vertical microstrip line 313 is connected with a tenth short microstrip line 340, the other end of the thirteenth vertical microstrip line 313 is connected with the other end of the fifteenth vertical microstrip line 315 through a seventh horizontal microstrip line 327, one end of the fifteenth vertical microstrip line 315 is connected with an eleventh short microstrip line 341, the other end of the fourteenth vertical microstrip line 314 is connected with the middle part of the seventh horizontal microstrip line 327 and is located between the thirteenth vertical microstrip line 313 and the fifteenth vertical microstrip line 315, and one end of the fourteenth vertical microstrip line 314 is connected with an eighth horizontal microstrip line 328. The second filter 4 can better filter the 5G signal in the vertical signal, and better prevent the 5G signal in the vertical signal from interfering, so that the down converter can work normally, and a user can watch the video normally.
In this embodiment, the number of the third microstrip line groups is 3, the number of the fourth microstrip line groups is 2, and the fourth microstrip line group is located between two of the third microstrip line groups. In order to achieve a more optimal effect of resisting 5G signal interference, the width of the end of the eleventh vertical microstrip line 311 connected to the fifth transverse microstrip line 325 is greater than the width of the end thereof connected to the sixth transverse microstrip line 326; the width of the end of the fourteenth vertical microstrip line 314 connected to the seventh horizontal microstrip line 327 is greater than the width of the end connected to the eighth horizontal microstrip line 328. The eleventh vertical microstrip line 311 is connected to the sixth horizontal microstrip line 326 at a position which is on the left of the middle of the eleventh vertical microstrip line 311, so that the length of the sixth horizontal microstrip line 326 on the right side of the eleventh vertical microstrip line 311 is greater than the length of the eleventh vertical microstrip line 311 on the left side of the eleventh vertical microstrip line 311; the fourteenth vertical microstrip line 314 is connected to the eighth horizontal microstrip line 328 at a position which is slightly to the left of the middle portion of the fourteenth vertical microstrip line 314, so that the length of the eighth horizontal microstrip line 328 which is located on the right side of the fourteenth vertical microstrip line 314 is greater than the length of the eighth horizontal microstrip line 328 which is located on the left side of the fourteenth vertical microstrip line 314.
The working principle of each circuit is as follows: the horizontal signal receiving circuit 1 amplifies an RF signal with the frequency of 3.7-4.2GHz for three times and outputs a signal with the frequency of 3.7-4.2GHz to the first filter 3, the horizontal signal receiving circuit 1 amplifies the signal for three times to obtain amplification gain, the first amplification includes receiving sensitivity and gain amplification, the second amplification and the third amplification strengthen the amplification of the signal, and the gain of each stage is about 12 db. The output frequency of the first filter 3 is 3.7-4.2GHz, the output frequency of the first IF mixing amplifying circuit 5 is 950-1450MHz, and the output frequency of the first IF filtering circuit 7 is 950-2050 MHz; the vertical signal receiving circuit 2 amplifies an RF signal with the frequency of 3.7-4.2GHz for three times and outputs a signal with the frequency of 3.7-4.2GHz to the second filter 4, the vertical signal receiving circuit 2 amplifies the signal for three times to obtain amplification gain, the first amplification comprises receiving sensitivity and gain amplification, the second amplification and the third amplification strengthen the amplification of the signal, and the gain of each stage is about 12 db. The output frequency of the second filter 4 is 3.7-4.2GHz, the output frequency of the second IF mixing amplifying circuit 6 is 950-1450MHz, and the output frequency of the second IF filtering circuit 8 is 950-1450MHz; the output frequency of the IF mixer circuit 11 is 950 to 1450MHz, and the output frequency of the signal output circuit 9 is 950 to 1450 MHz. The circuit down-converts the RF signal to an Intermediate Frequency (IF) signal. The first IF mixer amplifier circuit 5, the second IF mixer amplifier circuit 6, the first IF filter circuit 7, and the second IF filter circuit 8 all have gain amplification functions.
Claims (10)
1. A dual-polarization single-local-oscillator single-output frequency-reducing circuit resisting 5G signal interference comprises a horizontal signal receiving circuit (1), a vertical signal receiving circuit (2), a first filter (3), a second filter (4), a first IF mixing amplifying circuit (5), a second IF mixing amplifying circuit (6), a first IF filtering circuit (7), a second IF filtering circuit (8), a signal output circuit (9), a power supply circuit (10) for providing working voltage, an IF mixing circuit (11) and a signal switching control circuit (12), wherein signals received by the horizontal signal receiving circuit (1) sequentially pass through the first filter (3), the first IF mixing amplifying circuit (5) and the first IF filtering circuit (7) and then output horizontal IF signals to the IF mixing circuit (11), signals received by the vertical signal receiving circuit (2) sequentially pass through the second filter (4), the second IF mixing amplifying circuit (6) and the second IF filtering circuit (8) and then output vertical IF signals to the mixing amplifying circuit (11), the first IF filtering circuit (7), the second IF filtering circuit (8) and the vertical IF filtering circuit (11) and the horizontal IF filtering circuit (12) and the signals are respectively output to the vertical signal receiving circuit (11) or the vertical signal receiving circuit (7), the IF filtering circuit (12), and the IF mixing amplifying circuit (11) and the horizontal signal or the horizontal signal output to the horizontal signal switching control circuit (12), and the horizontal signal output to the IF mixing control circuit (12), and the horizontal signal, and the IF filtering circuit (11), and the horizontal signal switching control circuit (12), and the horizontal signal output to the IF filtering circuit (11), and the horizontal signal switching control circuit, and the horizontal signal, and the IF filtering circuit, and the horizontal signal output to be respectively And one of the vertical IF signals is adjusted and then output to the signal output circuit (9), characterized in that: the first filter (3) comprises a first vertical microstrip line (301), a first short microstrip line (331), an eighth vertical microstrip line (308) and a sixth short microstrip line (336), one end of the first vertical microstrip line (301) is connected with the horizontal signal receiving circuit (1), the other end of the first vertical microstrip line (301) is connected with the first short microstrip line (331) facing the horizontal signal receiving circuit (1), one end of the eighth vertical microstrip line (308) is connected with the first IF mixing and amplifying circuit (5), and the other end of the eighth vertical microstrip line (308) is connected with the sixth short microstrip line (336) facing the first IF mixing and amplifying circuit (5); a plurality of first microstrip line groups and second microstrip line groups which are connected in a coupling mode are distributed between the first vertical microstrip line (301) and the eighth vertical microstrip line (308) in an interval array mode.
2. The anti-5G signal interference dual-polarized single-local-oscillator single-output frequency reduction circuit of claim 1, characterized in that: the first microstrip line group comprises a second vertical microstrip line (302), a third vertical microstrip line (303), a fourth vertical microstrip line (304), a first transverse microstrip line (321), a second transverse microstrip line (322), a second short microstrip line (332) and a third short microstrip line (333); one end of the second vertical microstrip line (302) is connected with one end of the fourth vertical microstrip line (304) through a first transverse microstrip line (321), the inner side of the other end of the second vertical microstrip line (302) is connected with a second short microstrip line (332) deviating from the first vertical microstrip line (301), one end of the third vertical microstrip line (303) is connected with the middle part of the first transverse microstrip line (321) and is positioned between the second vertical microstrip line (302) and the fourth vertical microstrip line (304), the other end of the third vertical microstrip line (303) is connected with a second transverse microstrip line (322), and the other end of the fourth vertical microstrip line (304) is connected with a third short microstrip line (333) facing the third vertical microstrip line (303);
the second microstrip line group comprises a fifth vertical microstrip line (305), a sixth vertical microstrip line (306), a seventh vertical microstrip line (307), a third transverse microstrip line (323), a fourth transverse microstrip line (324), a fourth short microstrip line (334) and a fifth short microstrip line (335); the fifth vertical microstrip line (305) is vertically arranged and coupled with a fourth vertical microstrip line (304), one end of the fifth vertical microstrip line (305) is connected with a fourth short microstrip line (334), the other end of the fifth vertical microstrip line (305) is connected with the other end of the seventh vertical microstrip line (307) through a third transverse microstrip line (323), one end of the seventh vertical microstrip line (307) is connected with a fifth short microstrip line (335), the other end of the sixth vertical microstrip line (306) is connected with the middle part of the third transverse microstrip line (323) and is positioned between the fifth vertical microstrip line (305) and the seventh vertical microstrip line (307), and one end of the sixth vertical microstrip line (306) is connected with a fourth transverse microstrip line (324).
3. The anti-5G signal interference dual-polarized single-local-oscillator single-output frequency reduction circuit of claim 2, characterized in that: the number of the first microstrip line groups is 3, the number of the second microstrip line groups is 2, and the second microstrip line groups are located between the two first microstrip line groups.
4. The anti-5G signal interference dual-polarized single-local-oscillator single-output frequency-reduction circuit according to claim 3, characterized in that: the width of one end of the third vertical microstrip line (303) connected with the first transverse microstrip line (321) is larger than that of one end of the third vertical microstrip line connected with the second transverse microstrip line (322); the width of the end of the sixth vertical microstrip line (306) connected with the third transverse microstrip line (323) is larger than that of the end of the sixth vertical microstrip line connected with the fourth transverse microstrip line (324).
5. The anti-5G signal interference dual-polarized single-local-oscillator single-output frequency reduction circuit of claim 3, characterized in that: the third vertical microstrip line (303) is connected with the second transverse microstrip line (322) at a position which is slightly left from the middle part, so that the length of the second transverse microstrip line (322) on the right side of the third vertical microstrip line (303) is greater than the length of the third vertical microstrip line (303) on the left side of the third vertical microstrip line (303); the sixth vertical microstrip line (306) is connected with a fourth transverse microstrip line (324) at a position which is on the left of the middle of the sixth vertical microstrip line (306), so that the length of the fourth transverse microstrip line (324) on the right side of the sixth vertical microstrip line (306) is greater than the length of the fourth transverse microstrip line (324) on the left side of the sixth vertical microstrip line (306).
6. The anti-5G signal interference dual-polarized single-local-oscillator single-output frequency-reduction circuit according to any one of claims 1 to 5, characterized in that: the second filter (4) comprises a ninth vertical microstrip line (309), a seventh short microstrip line (337), a sixteenth vertical microstrip line (316) and a twelfth short microstrip line (342), one end of the ninth vertical microstrip line (309) is connected with the vertical signal receiving circuit (2), the other end of the ninth vertical microstrip line (309) is connected with the seventh short microstrip line (337) facing the vertical signal receiving circuit (2), one end of the sixteenth vertical microstrip line (316) is connected with the second IF mixing and amplifying circuit (6), and the other end of the sixteenth vertical microstrip line (316) is connected with the twelfth short microstrip line (342) facing the second IF mixing and amplifying circuit (6); a plurality of third microstrip line groups and fourth microstrip line groups which are connected in a coupling mode are distributed between the ninth vertical microstrip line (309) and the sixteenth vertical microstrip line (316) in an interval array mode.
7. The anti-5G signal interference dual-polarized single-local-oscillator single-output frequency-reduction circuit according to claim 6, characterized in that: the third microstrip line group comprises a tenth vertical microstrip line (310), an eleventh vertical microstrip line (311), a twelfth vertical microstrip line (312), a fifth transverse microstrip line (325), a sixth transverse microstrip line (326), an eighth short microstrip line (338) and a ninth short microstrip line (339); one end of the tenth vertical microstrip line (310) is connected with one end of the twelfth vertical microstrip line (312) through a fifth transverse microstrip line (325), an eighth short microstrip line (338) deviating from the ninth vertical microstrip line (309) is connected to the inner side of the other end of the tenth vertical microstrip line (310), one end of the eleventh vertical microstrip line (311) is connected with the middle part of the fifth transverse microstrip line (325) and is positioned between the tenth vertical microstrip line (310) and the twelfth vertical microstrip line (312), the other end of the eleventh vertical microstrip line (311) is connected with a sixth transverse microstrip line (326), and the other end of the twelfth vertical microstrip line (312) is connected with a ninth short microstrip line (339) facing the eleventh vertical microstrip line (311);
the fourth microstrip line group comprises a thirteenth vertical microstrip line (313), a fourteenth vertical microstrip line (314), a fifteenth vertical microstrip line (315), a seventh transverse microstrip line (327), an eighth transverse microstrip line (328), a tenth short microstrip line (340) and an eleventh short microstrip line (341); the thirteenth vertical microstrip line (313) is vertically arranged and coupled with a twelfth vertical microstrip line (312), one end of the thirteenth vertical microstrip line (313) is connected with a tenth short microstrip line (340), the other end of the thirteenth vertical microstrip line (313) is connected with the other end of the fifteenth vertical microstrip line (315) through a seventh transverse microstrip line (327), one end of the fifteenth vertical microstrip line (315) is connected with an eleventh short microstrip line (341), the other end of the fourteenth vertical microstrip line (314) is connected with the middle part of the seventh transverse microstrip line (327) and is located between the thirteenth vertical microstrip line (313) and the fifteenth vertical microstrip line (315), and one end of the fourteenth vertical microstrip line (314) is connected with an eighth transverse microstrip line (328).
8. The anti-5G signal interference dual-polarized single-local-oscillator single-output frequency reduction circuit of claim 7, wherein: the number of the third microstrip line groups is 3, the number of the fourth microstrip line groups is 2, and the fourth microstrip line group is located between the two third microstrip line groups.
9. The anti-5G signal interference dual-polarized single-local-oscillator single-output frequency reduction circuit of claim 8, wherein: the width of the end of the eleventh vertical microstrip line (311) connected with the fifth transverse microstrip line (325) is larger than that of the end of the eleventh vertical microstrip line connected with the sixth transverse microstrip line (326); the width of the end of the fourteenth vertical microstrip line (314) connected with the seventh transverse microstrip line (327) is greater than that of the end of the fourteenth vertical microstrip line connected with the eighth transverse microstrip line (328).
10. The anti-5G signal interference dual-polarized single-local-oscillator single-output frequency-reduction circuit according to claim 9, wherein: the eleventh vertical microstrip line (311) is connected with a sixth transverse microstrip line (326) at a position which is on the left of the middle part of the eleventh vertical microstrip line (311), so that the length of the sixth transverse microstrip line (326) on the right side of the eleventh vertical microstrip line (311) is greater than the length of the eleventh vertical microstrip line (311) on the left side of the eleventh vertical microstrip line (311); the fourteenth vertical microstrip line (314) is connected with the eighth transverse microstrip line (328) at a position which is on the left of the middle part of the eighth vertical microstrip line (314), so that the length of the eighth transverse microstrip line (328) on the right side of the fourteenth vertical microstrip line (314) is greater than the length of the eighth transverse microstrip line (328) on the left side of the fourteenth vertical microstrip line (314).
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| CN202221657670.7U CN218301453U (en) | 2022-06-28 | 2022-06-28 | Anti 5G signal interference's single output frequency reduction circuit of double polarization single local oscillator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221657670.7U CN218301453U (en) | 2022-06-28 | 2022-06-28 | Anti 5G signal interference's single output frequency reduction circuit of double polarization single local oscillator |
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| CN218301453U true CN218301453U (en) | 2023-01-13 |
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