CN218243351U

CN218243351U - DC conversion circuit

Info

Publication number: CN218243351U
Application number: CN202222008671.5U
Authority: CN
Inventors: 孙明珠; 尹雪芹; 曹虎; 尹小强
Original assignee: BYD Co Ltd
Current assignee: BYD Co Ltd
Priority date: 2022-07-29
Filing date: 2022-07-29
Publication date: 2023-01-06
Anticipated expiration: 2032-07-29

Abstract

A kind of direct current conversion circuit, the first end of the first capacitor connects the first end of the first switch tube and first end of the third capacitor, the second end of the first switch tube connects the first end of the second capacitor and first end of the second switch tube, the second end of the second capacitor connects the first end of the first inductance, the second end of the first inductance connects the first end of the first coil of the transformer, the second end of the first coil connects the second end of the third capacitor and first end of the fourth capacitor, the second end of the fourth capacitor connects the second end of the second switch tube and second end of the first capacitor; the first end of the seventh capacitor is connected with the first end of the third switching tube and the first end of the fifth capacitor, the second end of the fifth capacitor is connected with the first end of the second coil of the transformer and the first end of the sixth capacitor, the second end of the second coil is connected with the second end of the third switching tube and the first end of the fourth switching tube, and the second end of the fourth switching tube is connected with the second end of the sixth capacitor and the second end of the seventh capacitor. The voltage stress of the switching tube can be reduced.

Description

DC conversion circuit

Technical Field

The application relates to the technical field of electronic circuits, in particular to a direct current conversion circuit.

Background

In a Direct current (DC-DC) conversion circuit such as a DC-DC (Direct current-Direct current) circuit, a phase-shifted full-bridge DC-DC circuit is generally adopted, and a control method thereof is single phase-shifted control. During single phase-shift control, if the device works in high-voltage and high-current occasions, the phase-shift inductor and the low-voltage side switching tube have higher voltage stress during working.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a direct current conversion circuit, which can reduce the voltage stress of a switch tube.

A first aspect of the embodiments of the present application provides a dc conversion circuit, including a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a first inductor, and a transformer;

a first end of the first capacitor is connected with a first end of the first switch tube and a first end of the third capacitor, a second end of the first switch tube is connected with a first end of the second capacitor and a first end of the second switch tube, a second end of the second capacitor is connected with a first end of the first inductor, a second end of the first inductor is connected with a first end of a first coil of the transformer, a second end of the first coil is connected with a second end of the third capacitor and a first end of a fourth capacitor, and a second end of the fourth capacitor is connected with a second end of the second switch tube and a second end of the first capacitor;

the first end of the seventh capacitor is connected with the first end of the third switching tube and the first end of the fifth capacitor, the second end of the fifth capacitor is connected with the first end of the second coil of the transformer and the first end of the sixth capacitor, the second end of the second coil is connected with the second end of the third switching tube and the first end of the fourth switching tube, and the second end of the fourth switching tube is connected with the second end of the sixth capacitor and the second end of the seventh capacitor.

A second aspect of the embodiments of the present application provides a dc conversion circuit, including a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a first inductor, and a transformer;

a first end of the first capacitor is connected to a first end of the first switching tube and a first end of the third capacitor, a second end of the first switching tube is connected to a first end of the second switching tube and a first end of a first coil of the transformer, a second end of the first coil is connected to a first end of the first inductor, a second end of the first inductor is connected to a first end of the second capacitor, a second end of the second capacitor is connected to a second end of the third capacitor and a first end of the fourth capacitor, and a second end of the fourth capacitor is connected to a second end of the second switching tube and a second end of the first capacitor;

the first end of the seventh capacitor is connected with the first end of the third switch tube and the first end of the fifth capacitor, the second end of the fifth capacitor is connected with the first end of the second coil of the transformer and the first end of the sixth capacitor, the second end of the second coil is connected with the second end of the third switch tube and the first end of the fourth switch tube, and the second end of the fourth switch tube is connected with the second end of the sixth capacitor and the second end of the seventh capacitor.

A third aspect of the embodiments of the present application provides a dc conversion circuit, including a first capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, and a transformer;

a first end of the first capacitor is connected with a first end of the first switch tube and a first end of the third capacitor, a second end of the first switch tube is connected with a first end of the second switch tube and a first end of a first coil of the transformer, a second end of the first coil is connected with a second end of the third capacitor and a first end of the fourth capacitor, and a second end of the fourth capacitor is connected with a second end of the second switch tube and a second end of the first capacitor;

A fourth aspect of the embodiments of the present application provides a dc conversion circuit, including a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, and a transformer;

a first end of the first capacitor is connected to a first end of the first switch tube and a first end of the third capacitor, a second end of the first switch tube is connected to a first end of the second capacitor and a first end of the second switch tube, a second end of the second capacitor is connected to a first end of a first coil of the transformer, a second end of the first coil is connected to a second end of the third capacitor and a first end of the fourth capacitor, and a second end of the fourth capacitor is connected to a second end of the second switch tube and a second end of the first capacitor;

A fifth aspect of the embodiment of the present application provides a dc conversion circuit, including a first capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first inductor, and a transformer;

a first end of the first capacitor is connected with a first end of the first switch tube and a first end of the third capacitor, a second end of the first switch tube is connected with a first end of the second switch tube and a first end of the first inductor, a second end of the first inductor is connected with a first end of a first coil of the transformer, a second end of the first coil is connected with a second end of the third capacitor and a first end of the fourth capacitor, and a second end of the fourth capacitor is connected with a second end of the second switch tube and a second end of the first capacitor;

Optionally, a capacitance value of the third capacitor is the same as a capacitance value of the fourth capacitor, and a capacitance value of the fifth capacitor is the same as a capacitance value of the sixth capacitor.

Optionally, the third capacitor includes N sub-capacitors connected in series, the fourth capacitor includes M sub-capacitors connected in series, N is an integer greater than or equal to 2, and M is an integer greater than or equal to 2; the fifth capacitor comprises P sub-capacitors connected in series, the sixth capacitor comprises Q sub-capacitors connected in series, P is an integer greater than or equal to 2, and Q is an integer greater than or equal to 2.

Optionally, capacitance values of any two sub-capacitors of the N series-connected sub-capacitors are the same, and capacitance values of any two sub-capacitors of the M series-connected sub-capacitors are the same; any two sub-capacitors in the P series sub-capacitors have the same capacitance value, and any two sub-capacitors in the Q series sub-capacitors have the same capacitance value. Optionally, the dc-to-dc conversion circuit further includes a second inductor, and a first end of the second inductor is connected to a first end of the seventh capacitor.

Optionally, a first dc voltage is applied between the first end of the first capacitor and the second end of the first capacitor, a second dc voltage is applied between the first end of the seventh capacitor and the second end of the seventh capacitor, and a voltage value of the first dc voltage is different from a voltage value of the second dc voltage.

Optionally, the control end of the first switching tube loads a first pulse width modulation PWM signal, the control end of the second switching tube loads a second PWM signal, the control end of the third switching tube loads a third PWM signal, and the control end of the fourth switching tube loads a fourth PWM signal.

Optionally, in a case that the voltage value of the first dc voltage is greater than the voltage value of the second dc voltage, the waveform phase angle of the third PWM signal lags behind the waveform phase angle of the first PWM signal, and the waveform phase angle of the fourth PWM signal lags behind the waveform phase angle of the second PWM signal; energy of the dc conversion circuit is transferred from the first coil side to the second coil side.

Optionally, when the first switching tube is turned on and the second switching tube is turned off, an absolute value of a voltage between the first end of the first inductor and the second end of the first coil is half of the first direct-current voltage;

during a time period after the first switch tube is turned off and before the second switch tube is turned on, a voltage between the first end of the first inductor and the second end of the first coil is zero;

under the condition that the second switch tube is conducted and the first switch tube is turned off, the absolute value of the voltage between the first end of the first inductor and the second end of the first coil is half of the first direct-current voltage;

in a time period after the second switch tube is turned off and before the first switch tube is turned on, a voltage between the first end of the first inductor and the second end of the first coil is zero.

Optionally, in a case where the voltage value of the second dc voltage is greater than the voltage value of the first dc voltage, the waveform phase angle of the first PWM signal lags behind the waveform phase angle of the third PWM signal, and the waveform phase angle of the second PWM signal lags behind the waveform phase angle of the fourth PWM signal; energy of the direct current conversion circuit is transferred from the second coil side to the first coil side.

Optionally, when the third switching tube is turned on and the fourth switching tube is turned off, an absolute value of a voltage between the first end of the second coil and the second end of the second coil is half of the second direct-current voltage;

in a time period after the third switching tube is turned off and before the fourth switching tube is turned on, a voltage between the first end of the second coil and the second end of the second coil is zero;

under the condition that the fourth switching tube is turned on and the third switching tube is turned off, the absolute value of the voltage between the first end of the second coil and the second end of the second coil is half of the second direct-current voltage;

in a time period after the fourth switching tube is turned off and before the third switching tube is turned on, a voltage between the first end of the second coil and the second end of the second coil is zero.

Optionally, the duty ratio of the first PWM signal and the duty ratio of the second PWM signal are both 50%, and the first PWM signal and the second PWM signal are complementary;

the duty cycle of the third PWM signal and the duty cycle of the fourth PWM signal are both 50%, and the third PWM signal is complementary to the fourth PWM signal.

The direct current conversion circuit comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first inductor and a transformer; the first end of the first capacitor is connected with the first end of the first switch tube and the first end of the third capacitor, the second end of the first switch tube is connected with the first end of the second capacitor and the first end of the second switch tube, the second end of the second capacitor is connected with the first end of the first inductor, the second end of the first inductor is connected with the first end of the first coil of the transformer, the second end of the first coil is connected with the second end of the third capacitor and the first end of the fourth capacitor, and the second end of the fourth capacitor is connected with the second end of the second switch tube and the second end of the first capacitor; the first end of the seventh capacitor is connected with the first end of the third switching tube and the first end of the fifth capacitor, the second end of the fifth capacitor is connected with the first end of the second coil of the transformer and the first end of the sixth capacitor, the second end of the second coil is connected with the second end of the third switching tube and the first end of the fourth switching tube, and the second end of the fourth switching tube is connected with the second end of the sixth capacitor and the second end of the seventh capacitor. Compared with the phase-shifted full-bridge DC-DC circuit, the DC conversion circuit has the advantages that the original switch tube of the phase-shifted full-bridge DC-DC circuit is replaced by the third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor, and when the DC conversion circuit works, if any one of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube is turned off, the DC conversion circuit can be divided by one of the third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor, so that the voltage stress borne by the switch tube is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a dc conversion circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application;

fig. 3 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application;

fig. 4 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application;

fig. 5 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application;

fig. 6 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application;

fig. 7 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application;

fig. 8 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application;

fig. 9 is a schematic structural diagram of another dc conversion circuit according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description and claims of the present application and in the foregoing drawings are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, system, article, or apparatus.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a dc conversion circuit according to an embodiment of the present disclosure. As shown in fig. 1, the dc conversion circuit 100 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a first inductor L1, and a transformer T;

a first end of the first capacitor C1 is connected to a first end of the first switch tube Q1 and a first end of the third capacitor C3, a second end of the first switch tube Q1 is connected to a first end of the second capacitor C2 and a first end of the second switch tube Q2, a second end of the second capacitor C2 is connected to a first end of the first inductor L1, a second end of the first inductor L1 is connected to a first end of a first coil A1 of the transformer T, a second end of the first coil A1 is connected to a second end of the third capacitor C3 and a first end of the fourth capacitor C4, and a second end of the fourth capacitor C4 is connected to a second end of the second switch tube Q2 and a second end of the first capacitor C1;

a first end of the seventh capacitor C7 is connected to the first end of the third switch Q3 and the first end of the fifth capacitor C5, a second end of the fifth capacitor C5 is connected to the first end of the second coil A2 of the transformer T and the first end of the sixth capacitor C6, a second end of the second coil A2 is connected to the second end of the third switch Q3 and the first end of the fourth switch Q4, and a second end of the fourth switch Q4 is connected to the second end of the sixth capacitor C6 and the second end of the seventh capacitor C7.

The DC conversion circuit 100 may be a Direct current-Direct current (DC-DC) circuit, and may implement conversion between DC voltages. When the voltage across the first capacitor C1 is the input voltage of the dc conversion circuit 100, the first capacitor C1 is the input capacitor, and the seventh capacitor C7 is the output capacitor. When the voltage across the seventh capacitor C7 is the input voltage of the dc conversion circuit 100, the seventh capacitor C7 is the input capacitor, and the first capacitor C1 is the output capacitor.

The second capacitor C2 is a blocking capacitor, which prevents the transformer T from biasing during operation of the dc conversion circuit 100, and further biases the dc bus voltage to a certain side, resulting in the Q1 or Q2 being damaged due to too high voltage.

The first inductor L1 is a phase-shifting inductor, and T is a transformer, which transmits system energy during the operation of the dc conversion circuit 100.

When the voltage across the first capacitor C1 is used as the input voltage of the dc conversion circuit 100, the first capacitor C1 is a supporting capacitor of the dc bus, so that the input voltage of the dc conversion circuit 100 can be prevented from sudden change.

When the voltage at the two ends of the first capacitor C1 is greater than the voltage at the two ends of the seventh capacitor C7, the first switch tube Q1 and the second switch tube Q2 are high-voltage side switch tubes, and Q1 and Q2 form a high-voltage side leading bridge arm. The third capacitor C3 and the fourth capacitor C4 are high-voltage-side support capacitors, and provide support current when the dc conversion circuit 100 operates. The fifth capacitor C5 and the sixth capacitor C6 are low-voltage-side support capacitors, and provide support current when the dc conversion circuit 100 operates. The third switching tube Q3 and the fourth switching tube Q4 are low-voltage side switching tubes, and Q3 and Q4 form a low-voltage side hysteresis bridge arm.

The switching tube in the embodiment of the present application may be a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), which is referred to as an MOS tube for short. The MOS tube can comprise an NMOS tube or a PMOS tube. The first end of the MOS tube can be a source electrode or a drain electrode of the MOS tube, and the second end of the MOS tube can be a drain electrode or a source electrode of the MOS tube. The control end of the MOS tube can be the grid electrode of the MOS tube.

When the voltage across the first capacitor C1 is greater than the voltage across the seventh capacitor C7, the first coil may be a primary coil of the transformer T and the second coil may be a secondary coil of the transformer T.

When the voltage across the first capacitor C1 is less than the voltage across the seventh capacitor C7, the first coil may be a secondary coil of the transformer T and the second coil may be a primary coil of the transformer T.

Referring to fig. 2, fig. 2 is a schematic structural diagram of another dc conversion circuit according to an embodiment of the present disclosure. The direct current conversion circuit is a phase-shifted full-bridge DC-DC circuit.

Compared with the phase-shifted full-bridge DC-DC circuit in fig. 2, the direct-current conversion circuit in fig. 1 replaces the original switching tubes (Q5, Q6, Q7, Q8) of the phase-shifted full-bridge DC-DC circuit with the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor, and when the direct-current conversion circuit works, if any one of the first switching tube, the second switching tube, the third switching tube, and the fourth switching tube is turned off, the direct-current conversion circuit divides voltage with one of the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor, so that voltage stress borne by the switching tube is reduced.

Optionally, a first dc voltage is applied between the first end of the first capacitor C1 and the second end of the first capacitor C1, a second dc voltage is applied between the first end of the seventh capacitor C7 and the second end of the seventh capacitor C7, and a voltage value of the first dc voltage is different from a voltage value of the second dc voltage.

In the embodiment of the present application, when the voltage across the first capacitor C1 is the input voltage of the dc conversion circuit 100, the first dc voltage is the input voltage of the dc conversion circuit 100, and the second dc voltage is the output voltage of the dc conversion circuit 100 (as shown in Uo in fig. 1).

When the voltage across the seventh capacitor C7 is the input voltage of the dc conversion circuit 100, the first dc voltage is the output voltage of the dc conversion circuit 100, and the second dc voltage is the input voltage of the dc conversion circuit 100.

Optionally, the control end of the first switching tube Q1 loads a first pulse width modulation PWM signal, the control end of the second switching tube Q2 loads a second PWM signal, the control end of the third switching tube Q3 loads a third PWM signal, and the control end of the fourth switching tube Q4 loads a fourth PWM signal.

In the embodiment of the present application, the first switching tube Q1, the second switching tube Q2, the third switching tube Q3, and the fourth switching tube Q4 can be controlled to be turned on or turned off by a Pulse Width Modulation (PWM) signal.

Optionally, in a case that the voltage value of the first dc voltage is greater than the voltage value of the second dc voltage, the waveform phase angle of the third PWM signal lags behind the waveform phase angle of the first PWM signal, and the waveform phase angle of the fourth PWM signal lags behind the waveform phase angle of the second PWM signal; the energy of the dc conversion circuit is transferred from the first coil A1 side to the second coil A2 side.

In the embodiment of the present application, the first dc voltage is a high-side voltage, and the second dc voltage is a low-side voltage. As shown in FIG. 1, HDC + is the positive pole of the first DC voltage, and HDC-is the negative pole of the first DC voltage. LDC + is the positive pole of the second direct current voltage, and LDC-is the negative pole of the second direct current voltage.

Optionally, when the first switching tube Q1 is turned on and the second switching tube Q2 is turned off, an absolute value of a voltage between the first end of the first inductor L1 and the second end of the first coil A1 is half of the first direct current voltage;

in a time period after the first switching tube Q1 is turned off and before the second switching tube Q2 is turned on, a voltage between the first end of the first inductor L1 and the second end of the first coil A1 is zero;

when the second switching tube Q2 is turned on and the first switching tube Q1 is turned off, an absolute value of a voltage between the first end of the first inductor L1 and the second end of the first coil A1 is half of the first direct current voltage;

in a time period after the second switching tube Q2 is turned off and before the first switching tube Q1 is turned on, a voltage between the first end of the first inductor L1 and the second end of the first coil A1 is zero.

In the embodiment of the present application, the energy of the dc conversion circuit 100 is transferred from the first coil A1 side to the second coil A2 side.

When the dc conversion circuit 100 works, if the first switching transistor Q1 and the second switching transistor Q2 are complementarily turned on at a duty ratio of 50%, and the third switching transistor Q3 and the fourth switching transistor Q4 are complementarily turned on at a duty ratio of 50%, the control of the output voltage is realized by shifting the phase angles of Q3 and Q4 with respect to Q1. Assuming that at the beginning, Q1 is turned on first, Q2 is turned on later, Q3 and Q4 are used as phase-shifting switching devices, and energy is analyzed from a high-voltage side (a first capacitor C1 side) to a low-voltage side (a seventh capacitor C7 side), the specific working flow is as follows:

1. at the moment when the Q1 is conducted, the high-voltage side current passes through the Q1, the C2, the L1, the T and the C4 and returns to the negative pole, at the moment, the capacitor C2 is charged, the C1 is discharged, the voltage Uab (shown in figure 1, namely, the voltage between the first end of the first inductor L1 and the second end of the first coil A1) at the two ends of the transformer T is half of the first direct-current voltage, and when the waveform phase angle of the PWM signals of the Q3 and the Q4 lags behind the Q1, the energy is transmitted from the high-voltage side to the low-voltage side;

2. in the time period after Q1 is turned off and before Q2 is turned on, current flows through body diodes of C2, L1, T, C4 and Q2, voltage Uab (shown in figure 1, namely, the voltage between the first end of the first inductor L1 and the second end of the first coil A1) at two ends of the transformer T is 0, and when the waveform phase angle of PWM signals of Q3 and Q4 lags behind Q1, energy continues to be transmitted from the high-voltage side to the low-voltage side;

3. after Q2 is switched on and Q1 is switched off, the current on the high-voltage side passes through C3, T, L1, C2 and Q2 and returns to the negative pole, at the moment, the capacitor C1 is charged, the C2 is discharged, the voltage Uab (shown in figure 1, namely, the voltage between the first end of the first inductor L1 and the second end of the first coil A1) at the two ends of the transformer T is half of the first direct-current voltage, and when the waveform phase angle of the PWM signals of Q3 and Q4 lags behind Q1, the energy is transmitted from the high-voltage side to the low-voltage side;

4. in the time period after Q2 is turned off and before Q1 is turned on, current freewheels through body diodes of T, L1, C2 and Q1, voltage Uab (shown in figure 1, namely voltage between the first end of the first inductor L1 and the second end of the first coil A1) at two ends of the transformer is 0, and when the waveform phase angle of PWM signals of Q3 and Q4 lags behind Q1, energy continues to be transmitted from the high-voltage side to the low-voltage side.

Through the four steps, one cycle of work is completed, and energy is transmitted from a high-voltage side to a low-voltage side.

During operation, due to the existence of the third capacitor C3 and the fourth capacitor C4, if the capacitance values of the third capacitor C3 and the fourth capacitor C4 are the same, the capacitor C3 and the capacitor C4 respectively divide half of the voltage of the dc bus. The voltage at the two ends of Uab is half of the dc bus voltage (first dc voltage), and Q1 and Q2 bear half of the dc bus voltage in one cycle, so the voltage stress on the high-voltage side is half of the full-bridge topology, the voltage stress decreases by half, the current stress also decreases by half of the full-bridge with the decrease of the voltage stress, and similarly Q3 and Q4 on the low-voltage side are the same. Specifically, when Q1 is turned on and Q2 is turned off, the voltages across Uab and C4 are equal to the dc bus voltage, so Uab is half of the dc bus voltage. When Q1 is turned off and Q2 is turned on, the voltage across Uab and C3 is equal to the voltage of the DC bus, so that Uab is half of the voltage of the DC bus. When Q1 is turned off and Q2 is turned off, the voltage across Uab is 0, the voltage across Q1 is equal to the voltage across C3, which is half the voltage of the dc bus, and the voltage across Q2 is equal to the voltage across C4, which is half the voltage of the dc bus.

Based on the above characteristics, the topology of the dc conversion circuit 100 can be used in the case where the dc bus voltage is 1200V or more and the current is large, and the topology is simple in control method, low in cost and easy to implement.

Optionally, in a case where the voltage value of the second dc voltage is greater than the voltage value of the first dc voltage, the waveform phase angle of the first PWM signal lags behind the waveform phase angle of the third PWM signal, and the waveform phase angle of the second PWM signal lags behind the waveform phase angle of the fourth PWM signal; the energy of the dc conversion circuit is transferred from the second coil A2 side to the first coil A1 side.

Optionally, when the third switching tube Q3 is turned on and the fourth switching tube Q4 is turned off, an absolute value of a voltage between the first end of the second coil A2 and the second end of the second coil A2 is half of the second direct-current voltage;

in a period after the third switching tube Q3 is turned off and before the fourth switching tube Q4 is turned on, a voltage between the first end of the second coil A2 and the second end of the second coil A2 is zero;

when the fourth switching tube Q4 is turned on and the third switching tube Q3 is turned off, an absolute value of a voltage between the first end of the second coil A2 and the second end of the second coil A2 is half of the second direct-current voltage;

in a time period after the fourth switching tube Q4 is turned off and before the third switching tube Q3 is turned on, a voltage between the first end of the second coil A2 and the second end of the second coil A2 is zero.

In the embodiment of the present application, the energy of the dc conversion circuit 100 is transferred from the second coil A2 side to the first coil A1 side.

When the direct current conversion circuit 100 works, if the first switching tube Q1 and the second switching tube Q2 are complementarily turned on at a duty ratio of 50%, and the third switching tube Q3 and the fourth switching tube Q4 are complementarily turned on at a duty ratio of 50%, the control of the output voltage is realized by shifting the phase angles of Q1 and Q2 relative to Q3. Assuming that at the beginning, Q3 is turned on first, Q4 is turned on later, Q1 and Q2 are used as phase-shifting switching devices, and energy is analyzed from a high-voltage side (a seventh capacitor C7 side) to a low-voltage side (a first capacitor C1 side), the specific working flow is as follows:

1. at the moment that Q3 is conducted, the high-voltage side current passes through Q3, T and C6 and returns to the negative pole, at this moment, C7 discharges, the voltage Ucd (shown in figure 1, namely, the voltage between the first end of the second coil A2 and the second end of the second coil A2) at two ends of the transformer T is half of the second direct-current voltage, and when the waveform phase angle of the PWM signals of Q1 and Q2 lags behind Q3, the energy is transmitted from the high-voltage side to the low-voltage side;

2. in the time period after Q3 is turned off and before Q4 is turned on, current flows through body diodes of T, C6 and Q4, the voltage Ucd (shown in figure 1, namely the voltage between the first end of the second coil A2 and the second end of the second coil A2) at two ends of the transformer T is 0, and when the waveform phase angle of PWM signals of Q1 and Q2 lags behind Q3, energy continues to be transmitted from the high-voltage side to the low-voltage side;

3. after Q4 is switched on and Q3 is switched off, the high-voltage side current passes through C5, T and Q4 and returns to the negative pole, at the moment, the capacitor C7 is charged, the voltage Ucd (shown in figure 1, namely, the voltage between the first end of the second coil A2 and the second end of the second coil A2) at the two ends of the transformer T is half of the second direct-current voltage, and when the waveform phase angle of the PWM signals of Q1 and Q2 lags behind Q3, the energy is transmitted from the high-voltage side to the low-voltage side;

4. in the time period after Q2 is turned off and before Q1 is turned on, current flows through body diodes of T, C5 and Q3, voltage Ucd (shown in figure 1, namely, the voltage between the first end of the second coil A2 and the second end of the second coil A2) at two ends of the transformer is 0, and when the waveform phase angle of PWM signals of Q1 and Q2 lags behind Q3, energy continues to be transmitted from the high-voltage side to the low-voltage side.

In operation, due to the existence of the fifth capacitor C5 and the sixth capacitor C6, the voltage at the two ends of the Ucd is half of the dc bus voltage (second dc voltage), and Q3 and Q4 respectively bear half of the dc bus voltage in one cycle, so the voltage stress at the high-voltage side is half of the full-bridge topology, the voltage stress is reduced by half, the current stress is reduced to half of the full-bridge along with the reduction of the voltage stress, and similarly, Q1 and Q2 at the low-voltage side are the same.

Optionally, the capacitance values of the third capacitor C3 and the fourth capacitor C4 are equal, and the capacitance values of the fifth capacitor C5 and the sixth capacitor C6 are equal.

In this embodiment, the capacitance values of the third capacitor C3 and the fourth capacitor C4 are equal to each other, and the third capacitor C3 and the fourth capacitor C4 can bear half of the dc bus voltage respectively, so that Q1 and Q2 bear half of the dc bus voltage respectively in one period, thereby reducing the voltage stress of Q1 and Q2.

The capacitance values of the fifth capacitor C5 and the sixth capacitor C6 are equal, and the fifth capacitor C5 and the sixth capacitor C6 can bear half of the voltage of the direct-current bus respectively, so that the Q3 and the Q4 bear half of the voltage of the direct-current bus respectively in one period, and the voltage stress of the Q3 and the Q4 is reduced.

Optionally, referring to fig. 3, fig. 3 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application. Fig. 3 is further optimized based on fig. 1, and as shown in fig. 3, the third capacitor C3 includes N series-connected sub-capacitors (C31, C32, \ 8230; C3N), the fourth capacitor C4 includes M series-connected sub-capacitors (C41, C42, \8230; C4M), the fifth capacitor C5 includes P series-connected sub-capacitors (C51, C52, \8230; C5P), and the sixth capacitor C6 includes Q series-connected sub-capacitors (C61, C62, \8230; C6Q).

Each capacitor is formed by connecting a plurality of sub-capacitors in series, voltage stress on each sub-capacitor can be further reduced, and the capacitor with smaller voltage resistance can be adopted in a high-voltage scene (for example, in a power utilization scene of more than 1000V), so that the cost is saved.

Optionally, capacitance values of any two sub-capacitors of the N series-connected sub-capacitors are the same, and capacitance values of any two sub-capacitors of the M series-connected sub-capacitors are the same; any two sub-capacitors in the P series sub-capacitors have the same capacitance value, and any two sub-capacitors in the Q series sub-capacitors have the same capacitance value.

Each sub capacitor is the same in size, so that the voltage division of each sub capacitor is the same, the voltage of a certain sub capacitor is not too large or too small, the sub capacitors with smaller voltage resistance can be adopted in a high-voltage scene, and the cost is saved.

Optionally, referring to fig. 4, fig. 4 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application. As shown in fig. 4, the dc conversion circuit 100 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a first inductor L1, and a transformer T;

a first end of the first capacitor C1 is connected to a first end of the first switch tube Q1 and a first end of the third capacitor C3, a second end of the first switch tube Q1 is connected to a first end of the second switch tube Q2 and a first end of a first coil A1 of the transformer T, a second end of the first coil A1 is connected to a first end of the first inductor L1, a second end of the first inductor L1 is connected to a first end of the second capacitor C2, a second end of the second capacitor C2 is connected to a second end of the third capacitor C3 and a first end of the fourth capacitor C4, and a second end of the fourth capacitor C4 is connected to a second end of the second switch tube Q2 and a second end of the first capacitor C1;

the first end of the seventh capacitor C7 is connected to the first end of the third switch tube Q3 and the first end of the fifth capacitor C5, the second end of the fifth capacitor C5 is connected to the first end of the second coil A2 of the transformer T and the first end of the sixth capacitor C6, the second end of the second coil A2 is connected to the second end of the third switch tube Q3 and the first end of the fourth switch tube Q4, and the second end of the fourth switch tube Q4 is connected to the second end of the sixth capacitor C6 and the second end of the seventh capacitor C7.

Fig. 4 is similar to the circuit structure of fig. 1, and the circuit principle thereof refers to the description related to fig. 1, which is not repeated herein.

Optionally, referring to fig. 5, fig. 5 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application. As shown in fig. 5, the dc conversion circuit 100 reduces the first inductance and the second capacitance based on fig. 1.

Optionally, referring to fig. 6, fig. 6 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application. As shown in fig. 6, the dc-dc converter circuit 100 reduces the first inductance based on fig. 1.

Optionally, referring to fig. 7, fig. 7 is a schematic structural diagram of another dc conversion circuit provided in the embodiment of the present application. As shown in fig. 7, the dc conversion circuit 100 is based on fig. 1 and has a reduced second capacitance.

Optionally, referring to fig. 8 and fig. 9, fig. 8 is a schematic structural diagram of another dc conversion circuit provided in this embodiment of the present application. Fig. 8 is further obtained on the basis of fig. 1. As shown in fig. 8, the dc conversion circuit 100 further includes a second inductor L2, and a first end of the second inductor L2 is connected to a first end of the seventh capacitor C7. Fig. 9 is further obtained on the basis of fig. 4. As shown in fig. 9, the dc conversion circuit 100 further includes a second inductor L2, and a first end of the second inductor L2 is connected to a first end of the seventh capacitor C7.

The second inductor L2 is an output filter inductor, and filters out high-frequency ripples output by the dc-dc converter circuit 100 during operation.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and may be implemented in other ways, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the core concepts of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A direct current conversion circuit is characterized by comprising a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first inductor and a transformer;

a first end of the first capacitor is connected to a first end of the first switch tube and a first end of the third capacitor, a second end of the first switch tube is connected to a first end of the second capacitor and a first end of the second switch tube, a second end of the second capacitor is connected to a first end of the first inductor, a second end of the first inductor is connected to a first end of a first coil of the transformer, a second end of the first coil is connected to a second end of the third capacitor and a first end of the fourth capacitor, and a second end of the fourth capacitor is connected to a second end of the second switch tube and a second end of the first capacitor;

2. A direct current conversion circuit is characterized by comprising a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a first inductor and a transformer;

a first end of the first capacitor is connected with a first end of the first switch tube and a first end of the third capacitor, a second end of the first switch tube is connected with a first end of the second switch tube and a first end of a first coil of the transformer, a second end of the first coil is connected with a first end of the first inductor, a second end of the first inductor is connected with a first end of the second capacitor, a second end of the second capacitor is connected with a second end of the third capacitor and a first end of the fourth capacitor, and a second end of the fourth capacitor is connected with a second end of the second switch tube and a second end of the first capacitor;

3. A direct current conversion circuit is characterized by comprising a first capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a transformer;

the first end of the first capacitor is connected with the first end of the first switch tube and the first end of the third capacitor, the second end of the first switch tube is connected with the first end of the second switch tube and the first end of the first coil of the transformer, the second end of the first coil is connected with the second end of the third capacitor and the first end of the fourth capacitor, and the second end of the fourth capacitor is connected with the second end of the second switch tube and the second end of the first capacitor;

4. A direct current conversion circuit is characterized by comprising a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a transformer;

a first end of the first capacitor is connected with a first end of the first switch tube and a first end of the third capacitor, a second end of the first switch tube is connected with a first end of the second capacitor and a first end of the second switch tube, a second end of the second capacitor is connected with a first end of a first coil of the transformer, a second end of the first coil is connected with a second end of the third capacitor and a first end of a fourth capacitor, and a second end of the fourth capacitor is connected with a second end of the second switch tube and a second end of the first capacitor;

5. A direct current conversion circuit is characterized by comprising a first capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first inductor and a transformer;

a first end of the first capacitor is connected to a first end of the first switching tube and a first end of the third capacitor, a second end of the first switching tube is connected to a first end of the second switching tube and a first end of the first inductor, a second end of the first inductor is connected to a first end of a first coil of the transformer, a second end of the first coil is connected to a second end of the third capacitor and a first end of the fourth capacitor, and a second end of the fourth capacitor is connected to a second end of the second switching tube and a second end of the first capacitor;

6. The dc conversion circuit according to any one of claims 1 to 5, wherein a capacitance value of the third capacitor is the same as a capacitance value of the fourth capacitor, and a capacitance value of the fifth capacitor is the same as a capacitance value of the sixth capacitor.

7. The DC conversion circuit according to claim 6, wherein the third capacitor comprises N sub-capacitors connected in series, the fourth capacitor comprises M sub-capacitors connected in series, N is an integer greater than or equal to 2, and M is an integer greater than or equal to 2; the fifth capacitor comprises P sub-capacitors connected in series, the sixth capacitor comprises Q sub-capacitors connected in series, P is an integer greater than or equal to 2, and Q is an integer greater than or equal to 2.

8. The dc conversion circuit according to claim 7, wherein any two of the N series-connected sub-capacitors have the same capacitance value, and any two of the M series-connected sub-capacitors have the same capacitance value; any two sub-capacitors in the P series sub-capacitors have the same capacitance value, and any two sub-capacitors in the Q series sub-capacitors have the same capacitance value.

9. The dc conversion circuit according to any one of claims 1 to 5, further comprising a second inductor, wherein a first end of the second inductor is connected to a first end of the seventh capacitor.

10. The dc conversion circuit according to any one of claims 1 to 5, wherein a first dc voltage is applied between the first terminal of the first capacitor and the second terminal of the first capacitor, a second dc voltage is applied between the first terminal of the seventh capacitor and the second terminal of the seventh capacitor, and a voltage value of the first dc voltage is different from a voltage value of the second dc voltage.

11. The dc conversion circuit of claim 10, wherein a control terminal of the first switching tube is loaded with a first PWM signal, a control terminal of the second switching tube is loaded with a second PWM signal, a control terminal of the third switching tube is loaded with a third PWM signal, and a control terminal of the fourth switching tube is loaded with a fourth PWM signal.