CN218241815U

CN218241815U - High heat dissipation fan-out packaging structure based on metal substrate

Info

Publication number: CN218241815U
Application number: CN202222221432.8U
Authority: CN
Inventors: 张鹏; 耿雪琪; 王成迁
Original assignee: Wuxi Zhongwei High Tech Electronic Co ltd
Current assignee: Wuxi Zhongwei High Tech Electronic Co ltd
Priority date: 2022-08-23
Filing date: 2022-08-23
Publication date: 2023-01-06
Anticipated expiration: 2032-08-23

Abstract

The utility model relates to an integrated circuit encapsulates technical field, in particular to high heat dissipation fan-out packaging structure based on metal substrate. The radiating structure comprises a first radiating substrate, wherein a through conductive through hole is formed in the first radiating substrate, a chip cavity is formed in the lower surface of the first radiating substrate, a chip is arranged in the chip cavity, a second radiating substrate is arranged below the first radiating substrate, a first wiring layer is arranged on the upper surface of the first radiating substrate, a second wiring layer is arranged on the lower surface of the first radiating substrate, the first wiring layer is electrically connected with the second wiring layer through the conductive through hole, the chip is connected with the second wiring layer, and an antenna is arranged on the first wiring layer. The utility model discloses a heat dissipation basement for whole packaging structure possesses excellent heat dispersion. The chip is embedded in the metal substrate and is interconnected with the peripheral circuit through the through hole, a routing bonding process is replaced, signal delay is effectively reduced, and parasitic effect and transmission loss are effectively reduced.

Description

High heat dissipation fan-out packaging structure based on metal substrate

Technical Field

The utility model relates to an integrated circuit encapsulates technical field, in particular to high heat dissipation fan-out packaging structure based on metal substrate.

Background

With the rapid development of three-dimensional heterogeneous integrated packages, the integration level of chips is continuously increased, and in order to further improve the integration level, the international semiconductor technology development route organization proposes a moore law, aiming at integrating a processor, a memory, a radio frequency module, a digital module, an analog module, a photoelectric module, a sensing module and the like into a single package to realize system-in-package (SIP). If the antenna is also integrated in a system in package, it may be referred to as an antenna level package (AIP). Customized to take full advantage of the potential advantages, according to the specific end application, the SIP form covers integrated solutions from traditional 2D modules comprising multiple active chips and passive elements to more complex modules like PIP, POP, 2.5D and 3D. The used substrate materials comprise LTCC, an organic substrate, silicon, PCB, glass and plastic sealant.

Currently, the AIP research mainly focuses on the integration of a single chip transceiver and an antenna, however, the main technical problems facing the implementation of the integrated package of a multi-chip rf front end and an antenna array include: first, as the integration level is improved, the heat dissipation capacity of the active chip is increased, but the heat dissipation cannot be performed in the antenna package by using a heat sink mounted on the package, so that a high-heat dissipation package structure with high efficiency and simple structure is urgently needed for the high-integration integrated antenna and radio frequency front end package; secondly, a millimeter wave chip used at the radio frequency front end is mainly based on a compound semiconductor process, and the packaging form of the chip is limited to lead bonding by the requirements of an active surface transmission line, an inductance-capacitance air bridge and back grounding, but the parasitic effect of the bonding line cannot be ignored along with the increase of the working frequency, and meanwhile, the interconnection mode also limits the further reduction of the section of the multilayer stacked packaging body; thirdly, when the antenna and the radio frequency front end are integrated in high density, the problem of electromagnetic interference between the active chip and between the antenna and the active chip is particularly serious.

Disclosure of Invention

The utility model provides a high heat dissipation fan-out packaging structure based on metal substrate has solved the technical problem who exists among the at least one prior art.

The utility model adopts the following technical scheme: the utility model provides a high heat dissipation fan-out packaging structure based on metal substrate, includes first heat dissipation basement, be provided with at least one electrically conductive through hole that runs through on the first heat dissipation basement and the chip cavity has been seted up to first heat dissipation basement lower surface, be provided with the chip in the chip cavity, the below of first heat dissipation basement is provided with second heat dissipation basement, the upper surface of first heat dissipation basement is provided with first wiring layer and the lower surface is provided with second wiring layer, is connected through electrically conductive through hole electricity between first wiring layer and the second wiring layer, the chip is connected with the second wiring layer, be provided with the antenna on the first wiring layer.

Furthermore, the first heat dissipation substrate and the second heat dissipation substrate are made of conductive metal.

Furthermore, the surface of the first heat dissipation substrate and the inner wall of the conductive through hole are covered with first insulating layers, and the surface of the second heat dissipation substrate is covered with second insulating layers.

Furthermore, the first insulating layer and the second insulating layer are both made of resin or silicon dioxide.

Furthermore, a first bonding pad is arranged on the surface of a second wiring layer of the chip cavity, a first welding ball is arranged on the first bonding pad, and the first welding ball is connected with the chip.

Furthermore, a second bonding pad is arranged on the first wiring layer, a second solder ball is arranged on the second bonding pad, and the second solder ball is connected with the antenna.

The antenna, the second bonding pad and the second solder ball are arranged on the upper surface of the first heat dissipation substrate, and the second heat dissipation substrate is covered with the second plastic package layer.

Further, the conductive through hole is filled with a conductive medium.

Furthermore, the active surface of the chip is connected with the second wiring layer, and the back surface of the chip is flush with the lower surface of the first heat dissipation substrate.

Further, the first heat dissipation substrate and the second heat dissipation substrate are connected through a bonding process.

The utility model has the advantages that: the utility model discloses a heat dissipation basement, the material of heat dissipation basement be the metal that the heat conductivility is good for whole packaging structure possesses excellent heat dispersion. The chip is embedded in the metal substrate and is interconnected with the peripheral circuit through the through hole, a routing bonding process is replaced, signal delay is effectively reduced, and parasitic effect and transmission loss are effectively reduced. The antenna and each active chip are respectively positioned in different cavities, so that the electromagnetic isolation between the active chips and between the antennas and between the active chips is obviously improved. And a second heat dissipation substrate is added to form a good heat dissipation structure.

Drawings

Fig. 1 is a schematic diagram of the overall structure of the high heat dissipation fan-out package structure of the present invention.

Fig. 2 is a schematic structural diagram of the first heat dissipation substrate of the present invention.

Fig. 3 is a schematic diagram illustrating the fabrication of the first insulating layer according to the present invention.

Fig. 4 is a schematic diagram of the first wiring layer according to the present invention.

Fig. 5 is a schematic diagram of the chip mounting in the present invention.

Fig. 6 is a schematic view illustrating the second insulating layer of the second heat dissipation substrate according to the present invention.

Fig. 7 is a schematic view illustrating the connection between the first heat dissipation substrate and the second heat dissipation substrate according to the present invention.

Fig. 8 is a schematic diagram of the antenna installation of the present invention.

Fig. 9 is a schematic diagram of the first plastic package layer and the second plastic package layer of the present invention.

Detailed Description

In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall fall within the protection scope of the present invention.

In the embodiment of the present invention, fig. 1 is a schematic structural diagram according to the present invention, as shown in fig. 1, provided by a high heat dissipation fan-out packaging structure based on a metal substrate, the present invention specifically includes: a first heat dissipation substrate 101 and a second heat dissipation substrate 108. At least one through conductive via 105 is disposed on the first heat dissipation substrate 101, and at least one chip cavity 102 is disposed on a lower surface of the first heat dissipation substrate 101. The number of the chip cavities 102 may be two or more, and the number of the conductive vias 105 is not limited to two in fig. 1, which is determined by practical requirements and is not limited herein, and the depth and width of the chip slot are not limited. The material of the first heat dissipation substrate 101 and the second heat dissipation substrate 108 can be, but is not limited to, metal, as long as the heat dissipation performance is sufficiently high. By adopting the scheme, the chip cavities with different sizes can be formed in the same substrate, so that chips with different types and sizes can be placed, multiple chips can be packaged simultaneously, the packaging efficiency is greatly improved, and the whole size of the packaging structure can be reduced. A second heat dissipation substrate 108 is disposed below the first heat dissipation substrate 101, and heat generated by the chip body can be directly conducted to the second heat dissipation substrate and then conducted to the outside through the second heat dissipation substrate. In order to enable the heat generated by the chip to be more effectively transferred to the second heat dissipation substrate, the back surface of the chip is flush with the lower surface of the first heat dissipation substrate 101.

The first heat dissipation substrate 101 has a first wiring layer 111 on an upper surface thereof and a second wiring layer 106 on a lower surface thereof, and the first wiring layer 111 and the second wiring layer 106 are electrically connected through a conductive via 105. The chip 107 is connected to the second wiring layer 106, and an antenna 112 is disposed on the first wiring layer 111. The active surface of the chip is communicated with the first wiring layer through the solder balls and the second wiring layer through the conductive through holes, so that the active surface of the chip is further communicated with the antenna, and communication between the antenna and the chip is achieved. The conductive via 105 is filled with a conductive medium to realize electrical connection between the first wiring layer 111 and the second wiring layer 106, and the conductive medium may be copper.

In an embodiment of the present invention, the material of the first heat dissipation substrate 101 and the second heat dissipation substrate 108 is conductive metal, and the conductive metal includes but is not limited to copper, aluminum or alloy, and is required to have good heat conductivity. When the first heat dissipation substrate 101 and the second heat dissipation substrate 108 are made of conductive metal, the surface of the first heat dissipation substrate 101 and the inner wall of the conductive through hole 105 are covered with the first insulation layer 104, and the surface of the second heat dissipation substrate 108 is covered with the second insulation layer 109. The first insulating layer 104 and the second insulating layer 109 are made of resin or silicon dioxide, so that the metal substrate is insulated from the outside.

In an embodiment of the present invention, a surface of the second wiring layer 106 located in the chip cavity 102 is provided with a first bonding pad, and the first bonding pad is provided with a first solder ball, and the first solder ball is connected to the chip 107. A second bonding pad is disposed on the first wiring layer 111, and a second solder ball is disposed on the second bonding pad and connected to the antenna 112. The antenna is connected with the first heat dissipation substrate in the form of the bonding pad and the solder ball, and the chip is connected with the second heat dissipation substrate, so that the communication stability can be improved. Therefore, the heat dissipation effect of the chip can be effectively improved on the basis of low cost, the circuit layout is optimized, and a lead frame is not needed.

On this basis, the utility model discloses still include first plastic-sealed layer 113 and second plastic-sealed layer 114, first plastic-sealed layer 113 is located the upper surface and the cladding of first heat dissipation basement 101 antenna 112, second pad and second solder ball, the second plastic-sealed layer is located the lower surface and the cladding of first heat dissipation basement 101 second heat dissipation basement 108.

The high heat dissipation fan-out packaging structure based on the metal substrate is prepared by the following method:

the method comprises the following steps: as shown in fig. 2, a metal substrate is provided as the first heat dissipation substrate 101, the metal substrate needs to have a certain thickness, the material of the metal substrate may be a metal conductive material such as copper, aluminum, and the like, and needs to have a good heat conduction performance, a chip cavity 102 and a through hole 103 penetrating through the upper and lower surfaces are formed inward on the lower surface of the metal substrate through a groove milling process, and one or more through holes 103 penetrating through the upper and lower surfaces of the chip cavity 102 may be formed.

Step two: as shown in fig. 3, a first insulating layer 104 is formed on the upper and lower surfaces of the metal substrate, the surface of the chip cavity, and the sidewall of the through hole penetrating the upper and lower surfaces, and is made of an insulating dielectric material, such as resin or SiO2, so that the metal substrate is insulated from the outside.

Step three: as shown in fig. 3, a copper conductive via is formed by filling copper in a via hole penetrating through the upper and lower surfaces of the metal base through an electroplating process.

Step four: as shown in fig. 4, a second wiring layer 106 is formed on the surface of the first insulating layer 104 on the lower surface of the metal substrate by patterning, and the surface wiring layer may be a single layer or multiple layers, wherein the outermost wiring layer further includes the first pad.

Step five: as shown in fig. 5, flip chip bonding of chip 107 is performed within chip cavity 102. The chip 107 includes a first solder ball on the top layer of the chip, and the chip is flip-chip bonded to the first pad on the surface of the wiring layer, so as to electrically connect the chip and the wiring layer. Wherein the back surface of the chip faces outwards and is basically flush with the lower surface of the metal substrate.

Step six: as shown in fig. 6, another thin metal substrate is provided as a second heat dissipation substrate, which may be made of a conductive metal material such as copper, aluminum, etc., and is required to have a good thermal conductivity; forming a second insulating layer 109 on the upper and lower surfaces of the second heat dissipation substrate 108, wherein the material of the second insulating layer is an insulating dielectric material, such as resin and SiO2, so that the metal substrate is insulated from the outside;

step seven: and forming a wiring layer on the dielectric layer on the upper surface of the second metal substrate 108 through patterning, wherein the pattern of the wiring layer corresponds to the lower surface of the metal substrate 101 except for the chip cavity.

Step eight: as shown in fig. 7, the first heat dissipation substrate 101 and the second heat dissipation substrate 108 are connected by a bonding process. Specifically, the second heat dissipation substrate 108 obtained above is assembled with the first heat dissipation substrate 101 by using a bonding process to form a sealing structure, so that the back surface of the chip 107 is in contact with the second metal substrate 108.

Step nine: as shown in fig. 7, a surface first wiring layer 111 is formed on the surface of the first dielectric layer 104 on the upper surface of the metal substrate 101 by patterning, the surface wiring layer may be a single layer or multiple layers, wherein the outermost wiring layer further includes a second pad. The second wiring layer 106 on the upper surface of the metal base 101 and the first wiring layer 111 on the lower surface are interconnected by a conductive via 105 penetrating the upper and lower surfaces of the metal base.

Step ten: as shown in fig. 8, an antenna 112 is provided, which is flip-chip bonded to the second pads on the upper surface of the metal substrate to implement the signal interconnection between the antenna system and the chip.

Step eleven: as shown in fig. 9, the first plastic package layer 113 is formed on the upper surface of the wiring layer on the upper surface of the metal substrate, and the first plastic package layer fills the gap between the second solder ball and the second pad of the antenna and completely encapsulates and encapsulates the antenna system. And finally, forming the second plastic package layer 114 on the lower surface of the second metal substrate, and completely packaging and plastically packaging the second heat dissipation substrate.

Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to the examples, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the scope of the claims of the present invention.

Claims

1. The high-heat-dissipation fan-out packaging structure based on the metal substrate is characterized by comprising a first heat-dissipation substrate (101), wherein at least one penetrating conductive through hole (105) is formed in the first heat-dissipation substrate (101), at least one chip cavity (102) is formed in the lower surface of the first heat-dissipation substrate (101), a chip (107) is arranged in the chip cavity (102), a second heat-dissipation substrate (108) is arranged below the first heat-dissipation substrate (101), a first wiring layer (111) is arranged on the upper surface of the first heat-dissipation substrate (101), a second wiring layer (106) is arranged on the lower surface of the first heat-dissipation substrate, the first wiring layer (111) is electrically connected with the second wiring layer (106) through the conductive through hole (105), the chip (107) is connected with the second wiring layer (106), and an antenna (112) is arranged on the first wiring layer (111).

2. The metal substrate-based high heat dissipation fan-out package structure of claim 1, wherein the first heat dissipation substrate (101) and the second heat dissipation substrate (108) are both made of conductive metal.

3. The metal substrate-based high heat dissipation fan-out package structure of claim 2, wherein a surface of the first heat dissipation substrate (101) and an inner wall of the conductive via (105) are covered with a first insulating layer (104), and a surface of the second heat dissipation substrate (108) is covered with a second insulating layer (109).

4. The metal substrate-based high heat dissipation fan-out package structure of claim 3, wherein the materials of the first insulating layer (104) and the second insulating layer (109) are both resin or silicon dioxide.

5. The metal substrate-based high heat dissipation fan-out package structure recited in claim 1, wherein a surface of the second routing layer (106) located in the chip cavity (102) is provided with first bonding pads, and first solder balls are arranged on the first bonding pads and connected with the chip (107).

6. The metal substrate-based high heat dissipation fan-out package structure of claim 1, wherein a second solder pad is disposed on the first routing layer (111), and a second solder ball is disposed on the second solder pad and connected to the antenna (112).

7. The metal substrate-based high heat dissipation fan-out package structure of claim 1, further comprising a first molding compound layer (113) and a second molding compound layer (114), wherein the first molding compound layer (113) is located on the upper surface of the first heat dissipation substrate (101) and covers the antenna (112), the second bonding pads and the second solder balls, and the second molding compound layer is located on the lower surface of the first heat dissipation substrate (101) and covers the second heat dissipation substrate (108).

8. The metal substrate-based high heat dissipation fan-out package structure of claim 1, wherein the conductive via (105) is filled with a conductive dielectric.

9. The metal base based high heat dissipation fan-out package structure of claim 1, in which a back surface of the chip is flush with a lower surface of the first heat dissipating base (101).

10. The metal substrate-based high heat dissipation fan-out package structure of claim 1, wherein the first heat dissipation substrate (101) and the second heat dissipation substrate (108) are connected by a bonding process.