CN218240215U - Public special module power detection circuitry - Google Patents

Abstract

The utility model relates to a public special module power detection circuitry, including digital signal processor, the transmission signal passageway, the power control passageway, the power detection passageway, digital signal processor's signal output part respectively with the signal input part of transmission signal passageway, the signal input part of power control passageway is connected, digital signal processor's signal input part and power detection passageway's signal output part are connected, the power acquisition end of power detection passageway is connected with the signal transmission end of transmission signal passageway, the analog signal output part of power control passageway is connected with the analog signal input part of the power amplifier of transmission signal passageway. The beneficial effects are that: the power detection channel is used for sampling the actual power of the transmitting terminal of the transmitting signal channel, the actual power information is fed back to the digital signal processor, the power control channel is matched with the transmitting signal channel, the actual power of the transmitting terminal of the transmitting signal channel is adjusted according to the communication requirement, and the power consumption of the LTE terminal communication system is reduced.

Description

Public special module power detection circuit

Technical Field

The utility model relates to a public special module field especially relates to a public special module power detection circuitry.

Background

In a 4G LTE public and private communication system, under the condition of medium-strength signal network coverage, a terminal can meet the communication requirement without transmitting maximum power, the working voltage of the whole system, particularly a Power Amplifier (PA), is still higher at the moment, the working efficiency of the PA is lower at the moment, and the power consumption of the whole system is wasted.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome the above problem that prior art exists, provide a public special module power detection circuit.

For realizing above-mentioned technical purpose, reach above-mentioned technological effect, the utility model discloses a following technical scheme realizes:

a power detection circuit of a public and special module comprises a digital signal processor, a transmitting signal channel, a power control channel and a power detection channel, wherein a signal output end of the digital signal processor is respectively connected with a signal input end of the transmitting signal channel and a signal input end of the power control channel, the signal input end of the digital signal processor is connected with a signal output end of the power detection channel, a power acquisition end of the power detection channel is connected with a signal transmitting end of the transmitting signal channel, and an analog signal output end of the power control channel is connected with an analog signal input end of a power amplifier of the transmitting signal channel.

The transmitting signal channel comprises a variable gain amplifier and a power amplifier which are connected, the signal input end of the variable gain amplifier is connected with the signal output end of a digital signal processor, the serial interface of the digital signal processor is connected with the serial interface of the variable gain amplifier, and the I/O interface of the digital signal processor is connected with the I/O interface of the power amplifier.

The power control channel comprises a digital-to-analog converter and a DC-DC converter, wherein the signal input end of the digital-to-analog converter is connected with the signal output end of the digital signal processor, the analog signal output end of the digital-to-analog converter is connected with the analog signal input end of the DC-DC converter, and the analog signal output end of the DC-DC converter is connected with the analog signal input end of the power amplifier.

The power detection channel comprises a coupler, a detector, an attenuation network and an analog-to-digital converter which are connected in sequence.

The utility model has the advantages that: the method comprises the steps of sampling the actual power of a transmitting terminal of a transmitting signal channel by using a power detection channel, feeding actual power information back to a digital signal processor, matching the power control channel with the transmitting signal channel, adjusting the actual power of the transmitting terminal of the transmitting signal channel according to communication requirements, and reducing the power consumption of an LTE terminal communication system.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without undue limitation to the invention. In the drawings:

FIG. 1 is a block diagram of a power detection circuit of a public module of the present invention;

the reference numbers in the figures illustrate: the system comprises a transmission signal channel 100, a power control channel 200, a power detection channel 300, a digital signal processor 1, a variable gain amplifier 2, a power amplifier 3, an antenna 4, a digital-to-analog converter 5, a DC-DC converter 6, a coupler 7, a detector 8, an attenuation network 9 and an analog-to-digital converter 10.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

As shown in fig. 1, a power detection circuit for a public specific module includes a digital signal processor 1, a transmission signal channel 100, a power control channel 200, and a power detection channel 300, wherein a signal output end of the digital signal processor 1 is connected to a signal input end of the transmission signal channel 100 and a signal input end of the power control channel 200, respectively, a signal input end of the digital signal processor 1 is connected to a signal output end of the power detection channel 300, a power acquisition end of the power detection channel 300 is connected to a signal transmission end of the transmission signal channel 100, and an analog signal output end of the power control channel 300 is connected to an analog signal input end of a power amplifier 3 of the transmission signal channel 100.

The transmission signal channel 100 comprises a variable gain amplifier 2 and a power amplifier 3 which are connected, wherein the signal input end of the variable gain amplifier is connected with the signal output end of a digital signal processor, the serial interface of the digital signal processor is connected with the serial interface of the variable gain amplifier, the I/O interface of the digital signal processor is connected with the I/O interface of the power amplifier, and the signal transmission end of the power amplifier is connected with a transmission antenna 4.

The power control channel 200 comprises a digital-to-analog converter 5 and a DC-DC converter 6, wherein a signal input end of the digital-to-analog converter is connected with a signal output end of the digital signal processor, an analog signal output end of the digital-to-analog converter is connected with an analog signal input end of the DC-DC converter, and an analog signal output end of the DC-DC converter is connected with an analog signal input end of the power amplifier.

The power detection channel 300 comprises a coupler 7, a detector 8, an attenuation network 9 and an analog-to-digital converter 10 which are connected in sequence. The coupler is a directional coupler and the detector is an envelope detector.

The design principle is as follows:

1. transmission signal path

1.1 calibration of the transmitted Power

In order to overcome the near-far effect, reduce interference to other users and unnecessary power consumption, and also to meet the requirement of cell coverage, the transmission power of the terminal is required to have a certain dynamic range. For example, after considering a certain margin, the platform requires the terminal transmission power level to cover-44 dBm to 25dBm. As is known, the power control has three elements: PA (power amplifier) gain mode, PA (power amplifier) voltage codeword, APC (transmitter automatic gain control) value. Therefore, the transmission power is calibrated, and the transmission power configuration (PA gain mode, PA voltage code word, APC value) corresponding to each transmission power level is calibrated under the reference temperature and the reference frequency point and on the premise of meeting the ACLR (adjacent channel leakage ratio) index. Usually, the PA gain mode and PA voltage codeword corresponding to each transmit power level are already given, and the calibration process simply scans the APC value to obtain the APC value that can make the output power be the desired power. Meanwhile, if PA voltage codewords corresponding to different given transmit power levels are different, the transmit power calibration process actually already includes APT calibration.

1.2 transmit power temperature correction

1.2.1, output power

The output power must be kept within a valid range. The effective range of the maximum output power at normal temperature is given by the lower limit of power fluctuation and the upper limit of power fluctuation.

1.2.2 temperature Effect

In order to shorten the calibration time, the transmit power calibration is usually performed only at the reference temperature, and all other temperatures share the calibration value at the reference temperature. However, under the same transmit power configuration (PA gain mode, PA voltage codeword, APC value), high temperature will cause the output power to drop, and low temperature will cause the output power to rise. Therefore, when the temperature changes, the output power must be temperature-corrected in order to always keep the output power within the effective range.

1.2.3 temperature Compensation Collection

Firstly, calling a transmitting power configuration corresponding to a power level of 22dBm under a reference temperature and a reference frequency point obtained by transmitting power calibration, testing actual output power under the conditions of the reference temperature and the reference frequency point, and taking the actual output power as reference power; then, keeping the configuration of the reference frequency point and the transmitting power unchanged, collecting output power at all temperatures except the reference temperature, and comparing the output power with the reference power; finally, the difference (i.e., the temperature correction value, actually corrected in the form of an APC value) is saved.

1.2.4 temperature correction

Temperature correction, namely, after obtaining the emission power configuration under the reference temperature and the reference frequency point by checking the emission power configuration table, before writing the emission power configuration table into hardware, firstly judging the current temperature, and if the current temperature is the reference temperature, directly writing the current temperature into the hardware; if not, a temperature correction value should be added.

1.3 transmit power frequency correction

1.3.1, frequency influence

In order to shorten the calibration time, generally, one frequency band is only calibrated for the transmission power at the reference frequency point, and all other frequencies in the frequency band share the calibration value at the reference frequency point. However, under the same transmit power configuration (PA gain mode, PA voltage codeword, APC value), there is a certain fluctuation in the output power of the antenna port for different frequency points within the same frequency band. Knowing that the output power must be kept within the effective range, in order to keep the output power of all frequency points in the same frequency band within the effective range, the output power must be frequency compensated.

1.3.2 description of frequency complementation

The whole frequency band is divided into a plurality of sub-bands (such as a center sub-band, a low sub-band and a high sub-band, and whether the fluctuation in the band is severe or not is considered when the whole frequency band is divided into the plurality of sub-bands), a typical frequency point is selected on each sub-band, and all frequency points on the sub-bands share the correction value of the typical frequency point on the sub-band (under the same temperature and power configuration, the difference value between the output power of the typical frequency point on the sub-band and the reference power).

1.3.3, complementary frequency acquisition

Firstly, calling a transmitting power configuration corresponding to a reference temperature obtained by transmitting power calibration and a power level of 19dBm (frequency calibration should be carried out in a linear region) under a reference frequency point, testing actual output power under the conditions of the reference temperature and the reference frequency point, and taking the actual output power as reference power; then, keeping the reference temperature and the emission power configuration unchanged, collecting the output power of all typical frequency points except the reference frequency point, and comparing the output power with the reference power; finally, the difference (i.e., the frequency correction value, actually corrected in the form of an APC value) is saved.

1.3.4, frequency correction

Frequency correction, namely, after obtaining the reference temperature and the emission power configuration under the reference frequency point by checking the emission power configuration table, before writing the emission power configuration into hardware, firstly judging the current frequency point, and if the current frequency point is the reference frequency point, directly writing the current frequency point into the hardware; if the frequency is not the reference frequency point, the frequency correction value is added.

2. Power detection channel

2.1 overview of Power detection

And the base station indicates the expected power of the terminal on the antenna port through the TPC according to actual conditions. The terminal firstly determines the transmitting power grade of the terminal according to the expected power; then, taking out corresponding transmission power configuration (PA gain mode, PA voltage code word and APC value) from a transmission power configuration table calibrated under the reference temperature and the reference frequency point; secondly, temperature correction and frequency correction are carried out according to the temperature and the frequency point; and finally, writing the corrected transmission power configuration into hardware through a power control channel so as to control the actual power of the antenna port of the user. For some reasons, the calibrated transmit power configurations of the power classes may have some differences in actual situations, for example, the transmit power configuration of the power class 22dBm calibrated in the cable mode, the reference temperature and the reference frequency point may be 21dBm in the air interface mode, the reference temperature and the reference frequency point, and as can be known from the foregoing description of temperature correction and frequency correction, the temperature correction and frequency correction of the transmit signal channel only have the effect of eliminating the influence of temperature and frequency, and it is ensured that the effect of calling the transmit power configuration table calibrated in the reference temperature and the reference frequency point by all the temperature points and frequency points is the same (as the reference temperature and the reference frequency point), that is, the actual power configurations in the air interface mode, all the temperature points and the frequency points are 21dBm. Therefore, to eliminate the difference between the actual power and the desired power, the actual power is pulled to the desired power, and only power detection can be introduced.

As shown in fig. 1, the power detection channel includes: a directional coupler, an envelope detector, an attenuation network and an analog-to-digital converter. The method comprises the steps that a directional coupler carries out coupling sampling on a transmitting signal channel according to a certain proportion, then the transmitting signal is sent to an envelope detector for envelope detection, then detected envelope voltage is attenuated through an attenuation network so as to meet the requirement of input driving voltage of a next-stage ADC, finally the envelope voltage is sent to the ADC for analog-to-digital conversion, a DBB-DSP obtains a power detection ADC value through SPI reading operation after conversion, then the DBB-DSP can determine the actual power of an antenna port according to a power detection calibration table (temperature correction and frequency correction of a power detection channel are actually added), and therefore power detection correction (actually correction is carried out in the form of an APC value) is carried out on the existing transmitting power configuration (including APT, temperature compensation and frequency compensation) so that the actual power is corrected to the expected power.

2.2 Power detection calibration

And power detection calibration, namely calibrating under the reference temperature and the reference frequency point to obtain a power detection calibration table.

2.2.1, power detection calibration issues

During calibration, a signal source is required to directly inject a signal with accurate size into an input port of the coupler, a plate-level signal is not recommended, because the size of the plate-level signal cannot be accurately controlled and temperature change is easily introduced into PA; strictly controlling the configuration of the output signal of the signal source so as to make the output signal representative; the line loss is required to be accurate; at present, no special test port is used for filling signals into the input port of the coupler, and if an opening line is used, the effect is possibly poor; the calibration is performed at a reference temperature and a reference frequency.

2.2.2 Power detection calibration scheme

Under the reference temperature and the reference frequency point, the software on the PC side remotely controls the output power of the signal source through GPIB or LAN, and the power detection ADC value is acquired through a physical layer software interface after the output power of the signal source is regulated stably.

If a board level signal: after the transmission power is calibrated, under the reference temperature and the reference frequency point, the software on the PC side sequentially changes the power level (namely, changes the transmission power configuration), and reads the actual power from the instrument (such as a frequency spectrograph, a comprehensive measuring instrument and the like) through GPIB or LAN after the transmission power configuration (temperature compensation and frequency compensation are not added) is changed every time, and simultaneously obtains the power detection ADC value through a physical layer software interface.

2.3 Power detection correction

The power detection channel is also affected by temperature and frequency like the transmission signal channel, but in order to shorten the calibration time, calibration is usually performed only at the reference temperature and the reference frequency point, and then all the temperatures and the frequency points share the power detection calibration table calibrated at the reference temperature and the reference frequency point. Therefore, the power detection channel must also be temperature corrected and frequency corrected like the transmit signal channel (the power detection correction can be done with a board level signal, since this is not related to absolute power, but only relative to a reference, but care should be taken to the effect of the transmit signal channel on ambient temperature).

2.3.1 Power sense temperature correction

2.3.1.1, acquisition of warming complement

Firstly, testing a power detection ADC value when the output power of a signal source is 22dBm (whether one power grade or a plurality of power grades are collected to see the actual effect) under the conditions of a reference temperature and a reference frequency point, and taking the power detection ADC value as a reference ADC value; then keeping the output power of the reference frequency point and the signal source unchanged, collecting power detection ADC values at all temperatures except the reference temperature, and comparing the power detection ADC values with the reference ADC value; finally, the difference (i.e., the temperature correction value) is saved.

2.3.1.2 temperature correction

Temperature correction, namely, after an ADC value is detected from SPI read back power, judging the current temperature, and if the current temperature is a reference temperature, directly checking a power detection calibration table to obtain the actual power; if the reference temperature is not the reference temperature, the temperature correction value is added, and then the power detection calibration table is checked to obtain the actual power.

2.3.2 Power detection frequency correction

2.3.2.1, complementary frequency acquisition

Firstly, testing a power detection ADC value when the output power of a signal source is 19dBm (whether one power grade or a plurality of power grades are collected to see the actual effect) under the conditions of a reference temperature and a reference frequency point, and taking the power detection ADC value as a reference ADC value; then keeping the reference temperature and the output power of the signal source unchanged, collecting power detection ADC values under all frequency points except the reference frequency point, and comparing the power detection ADC values with the reference ADC value; finally, the difference (i.e., the frequency correction value) is saved.

2.3.2.2, frequency correction

Frequency correction, namely, after an ADC value is detected from SPI read back power, judging a current frequency point, and if the current frequency point is a reference frequency point, directly checking a power detection calibration table to obtain actual power; if the frequency point is not the reference frequency point, the frequency correction value is added, and then the power detection calibration table is checked to obtain the actual power.

2.4 Power detection implementation details

The power detection channel has a power detection range beyond which detection values will be inaccurate or undetectable, which is limited by the various elements (directional coupler, envelope detector, attenuation network, and analog-to-digital converter) on the power detection channel. For example, directional couplers have an upper limit on input power that would otherwise damage the device; the minimum signal which can be detected by the envelope detector is certain, and when the input signal is too small, the minimum signal can be submerged by self bottom noise and cannot be detected; the attenuation network has damage to the small signal; the analog-to-digital converter also has its optimum operating range, and is inaccurate or swamped by noise when it is out of the operating range.

The coupler coupling ratio must not be too large, which may damage the desired signal on the transmit signal path or take into account coupling losses when performing power detection compensation.

In a linear amplification system such as non-GMSK, the power detection compensation method usually depends on the APC value for compensation, so the compensation accuracy is limited by the Step size of VGA. In the context of GMSK and other saturated PA applications, compensation is usually performed by the Vramp DAC value.

Since the power detection and the temperature detection share one ADC, the power detection ADC value and the temperature ADC value are read out in the power detection temperature correction process and when the power detection and the transmission signal temperature correction coexist in the transmission.

The power detection length is to be determined. The power detection length cannot be too short, otherwise, in a system with a large peak-to-average ratio, the actual power obtained by power detection will not be representative, and then the risk of overload at a large envelope and noise flooding at a small envelope exists. The power detection length is determined as one sub-frame, i.e. 1ms, should not be problematic, but according to our knowledge, there are three SPI operations (one APC for the first 12 symbols and one APC for the next 2 symbols) for setting APC in one sub-frame of the physical layer, so the power detection length also needs to be discussed with the physical layer.

A power detection period. The power detection is carried out for a long time, the power detection needs to be determined according to actual conditions, power is consumed when the power detection is too frequent, and the power detection can be carried out once when a TPC command changes.

In high power, the power detection cannot replace temperature compensation, the power detection has hysteresis, the power detection needs to be detected for a period of time and then can provide guidance for power control in subsequent time, therefore, the temperature compensation is needed when the burst is far away from the emission or just powered on and just after a few subframes from a SLEEP state, because the temperature compensation does not need sampling, a compensation value can be determined in idle time, and then the compensation can be immediately carried out when the burst exists. Therefore, power detection and temperature compensation are adopted at high and medium power, and temperature compensation is adopted at low power.

The actual power STEP corresponding to the power detection ADC value in the power detection calibration table is 1dB (the accuracy of the transmitted power calibration is needed to be seen when a board-level signal is calibrated), and the compensation precision is the STEP (0.25 dB) of VGA (video graphics array), so that a piecewise linear algorithm can be adopted (actually, a directional coupler is in fixed-ratio coupling, envelope detection is linear, an attenuation network is in fixed-ratio attenuation, and the ADC is also linear in a working range, so that the power detection channel as a whole also needs to be a linear channel, as for the linearity, the subsequent actual measurement is determined again).

Example, auxADC operation introduces:

the register address is 40; bit [24 ]; bit [0] is an enable switch of an internal temperature sensor of the RFIC, and an external temperature-sensitive resistor is adopted, so that the bit can write 0.

AUXADC full scale voltage selection is performed through bit 7, and the voltage selection is performed at 1.2V and 2.4V. The range of input signals (coupler coupling ratio, attenuation value of a debugging attenuation network) needs to be reasonably selected, otherwise, the detection range of a power detection channel is influenced, and the input dynamic range is large at 2.4V, but the power consumption is also large.

AUXADC reference clock selection is made via bit [6 ]. Which we have designed is 26MHz.

AUXADC working clock selection is performed through bit [10 ]. The sampling law is satisfied, and therefore, the envelope frequency is reasonably selected, otherwise, the detection accuracy is affected.

The AUXADC input signal source multiplexing selection is carried out through bit [ 9. And carrying out power detection and temperature detection selection.

The AUXADC working mode selection is carried out through bit [1], and the AUXADC working mode selection comprises single and continue. Single is only converted once and then automatically closed (bit 11 is automatically 0); continue with multiple conversion until artificial off (SPI writes bit [11] to 0), the final analog-to-digital conversion result is the average of multiple conversion results.

SPI writes bit [2] to 1, turns on the AUXADC working clock.

SPI writes bit [12] to 1, turns on the AUXADC working voltage.

SPI writes bit [11] to 1, letting AUXADC start the analog-to-digital conversion. If the mode is a single mode, 0 is automatically set after one conversion, so that the analog-digital conversion is automatically closed; if the mode is the continue mode, when the stop is needed, the SPI writes bit [11] to 0, and the analog-to-digital conversion is closed.

After the analog-to-digital conversion is turned off, the SPI reads the register 40, and takes the analog-to-digital conversion result on its bit [24 ].

The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the above embodiments, and that the foregoing embodiments and descriptions are provided only to illustrate the principles of the present invention without departing from the spirit and scope of the present invention.

Claims (6)

1. A public specific module power detection circuit is characterized in that: including digital signal processor, transmission signal passageway, power control passageway, power detection passageway, digital signal processor's signal output part is connected with the signal input part of transmission signal passageway, the signal input part of power control passageway respectively, digital signal processor's signal input part and power detection passageway's signal output part are connected, the power acquisition end of power detection passageway is connected with the signal transmission end of transmission signal passageway, the analog signal output part of power control passageway is connected with the analog signal input part of the power amplifier of transmission signal passageway.

2. The public module power detection circuit of claim 1, wherein: the transmitting signal channel comprises a variable gain amplifier and a power amplifier which are connected, the signal input end of the variable gain amplifier is connected with the signal output end of a digital signal processor, the serial interface of the digital signal processor is connected with the serial interface of the variable gain amplifier, and the I/O interface of the digital signal processor is connected with the I/O interface of the power amplifier.

3. The public module power detection circuit of claim 2, wherein: and the signal transmitting end of the power amplifier is connected with a transmitting antenna.

4. The utility module power detection circuit of claim 2, characterized in that: the power control channel comprises a digital-to-analog converter and a DC-DC converter, wherein the signal input end of the digital-to-analog converter is connected with the signal output end of the digital signal processor, the analog signal output end of the digital-to-analog converter is connected with the analog signal input end of the DC-DC converter, and the analog signal output end of the DC-DC converter is connected with the analog signal input end of the power amplifier.

5. The public module power detection circuit of claim 2, wherein: the power detection channel comprises a coupler, a detector, an attenuation network and an analog-to-digital converter which are connected in sequence.

6. The public module power detection circuit of claim 5, wherein: the coupler is a directional coupler and the detector is an envelope detector.

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