CN218183327U - Analog switch - Google Patents

Abstract

The utility model provides an analog switch, which is connected with a first node through a source electrode and a substrate of a first PMOS (P-channel metal oxide semiconductor) tube, a source electrode and a substrate of a second PMOS tube, a substrate of a third PMOS tube, a source electrode of a fourth NMOS (N-channel metal oxide semiconductor) tube, a source electrode of a fifth NMOS (N-channel metal oxide semiconductor) tube and a drain electrode of a sixth PMOS tube, so that the first PMOS tube, the second PMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth PMOS tube form a bias circuit of the third PMOS tube; the source electrode and the substrate of the first NMOS tube, the source electrode and the substrate of the second NMOS tube, the substrate of the third NMOS tube, the source electrode and the substrate of the fourth PMOS tube, the source electrode and the substrate of the fifth PMOS tube and the drain electrode of the sixth NMOS tube are connected to the second node, so that the first NMOS tube, the second NMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth NMOS tube form a bias circuit of the third NMOS tube, and therefore the problems of electric leakage risk caused by crosstalk of the output end and generation of the third PMOS tube and the third NMOS tube due to substrate bias effect are solved.

Description

Analog switch

Technical Field

The utility model relates to an integrated circuit field, in particular to analog switch.

Background

An analog switch is an interface which can pass or block analog signals and is mainly used for analog signals and digital control. With the development of integrated circuits in recent years, the switching performance of analog switches has been greatly improved, and analog switches can operate at very low operating voltage, have relatively low on-resistance and small package size, and are widely used in test equipment, communication products, multimedia systems, and the like.

At present, a transmission gate circuit is used as an analog switch, the analog switch comprises a PMOS tube and an NMOS tube which are connected in parallel, and due to the fact that a bias effect (namely a body effect) exists on a substrate of the PMOS tube and a substrate of the NMOS tube, the bias effect influences the threshold voltage of the substrate of the PMOS tube and the threshold voltage of the NMOS tube, the on-resistance is greatly increased, even the transmission gate circuit cannot be conducted and cannot transmit, and therefore the transmission gate circuit cannot be regarded as the switch.

In order to solve the above problems, the analog switch shown in fig. 1 is adopted to include a PMOS transistor TP and an NMOS transistor TN, the substrate of the PMOS transistor is connected with an input terminal Vi after being short-circuited with a source electrode, the input terminal receives an analog signal, the substrate of the NMOS transistor is also connected with the input terminal Vi after being short-circuited with the source electrode, both the drain electrode of the PMOS transistor and the drain electrode of the NMOS transistor are connected with an output terminal Vout, the gate electrode of the PMOS transistor receives a first control signal C1, and the NMOS transistor receives a second control signal C2. The analog switch enables the PMOS tube and the NMOS tube to have no bias effect, and solves the problem caused by the substrate bias effect. However, the output terminal of the analog switch may cross-talk with the input terminal, which may result in failure to turn off, causing a leakage risk.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an analog switch can solve the substrate biasing effect of PMOS pipe and NMOS pipe in the analog switch to and avoided the output can crosstalk the input, arouse the risk of electric leakage.

In order to solve the above problems, the present invention provides an analog switch, comprising a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor, said analog switch having an input terminal and an output terminal,

the source electrode and the substrate of the first PMOS tube, the source electrode and the substrate of the second PMOS tube, the substrate of the third PMOS tube, the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube and the drain electrode of the sixth PMOS tube are connected to a first node P, and the source electrode of the sixth PMOS tube is connected with a power supply; the source electrode and the substrate of the first NMOS transistor, the source electrode and the substrate of the second NMOS transistor, the substrate of the third NMOS transistor, the source electrode and the substrate of the fourth PMOS transistor, the source electrode and the substrate of the fifth PMOS transistor and the drain electrode of the sixth NMOS transistor are connected to a second node N, and the source electrode of the sixth NMOS transistor is grounded; the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth NMOS tube are all connected with a first control signal; the grid electrode of the first NMOS tube, the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube, the grid electrode of the fourth NMOS tube, the grid electrode of the fifth NMOS tube and the grid electrode of the sixth PMOS tube are all connected with a second control signal; the drain electrode of the first PMOS tube, the drain electrode and the substrate of the fourth NMOS tube, the drain electrode of the third PMOS tube, the drain electrode of the third NMOS tube, the drain electrode of the fourth PMOS tube and the drain electrode of the first NMOS tube are all connected with the input end; the drain electrode of the second PMOS tube, the drain electrode and the substrate of the fifth NMOS tube, the source electrode of the third PMOS tube, the source electrode of the third NMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the second NMOS tube are all connected with the output end.

Optionally, when the first control signal is at a high level, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are all turned off, and the sixth NMOS transistor is turned on; and

when the second control signal is at a low level, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are all turned off, and the sixth PMOS transistor is turned on.

Optionally, when the first control signal is at a low level, the second control signal is at a high level, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are all turned on, and the sixth NMOS transistor and the sixth PMOS transistor are all turned off.

Optionally, when the first control signal is at a high level and the second control signal is at a low level, the analog switch is turned off.

Furthermore, when the analog switch is turned off, the sixth PMOS transistor is turned on, and the substrate of the first PMOS transistor, the substrate of the second PMOS transistor and the substrate of the third PMOS transistor are all pulled up to the power supply through the sixth PMOS transistorIs/are as followsAnd voltage is applied, so that the first PMOS tube, the second PMOS tube and the third PMOS tube can be completely closed.

Further, when the analog switch is turned off, the sixth NMOS transistor is turned on, and the substrate of the first NMOS transistor, the substrate of the second NMOS transistor, and the substrate of the third NMOS transistor are all pulled down to the ground through the sixth NMOS transistor, so that the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor can be completely turned off.

Optionally, when the first control signal is at a low level, the second control signal is at a high level, and the analog switch is turned on.

Further, when the analog switch is turned on, the substrate of the third PMOS transistor is connected to the first node, and the on-state potential at the first node is determined by the first PMOS transistor, the second PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor.

Further, when the analog switch is turned on, the substrate of the third NMOS transistor is connected to the second node, and the on-state potential of the second node is determined by the first NMOS transistor, the second NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor.

Compared with the prior art, the utility model discloses following beneficial effect has:

the utility model provides an analog switch, through source electrode and substrate of first PMOS pipe, source electrode and substrate of second PMOS pipe, the substrate of third PMOS pipe, the source electrode of fourth NMOS pipe, the source electrode of fifth NMOS pipe and the drain electrode of sixth PMOS pipe connect at first node for first PMOS pipe, second PMOS pipe, fourth NMOS pipe, fifth NMOS pipe and sixth PMOS pipe constitute the bias circuit of third PMOS pipe; the source electrode and the substrate of the first NMOS tube, the source electrode and the substrate of the second NMOS tube, the substrate of the third NMOS tube, the source electrode and the substrate of the fourth PMOS tube, the source electrode and the substrate of the fifth PMOS tube and the drain electrode of the sixth NMOS tube are connected to a second node, so that the first NMOS tube, the second NMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth NMOS tube form a bias circuit of the third NMOS tube, and therefore the problems of electric leakage caused by crosstalk of the input end by the output end and generation of the third PMOS tube and the third NMOS tube due to a substrate bias effect are solved.

Drawings

FIG. 1 is a circuit diagram of an analog switch;

fig. 2 is a circuit diagram of an analog switch according to an embodiment of the present invention.

Detailed Description

An analog switch of the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the appended drawings, in which preferred embodiments of the invention are shown, it being understood that those skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.

In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be noted that the drawings are in simplified form and are not to be construed as precise ratios, which are merely intended to facilitate and clarify the explanation of the embodiments of the present invention.

Fig. 2 is a circuit diagram of an analog switch provided in this embodiment. As shown in fig. 2, the present embodiment provides an analog switch, which includes a first PMOS transistor TP1, a second PMOS transistor TP2, a third PMOS transistor TP3, a fourth PMOS transistor TP4, a fifth PMOS transistor TP5, a sixth PMOS transistor TP6, a first NMOS transistor TN1, a second NMOS transistor TN2, a third NMOS transistor TN3, a fourth NMOS transistor TN4, a fifth NMOS transistor TN5, and a sixth NMOS transistor TN6, wherein the analog switch has an input terminal Vi and an output terminal Vout.

The source electrode and the substrate of the first PMOS tube TP1, the source electrode and the substrate of the second PMOS tube TP2, the substrate of the third PMOS tube TP3, the source electrode of the fourth NMOS tube TN4, the source electrode of the fifth NMOS tube TN5 and the drain electrode of the sixth PMOS tube TP6 are connected to a first node P, the source electrode of the sixth PMOS tube TP6 is connected with a power supply, and the power supply provides a voltage VCC; the source electrode and the substrate of the first NMOS transistor TN1, the source electrode and the substrate of the second NMOS transistor TN2, the substrate of the third NMOS transistor TN3, the source electrode and the substrate of the fourth PMOS transistor TP4, the source electrode and the substrate of the fifth PMOS transistor TP5 and the drain electrode of the sixth NMOS transistor TN6 are connected to a second node N, and the source electrode of the sixth NMOS transistor TN6 is grounded GND; the grid electrode of the first PMOS tube TP1, the grid electrode of the second PMOS tube TP2, the grid electrode of the third PMOS tube TP3, the grid electrode of the fourth PMOS tube TP4, the grid electrode of the fifth PMOS tube TP5 and the grid electrode of the sixth NMOS tube TN6 are all connected with a first control signal C1; the grid electrode of the first NMOS transistor TN1, the grid electrode of the second NMOS transistor TN2, the grid electrode of the third NMOS transistor TN3, the grid electrode of the fourth NMOS transistor TN4, the grid electrode of the fifth NMOS transistor TN5 and the grid electrode of the sixth PMOS transistor TP6 are all connected with a second control signal C2; the drain electrode of the first PMOS tube TP1, the drain electrode and the substrate of the fourth NMOS tube TN4, the drain electrode of the third PMOS tube TP3, the drain electrode of the third NMOS tube TN3, the drain electrode of the fourth PMOS tube TP4 and the drain electrode of the first NMOS tube TN1 are all connected with the input end Vi; the drain electrode of the second PMOS transistor TP2, the drain electrode and the substrate of the fifth NMOS transistor TN5, the source electrode of the third PMOS transistor TP3, the source electrode of the third NMOS transistor TN3, the drain electrode of the fifth PMOS transistor TP5 and the drain electrode of the second NMOS transistor TN2 are all connected to the output terminal Vout.

The substrates of the first PMOS transistor TP1, the second PMOS transistor TP2, the third PMOS transistor TP3, the fourth PMOS transistor TP4, the fifth PMOS transistor TP5, the sixth PMOS transistor TP6, the first NMOS transistor TN1, the second NMOS transistor TN2, the third NMOS transistor TN3, the fourth NMOS transistor TN4, the fifth NMOS transistor TN5 and the sixth NMOS transistor TN6 are all P-type substrates, and the source and drain electrodes of the first PMOS transistor TP1, the second PMOS transistor TP2, the third PMOS transistor TP3, the fourth PMOS transistor TP4, the fifth PMOS transistor TP5 and the sixth PMOS transistor TP6 are all formed in an NWELL (N-well region), that is, an NWELL is formed in the P-type substrate, and the source and drain electrodes are formed in the NWELL. The source electrodes of the first PMOS transistor TP1, the second PMOS transistor TP2, the third PMOS transistor TP3, the fourth PMOS transistor TP4, the fifth PMOS transistor TP5 and the sixth PMOS transistor TP6 are all doped with P-type ions, i.e., P + source electrodes, and the source electrodes of the first NMOS transistor TN1, the second NMOS transistor TN2, the third NMOS transistor TN3, the fourth NMOS transistor TN4, the fifth NMOS transistor TN5 and the sixth NMOS transistor TN6 are all doped with N-type ions, i.e., N + source electrodes.

The first control signal C1 and the second control signal C2 are complementary voltage control signals, that is, when the first control signal C1 is at a high level, the second control signal C2 is at a low level, and conversely, when the first control signal C1 is at a low level, the second control signal C2 is at a high level.

In detail, when the first control signal C1 is at a high level, no matter how the input analog signal of the input end Vi changes, the first PMOS transistor TP1, the second PMOS transistor TP2, the third PMOS transistor TP3, the fourth PMOS transistor TP4, and the fifth PMOS transistor TP5 are not turned on, that is, turned off, and the sixth NMOS transistor TN6 is turned on; similarly, when the second control signal C2 is at a low level, no matter how the input analog signal of the input end Vi changes, the first NMOS transistor TN1, the second NMOS transistor TN2, the third NMOS transistor TN3, the fourth NMOS transistor TN4, and the fifth NMOS transistor TN5 are not turned on, that is, turned off, and the sixth PMOS transistor TP6 is turned on.

When the first control signal C1 is at a low level, the second control signal C2 is at a high level, and in the variation range of the input analog signal of the input end Vi, the first PMOS transistor TP1, the second PMOS transistor TP2, the third PMOS transistor TP3, the fourth PMOS transistor TP4, the fifth PMOS transistor TP5, the first NMOS transistor TN1, the second NMOS transistor TN2, the third NMOS transistor TN3, the fourth NMOS transistor TN4, and the fifth NMOS transistor TN5 are all turned on, and the sixth NMOS transistor TN6 and the sixth PMOS transistor TP6 are all turned off.

The analog switch has two states, which are on and off, respectively.

When the first control signal C1 is at a high level and the second control signal C2 is at a low level, the analog switch is turned off. At this time, the first PMOS transistor TP1, the second PMOS transistor TP2, the third PMOS transistor TP3, the fourth PMOS transistor TP4, the fifth PMOS transistor TP5, the first NMOS transistor TN1, the second NMOS transistor TN2, the third NMOS transistor TN3, the fourth NMOS transistor TN4, and the fifth NMOS transistor TN5 are all turned off, and the sixth NMOS transistor TN6 and the sixth PMOS transistor TP6 are all turned on.

In detail, when the first control signal C1 is at a high level and the second control signal C2 is at a low level, the sixth PMOS transistor TP6 is turned on, and the substrate of the first PMOS transistor TP1, the substrate of the second PMOS transistor TP2, and the substrate of the third PMOS transistor TP3 are all pulled up to the voltage VCC through the sixth PMOS transistor TP6 (i.e., the substrates of the first PMOS transistor TP1, the second PMOS transistor TP2, and the third PMOS transistor TP3 are all set at a high level), so that the substrate voltage of the first PMOS transistor TP1 is the highest among the source, the drain, the gate, and the substrate of the first PMOS transistor TP1, the substrate voltage of the second PMOS transistor TP2 is the highest among the source, the drain, the gate, and the substrate of the second PMOS transistor TP2, and the substrate voltage of the third PMOS transistor TP3 is the highest, which can ensure that the first PMOS transistor TP1, the drain, the gate, and the substrate of the third PMOS transistor TP3 are all turned off completely.

When the analog circuit is turned off, because the fourth NMOS transistor TN4 and the fifth NMOS transistor TN5 are turned off, the N-terminal of the parasitic NP diode of the fourth NMOS transistor TN4 and the N-terminal of the parasitic NP diode of the fifth NMOS transistor TN5 are both connected to the first node P, and the voltage at the first node P is pulled up to the voltage VCC through the sixth PMOS transistor TP6, so that the parasitic NP diode of the fourth NMOS transistor TN4 and the parasitic NP diode of the fifth NMOS transistor TN5 are not turned on.

The sixth NMOS tube TN6 is turned on, the substrate of the first NMOS tube TN1, the substrate of the second NMOS tube TN2, and the substrate of the third NMOS tube TN3 are all pulled down to the ground GND through the sixth NMOS tube TN6 (i.e., the substrate of the first NMOS tube TN1, the substrate of the second NMOS tube TN2, and the substrate of the third NMOS tube TN3 are all set to a low level), the substrate voltage of the first NMOS tube TN1 is the lowest voltage among the source, the drain, the gate, and the substrate of the first NMOS tube TN1, the substrate voltage of the second NMOS tube TN2 is the lowest voltage among the source, the drain, the gate, and the substrate of the second NMOS tube TN2, and the substrate of the third NMOS tube TN3, and the substrate voltage is the lowest among the source, the drain, the gate, and the substrate of the third NMOS tube TN3, so that the substrate voltage of the first NMOS tube TN1, the second NMOS tube TN2, and the third NMOS tube TN3 can be ensured to be completely turned off, thereby solving the risk of electrical leakage at the input end of the NMOS tube TN.

When the analog circuit is turned off, the fourth PMOS tube TP4 and the fifth PMOS tube TP5 are turned off, so that the P end of a parasitic PN diode of the fourth PMOS tube TP4 and the P end of a parasitic PN diode of the fifth PMOS tube TP5 are both connected to a second node N, and the voltage at the second node N is pulled down to the ground GND through the sixth NMOS tube TN6, so that the parasitic PN diode of the fourth PMOS tube TP4 and the parasitic PN diode of the fifth PMOS tube TP5 are not conducted.

When the first control signal C1 is at a low level, the second control signal C2 is at a high level, and the analog switch is turned on. At this time, the substrate of the third PMOS transistor TP3 is connected to the first node P1, and the on-potential at the first node P is determined through the first PMOS transistor TP1, the second PMOS transistor TP2, the fourth NMOS transistor TN4, and the fifth NMOS transistor TN5, thereby solving the problem of the third PMOS transistor TP3 caused by the substrate bias effect; the substrate of the third NMOS transistor TN3 is connected to the second node N, and the on-potential of the second node N is determined by the first NMOS transistor TN1, the second NMOS transistor TN2, the fourth PMOS transistor TP4, and the fifth PMOS transistor TP5, thereby solving the problem of the third NMOS transistor TN3 caused by the substrate bias effect.

In this embodiment, when the input voltage of the input terminal Vi is at a low level (i.e., GND), since the on-potential at the first node P is determined by the first PMOS transistor TP1, the second PMOS transistor TP2, the fourth NMOS transistor TN4, and the fifth NMOS transistor TN5, the voltage at the first node P is also at a low level, the substrate of the third PMOS transistor TP3 is connected to the low level, and the output terminal Vout is turned on by the parasitic PN diode of the third PMOS transistor TP3, so that the analog switch is turned on quickly.

When the input voltage of the input end Vi is a high level (namely VCC), the on-state potential of the second node N is determined through the first NMOS transistor TN1, the second NMOS transistor TN2, the fourth PMOS transistor TP4, and the fifth PMOS transistor TP5, so that the substrate of the third NMOS transistor TN3 is connected to the high level, and the output end Vout is turned on through a parasitic NP diode of the third NMOS transistor TN3, thereby enabling the analog switch to be turned on quickly.

To sum up, the utility model provides an analog switch, through source electrode and substrate of first PMOS pipe, source electrode and substrate of second PMOS pipe, the substrate of third PMOS pipe, the source electrode of fourth NMOS pipe, the source electrode of fifth NMOS pipe and the drain electrode of sixth PMOS pipe connect at first node for first PMOS pipe, second PMOS pipe, fourth NMOS pipe, fifth NMOS pipe and sixth PMOS pipe constitute the bias circuit of third PMOS pipe; the source electrode and the substrate of the first NMOS tube, the source electrode and the substrate of the second NMOS tube, the substrate of the third NMOS tube, the source electrode and the substrate of the fourth PMOS tube, the source electrode and the substrate of the fifth PMOS tube and the drain electrode of the sixth NMOS tube are connected to a second node, so that the first NMOS tube, the second NMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth NMOS tube form a bias circuit of the third NMOS tube, and therefore the problems of electric leakage caused by crosstalk of the input end by the output end and generation of the third PMOS tube and the third NMOS tube due to a substrate bias effect are solved.

In addition, it should be noted that the description of the terms "first", "second", and the like in the specification is only used for distinguishing each component, element, step, and the like in the specification, and is not used for representing a logical relationship or a sequential relationship between each component, element, step, and the like, unless otherwise specified or indicated.

It is to be understood that while the present invention has been disclosed in terms of the preferred embodiment, it is not intended to limit the invention to the disclosed embodiment. To anyone skilled in the art, without departing from the scope of the present invention, the technical solution disclosed above can be used to make many possible variations and modifications to the technical solution of the present invention, or to modify equivalent embodiments with equivalent variations. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention all still fall within the protection scope of the technical solution of the present invention, where the technical entity does not depart from the content of the technical solution of the present invention.

Claims (9)

1. An analog switch is characterized by comprising a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein the analog switch is provided with an input end and an output end,

the source electrode and the substrate of the first PMOS tube, the source electrode and the substrate of the second PMOS tube, the substrate of the third PMOS tube, the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube and the drain electrode of the sixth PMOS tube are connected to a first node P, and the source electrode of the sixth PMOS tube is connected to a power supply; the source electrode and the substrate of the first NMOS transistor, the source electrode and the substrate of the second NMOS transistor, the substrate of the third NMOS transistor, the source electrode and the substrate of the fourth PMOS transistor, the source electrode and the substrate of the fifth PMOS transistor and the drain electrode of the sixth NMOS transistor are connected to a second node N, and the source electrode of the sixth NMOS transistor is grounded; the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth NMOS tube are all connected with a first control signal; the grid electrode of the first NMOS tube, the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube, the grid electrode of the fourth NMOS tube, the grid electrode of the fifth NMOS tube and the grid electrode of the sixth PMOS tube are all connected with a second control signal; the drain electrode of the first PMOS tube, the drain electrode and the substrate of the fourth NMOS tube, the drain electrode of the third PMOS tube, the drain electrode of the third NMOS tube, the drain electrode of the fourth PMOS tube and the drain electrode of the first NMOS tube are all connected with the input end; the drain electrode of the second PMOS tube, the drain electrode and the substrate of the fifth NMOS tube, the source electrode of the third PMOS tube, the source electrode of the third NMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the second NMOS tube are all connected with the output end.

2. The analog switch of claim 1,

when the first control signal is at a high level, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor are all turned off, and the sixth NMOS transistor is turned on; and

when the second control signal is at a low level, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are all turned off, and the sixth PMOS transistor is turned on.

3. The analog switch of claim 1, wherein when the first control signal is at a low level, the second control signal is at a high level, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are all turned on, and the sixth NMOS transistor and the sixth PMOS transistor are all turned off.

4. The analog switch of any of claims 1-3, wherein the analog switch is turned off when the first control signal is high and the second control signal is low.

5. The analog switch of claim 4, wherein when the analog switch is turned off, the sixth PMOS transistor is turned on, and the substrate of the first PMOS transistor, the substrate of the second PMOS transistor, and the substrate of the third PMOS transistor are all pulled up to the voltage of the power supply through the sixth PMOS transistor, so that the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor can all be completely turned off.

6. The analog switch of claim 4, wherein when the analog switch is turned off, the sixth NMOS transistor is turned on, and the substrate of the first NMOS transistor, the substrate of the second NMOS transistor, and the substrate of the third NMOS transistor are all pulled down to ground through the sixth NMOS transistor, so that the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor can all be turned off completely.

7. The analog switch of any of claims 1-3, wherein when the first control signal is low, the second control signal is high, and the analog switch is turned on.

8. The analog switch of claim 7, wherein when the analog switch is turned on, the substrate of the third PMOS transistor is connected to the first node, and the turn-on potential at the first node is determined by the first PMOS transistor, the second PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor.

9. The analog switch of claim 7, wherein when the analog switch is turned on, the substrate of the third NMOS transistor is connected to the second node, and the turn-on potential of the second node is determined by the first NMOS transistor, the second NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor.

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