CN218162988U - Wiring structure and equipment of gigabit network board card - Google Patents
Wiring structure and equipment of gigabit network board card Download PDFInfo
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- CN218162988U CN218162988U CN202221711778.XU CN202221711778U CN218162988U CN 218162988 U CN218162988 U CN 218162988U CN 202221711778 U CN202221711778 U CN 202221711778U CN 218162988 U CN218162988 U CN 218162988U
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Abstract
The utility model discloses a wiring structure and equipment of giga net integrated circuit board, wiring structure includes the PCB body, be provided with first routing layer on the PCB body, refer to the ground layer, power surface layer and second wiring layer group, first routing layer is located refers to the ground layer, the upper portion of power surface layer and second wiring layer group, all be provided with differential signal line pair on first routing layer and the second wiring layer group, two internal differential signal line's of differential signal line length is the same, including referring to the ground layer and not including the power surface layer in the electric current return path of each internal differential signal line of differential signal line, be provided with the clock signal line on the first routing layer, the both sides of clock signal line are around there being the ground copper region, set up the first ground hole of a plurality of in the ground copper region, be provided with data transmission signal line and data reception signal line on the second wiring layer group, and data transmission signal line and data reception signal line are located the different second wiring layer groups in the second wiring layer group.
Description
Technical Field
The utility model belongs to the technical field of the PCB wiring design, concretely relates to wiring structure and equipment of giga net integrated circuit board.
Background
At present, when wiring design is performed on a gigabit network board, the following is generally performed:
1. the data transmission signal line, the data receiving signal line and the clock signal line are wired on the same layer, however, the clock signal line comprises the wiring of the component crystal oscillator, and the component crystal oscillator is a high-frequency device in the gigabit network board card, so the clock line is easy to interfere with the lines such as the data transmission signal line and the data receiving signal line, meanwhile, the clock signal line is also easy to be interfered by the outside, and in addition, the data transmission signal line and the data receiving signal line are wired on the same layer, and the defect of mutual crosstalk exists.
2. When the differential wiring from the network port connector to the control chips such as the network port isolator and the like is wired, a complete ground plane is not referenced, because the EMC environment between the reference ground plane layer and the power supply plane layer is poor, and meanwhile, the differential wiring is sensitive to interference, so that the differential wiring is extremely easy to be interfered if the complete ground plane is not referenced.
The occurrence of the above interference causes the actual rate of signals in the traces to fall short of the rate requirement of the gigabit network.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome one or more of prior art not enough, provide a wiring structure and equipment of giga net integrated circuit board.
The purpose of the utility model is realized through the following technical scheme:
first aspect
The utility model provides a first aspect provides a wiring structure of giga net integrated circuit board, wiring structure includes the PCB body, the PCB body is used for being connected with outside network port connector and control chip electricity, be provided with first wiring layer, reference ground layer, power surface layer and second on the PCB body and route the bed set, first wiring layer is located the upper portion of referring to ground layer, power surface layer and second and routing the bed set, all be provided with the differential signal line pair that is used for communication transmission between network port connector and the control chip on first wiring layer and the second routing bed set, the length of two differential signal lines in the differential signal line pair is the same; each differential signal line in the differential signal line pair includes the reference ground plane layer in a current return path and does not include the power plane layer; a clock signal line is arranged on the first wiring layer, two sides of the clock signal line are surrounded by a ground copper area, and a plurality of first ground holes are formed in the ground copper area; and the second wiring layer group is provided with a data transmitting signal line and a data receiving signal line, and the data transmitting signal line and the data receiving signal line are positioned on different second wiring layers in the second wiring layer group.
In a further improvement, the number of the differential signal line pairs is four, the length of each differential signal line in the four differential signal line pairs is the same, and the characteristic impedance of each differential signal line pair is 100 ohms.
In a further improvement, the number of the data sending signal lines is multiple, a plurality of second ground holes are formed in a second wiring layer where the data sending signal lines are located, and the plurality of second ground holes surround the data sending signal lines.
In a further improvement, the number of the data receiving signal lines is multiple, a plurality of third ground holes are formed in a second wiring layer where the data receiving signal lines are located, and the plurality of third ground holes surround the data receiving signal lines.
In a further improvement, the length of each of the data transmission signal lines is the same.
In a further improvement, the length of each of the data receiving signal lines is the same.
In a further improvement, the characteristic impedance of the data transmission signal line and the characteristic impedance of the data reception signal line are both 50 ohms.
The first aspect brings the following beneficial effects:
(1) By independently laying the ground copper areas on two sides of the whole section of the clock signal line and forming a plurality of first ground holes in the ground copper areas, the ground covering punching isolation of the clock signal line is realized, and the interference to other signal lines on the PCB body is reduced; through the layered wiring of the data sending signal line and the data receiving signal line, the mutual crosstalk between the data sending signal line and the data receiving signal line is reduced; the two differential signal lines in the differential signal line pairs are arranged in equal length, and each differential signal line in the four differential signal line pairs is arranged in equal length, so that the whole section of characteristic impedance of the differential signal lines is kept at 100 ohms, good impedance matching is realized, a current return path of each differential signal line only comprises a reference ground layer and does not comprise a power supply surface layer, complete ground plane reference of the differential signal lines is realized, and the integrity of signals is kept;
in summary, the transmission rate of the signal line in the wiring structure achieved by the first aspect meets the requirement of gigabit network rate.
(2) Through the arrangement of a plurality of second ground holes around the data transmitting signal line and the arrangement of a plurality of third ground holes around the data receiving signal line, the anti-interference capacity of the data transmitting signal line and the data receiving signal line is improved, and therefore the transmission rate of the signal line is further guaranteed.
(3) Through the equal-length arrangement of the data transmission signal lines, 50-ohm characteristic impedance is kept on the whole section of the data transmission signal line, good impedance matching is achieved, and signal transmission is further guaranteed.
(4) Through the equal-length arrangement of each data receiving signal line, 50 ohm characteristic impedance is kept on the whole section of the data receiving signal line, good impedance matching is achieved, and signal transmission is further guaranteed.
Second aspect of the invention
A second aspect of the utility model provides an equipment, include the equipment body and install the inside giga net integrated circuit board of equipment body, giga net integrated circuit board includes the first aspect wiring structure, giga net integrated circuit board with the equipment body electricity is connected.
The beneficial effects brought by the second aspect are the same as those of the first aspect, and are not described herein again.
Drawings
FIG. 1 is a first portion (first routing layer) of a schematic of a routing structure;
fig. 2 is a second part of the wiring structure diagram (a second wiring layer a in the second wiring layer group);
fig. 3 is a third part of the wiring structure diagram (second wiring layer b in the second wiring layer group);
in the figure, 1, a clock signal line; 2. a copper region; 3. a first differential signal line pair; 4. a second differential signal line pair; 5. a third differential signal line pair; 6. a data transmission signal line; 7. a data receiving signal line; 8. a first ground hole; 9. a second ground hole; 10. and a third ground hole.
Detailed Description
The technical solution of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.
Example one
Referring to fig. 1 to 3, the present embodiment provides a wiring structure of a gigabit network board, including a PCB body, where the PCB body is used to electrically connect with an external network connector and a control chip. The PCB body is provided with a first wiring layer, a reference ground layer (not shown in the figure), a power supply surface layer (not shown in the figure) and a second wiring layer group. The first wiring layer is located on the reference ground layer, the power supply layer and the second wiring layer, and in the embodiment, the first wiring layer is located on the TOP surface of the PCB body. And the first wiring layer group and the second wiring layer group are respectively provided with a differential signal line pair for communication and transmission between the network port connector and the control chip. Wherein the lengths of the two differential signal lines within the differential signal line pair are the same. The current return path of each differential signal line within the pair of differential signal lines includes the reference ground plane and does not include the power supply plane. The current return path of each differential signal wire only flows through the reference ground layer and does not flow through the power supply surface layer, and the anti-interference capability of the differential signal wire is improved compared with the wiring design mode of simultaneously referring to the ground layer and the power supply surface layer by the wiring design of the reference complete ground plane while the signal integrity is ensured.
The number of differential signal line pairs in this embodiment is four. The lengths of the differential signal lines in the four pairs of differential signal line pairs are the same, and the length error is within 5 mil. The characteristic impedance of each of the four pairs of differential signal lines is 100 ohms.
As shown in fig. 1, a clock signal line 1 is disposed on the first wiring layer, two sides of the clock signal line 1 are surrounded by a ground copper area 2, and a plurality of first ground holes 8 are disposed in the ground copper area 2. The first differential signal line pair 3 of the differential signal line pair is located on the first wiring layer. The ground copper is independently laid on two sides of the whole section of the clock signal wire 1 to form a ground copper area 2, and a plurality of first ground holes 8 are formed in the ground copper area 2 to shield possible interference on the clock signal wire 1, wherein the possible interference includes interference from the inside of a wiring structure, such as interference of other signal wires, and interference from the outside of the wiring structure, such as interference of a gigabit network board installation environment, and meanwhile, interference of the clock signal wire 1 on other signal wires is also reduced.
As shown in fig. 2 and 3, the data transmission signal lines 6 and the data reception signal lines 7 are distributed on the second wiring layer group, and the data transmission signal lines 6 and the data reception signal lines 7 are located on different second wiring layers in the second wiring layer group, where the data transmission signal lines 6 are distributed on the second wiring layer b and the data reception signal lines 7 are distributed on the second wiring layer a. The second differential signal line pair 4 of the differential signal line pair is distributed on the second wiring layer a, the third differential signal line pair 5 of the differential signal line pair is distributed on the second wiring layer b, and the fourth differential signal line pair (not shown in the figure) of the differential signal line pair is distributed on the other second wiring layer.
The data transmission signal line 6 is a plurality of lines. The second wiring layer b is provided with a plurality of second ground holes 9, and the plurality of second ground holes 9 surround the plurality of data transmission signal lines 6. Through the setting of second ground hole 9, realize that many data send signal line 6 whole group's parcel ground, strengthened the interference killing feature of data send signal line 6.
The data receiving signal line 7 is also plural. The second wiring layer a is provided with a plurality of third ground holes 10, and the plurality of third ground holes 10 surround the plurality of data receiving signal lines 7. Through the arrangement of the third ground hole 10, the whole group of the data receiving signal lines 7 is wrapped, and the anti-interference capability of the data receiving signal lines 7 is enhanced.
Preferably, the length of each data transmission signal line 6 is the same, and the length error is within 10 mils. And, the characteristic impedance of each data transmission signal line 6 is 50 ohms.
Preferably, the length of each data receiving signal line 7 is the same, and the length error is within 10 mils. And, the characteristic impedance of each data receiving signal line 7 is 50 ohms.
Compared with the wiring structure of a gigabit network board card in the prior art, the wiring structure realized by the embodiment is optimally designed as follows: 1) On the basis of ensuring the short, straight and smooth length of the differential signal line, the differential signal line pair keeps 100 ohm characteristic impedance in the whole section; 2) Each data transmission signal line 6 and each data reception signal line 7 maintain 50 ohm characteristic impedance; 3) The data transmitting signal lines 6 and the data receiving signal lines 7 are designed in a layered mode, and meanwhile the whole group of the data transmitting signal lines 6 is subjected to ground covering, and the whole group of the data receiving signal lines 7 is subjected to ground covering; 4) Laying ground copper on two sides of the clock signal wire 1 to form a ground copper area 2, and punching ground holes on the ground copper area 2; 5) Each differential signal line is referenced to a complete ground plane. Through the optimization design, the problem that the signal rate does not reach the standard in the background technology is effectively solved.
Example two
This embodiment provides an equipment, including the equipment body with install at the inside giga net integrated circuit board of equipment body, giga net integrated circuit board is connected with the equipment body electricity. The gigabit network board includes the wiring structure in the first embodiment.
The foregoing is illustrative of the preferred embodiments of the present invention, and it is to be understood that the invention is not limited to the precise forms disclosed herein, and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the invention as defined by the appended claims. But that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A wiring structure of a gigabit network board card comprises a PCB body, wherein the PCB body is used for being electrically connected with an external network port connector and a control chip, and is characterized in that a first wiring layer, a reference ground layer, a power supply surface layer and a second wiring layer group are arranged on the PCB body, the first wiring layer is positioned at the upper parts of the reference ground layer, the power supply surface layer and the second wiring layer group, differential signal line pairs for communication transmission between the network port connector and the control chip are arranged on the first wiring layer and the second wiring layer group, and the lengths of two differential signal lines in the differential signal line pairs are the same; each differential signal line in the differential signal line pair includes the reference ground plane layer in a current return path and does not include the power supply ground plane layer; a clock signal line is arranged on the first wiring layer, two sides of the clock signal line are surrounded by a ground copper area, and a plurality of first ground holes are formed in the ground copper area; and the second wiring layer group is provided with a data transmitting signal line and a data receiving signal line, and the data transmitting signal line and the data receiving signal line are positioned on different second wiring layers in the second wiring layer group.
2. The wiring structure of a gigabit network board as claimed in claim 1, wherein the number of the differential signal line pairs is four, each of the differential signal lines in the four differential signal line pairs has the same length, and the characteristic impedance of each of the four differential signal line pairs is 100 ohms.
3. The routing structure of a gigabit network board as claimed in claim 1, wherein the number of the data transmission signal lines is multiple, a plurality of second ground vias are formed in a second routing layer where the plurality of data transmission signal lines are located, and the plurality of second ground vias surround the plurality of data transmission signal lines.
4. The wiring structure of a gigabit network board as claimed in claim 1, wherein the number of the data receiving signal lines is multiple, a plurality of third ground holes are formed in the second wiring layer where the plurality of data receiving signal lines are located, and the plurality of third ground holes surround the plurality of data receiving signal lines.
5. The wiring structure of a gigabit network board as claimed in claim 3, wherein each of the data transmission signal lines has the same length.
6. The wiring structure of a gigabit network board as claimed in claim 4, wherein each of the data receiving signal lines has the same length.
7. The wiring structure of a gigabit network board as claimed in claim 1, wherein the characteristic impedance of each of the data transmission signal line and the data reception signal line is 50 ohms.
8. An apparatus comprising an apparatus body and a gigabit network board mounted inside the apparatus body, the gigabit network board comprising the wiring structure according to any one of claims 1 to 7, the gigabit network board being electrically connected to the apparatus body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221711778.XU CN218162988U (en) | 2022-07-05 | 2022-07-05 | Wiring structure and equipment of gigabit network board card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221711778.XU CN218162988U (en) | 2022-07-05 | 2022-07-05 | Wiring structure and equipment of gigabit network board card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218162988U true CN218162988U (en) | 2022-12-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221711778.XU Active CN218162988U (en) | 2022-07-05 | 2022-07-05 | Wiring structure and equipment of gigabit network board card |
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| Country | Link |
|---|---|
| CN (1) | CN218162988U (en) |
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2022
- 2022-07-05 CN CN202221711778.XU patent/CN218162988U/en active Active
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