CN218160375U - Array substrate and display panel - Google Patents
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- CN218160375U CN218160375U CN202222572096.1U CN202222572096U CN218160375U CN 218160375 U CN218160375 U CN 218160375U CN 202222572096 U CN202222572096 U CN 202222572096U CN 218160375 U CN218160375 U CN 218160375U
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Abstract
The utility model provides an array substrate and display panel, this array substrate are used for display panel. The array substrate comprises a substrate, a first insulating layer, a planarization layer and a first electrode layer. The base includes a substrate and at least one protrusion on one side of the substrate. The first insulating layer is located on one side of the substrate having the protruding portion. The first insulating layer includes a first insulating portion and a second insulating portion. The second insulating part is a part of the insulating layer at least covering one side of the protruding part, which is far away from the substrate, in the first insulating layer. The first insulating part is another insulating layer except the second insulating part in the first insulating layer. A first distance between the surface of the first insulating part on the side departing from the substrate and the surface of the substrate on the side departing from the first insulating layer is not less than a second distance between the surface of the second insulating part on the side departing from the substrate and the surface of the substrate on the side departing from the first insulating layer. The utility model discloses the planarization of the surface that the planarization layer deviates from substrate one side has effectively been improved.
Description
Technical Field
The utility model relates to a show technical field, concretely relates to array substrate and display panel.
Background
With the development of display technologies, the requirements for performance of display panels such as luminance uniformity are increasing. The array substrate is an important structure in the display panel, and the flatness of the array substrate plays a very important role in the brightness uniformity of the display panel.
Therefore, how to improve the flatness of the array substrate is an urgent problem to be solved.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides an array substrate and display panel, the surface that deviates from substrate one side through the first insulation layer that sets up in the array substrate is flat or set up the recess with the position department that the bellying corresponds in the first insulation layer to improve or avoided the arch that produces because of the position department that corresponds that the existence of bellying leads to in the first insulation layer, effectively improved the degree of flatness that the planarization layer deviates from the surface of substrate one side, be favorable to improving or avoiding the poor problem of display panel light-emitting homogeneity because of array substrate's unevenness leads to.
The utility model discloses the first aspect provides an array substrate, and this array substrate is used for display panel. The array substrate comprises a substrate, a first insulating layer, a planarization layer and a first electrode layer. The base includes a substrate and at least one protrusion on one side of the substrate. The first insulating layer is located on one side of the substrate having the protruding portion. The first insulating layer includes a first insulating portion and a second insulating portion. The second insulating part is a part of insulating layer at least covering one side of the bulge part, which is far away from the substrate. The first insulating part is another insulating layer except the second insulating part in the first insulating layer. A first distance between the surface of the first insulating part on the side departing from the substrate and the surface of the substrate on the side departing from the first insulating layer is not less than a second distance between the surface of the second insulating part on the side departing from the substrate and the surface of the substrate on the side departing from the first insulating layer. The planarization layer is located on a side of the first insulating layer facing away from the substrate. The first electrode layer is located on one side of the planarization layer, which faces away from the first insulating layer.
In the above scheme, by setting the first distance equal to the second distance, the surface of the first insulating layer on the side away from the substrate is made flat. And forming a groove at a position corresponding to the second insulating part in the first insulating layer by setting the first distance to be larger than the second distance. Because the flattening effect of the flattening layer on the protrusion is smaller than the flattening effect of the groove or the flat surface, the flatness of the surface of the flattening layer, which is far away from the substrate, is effectively improved, the problem of poor light emitting uniformity of the display panel caused by the unevenness of the array substrate is also favorably improved or avoided, and the display quality of the graphic image displayed by the display panel is improved.
In a particular embodiment of the first aspect of the present invention, an orthographic projection of the protrusion on the substrate is located within an orthographic projection of the second insulation on the substrate; or the orthographic projection of the convex part on the substrate is superposed with the orthographic projection of the second insulating part on the substrate. In this way, the protrusion on the insulating layer caused by the protrusion is completely eliminated, and the unevenness of the array substrate caused by the protrusion is further improved.
In one embodiment of the first aspect of the present invention, the difference between the first distance and the second distance is not greater than a third distance between a surface of the projection facing away from the substrate and a surface of the projection facing toward the substrate. Therefore, the phenomenon that the new bulge is too thick due to too large offset is effectively avoided, and the integral flatness of the planarization layer is improved.
In one embodiment of the first aspect of the present invention, the difference between the first distance and the second distance is in a range of 0.2 μm to 0.3 μm. In this way, it is advantageously achieved with less material of the planarization layer that the surface of the planarization layer facing away from the substrate, which surface corresponds to the recess, is more flush with the adjacent surface.
In one embodiment of the first aspect of the present invention, the material of the planarization layer comprises an organic material. Therefore, the organic material is more prone to flowing to the groove in the natural leveling process, so that the organic material can be stacked after the groove is filled with the organic material, and the flatness of the surface of the planarization layer, which is away from one side of the substrate, can be further improved.
In one embodiment of the first aspect of the present invention, the first electrode layer includes a plurality of first electrodes. A gap exists between two adjacent first electrodes. The orthographic projection of the second insulating part on the substrate is positioned in the orthographic projection of the first electrode on the substrate, or the orthographic projection of the second insulating part on the substrate is superposed with the orthographic projection of the first electrode on the substrate. In this way, the flatness of the surface of the planarization layer on the side away from the substrate at the position corresponding to each second insulating portion is improved, and accordingly, the flatness of the surface of the first electrode on the side away from the substrate is improved.
In a particular embodiment of the first aspect of the invention, the first electrode is an anode. Therefore, the surface of the anode, which is far away from one side of the substrate, can be ensured to be smoother, so that the brightness uniformity of emergent light passing through the anode is improved.
In one embodiment of the first aspect of the present invention, the base includes a plurality of metal traces on one side of the substrate, and the protruding portion is formed by the metal traces. Therefore, the bulge generated by the metal routing in the insulating layer can be eliminated, and the unevenness caused by the metal routing in the planarization layer is improved or avoided.
In a specific embodiment of the first aspect of the present invention, the substrate further includes one or more of a buffer layer, a semiconductor layer, a second insulating layer, a gate electrode, a source electrode, a drain electrode, and a third insulating layer on one side of the substrate. The protruding portion is constituted by any one or more of the semiconductor layer, the second insulating layer, the gate electrode, the source electrode, the drain electrode, and the third insulating layer. In this way, the protrusion generated by any one or more of the semiconductor layer, the second insulating layer, the gate electrode, the source electrode, the drain electrode and the third insulating layer on the insulating layer can be eliminated, and the flatness of the surface of the planarization layer on the side away from the substrate is improved.
A second aspect of the present invention provides a display panel including a light-emitting layer, a second electrode layer, and an array substrate according to any one of the embodiments of the first aspect. The light emitting layer is located on one side, away from the substrate, of the first electrode layer in the array substrate. The second electrode layer is positioned on one side of the light-emitting layer, which is far away from the first electrode layer.
Drawings
Fig. 1 is a schematic top view of a display panel.
Fig. 2 is an enlarged cross-sectional view of the array substrate of the display panel shown in fig. 1, taken along the plane AA' in the region O.
Fig. 3 is an enlarged cross-sectional view of the array substrate of the display panel shown in fig. 1 taken along an AA' area in an O area according to an embodiment of the present invention.
Fig. 4 is an enlarged cross-sectional view of the array substrate of the display panel shown in fig. 1 taken along an area AA' in an O region according to another embodiment of the present invention.
Fig. 5 is an enlarged cross-sectional view of the array substrate of the display panel shown in fig. 1 taken along an AA' in an O-region according to another embodiment of the present invention.
Fig. 6 is an enlarged cross-sectional view of the array substrate of the display panel shown in fig. 1 taken along an AA' in an O-region according to still another embodiment of the present invention.
Fig. 7 is an enlarged cross-sectional view of the array substrate of the display panel shown in fig. 1 taken along an AA' in an O-region according to still another embodiment of the present invention.
Fig. 8 is an enlarged cross-sectional view of the display panel shown in fig. 1 taken along an area AA' in an area O according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts all belong to the protection scope of the present invention.
With the development of display technologies, the demand for display performance of display panels, such as luminance uniformity, is increasing. The human eye is generally less sensitive to brighter light variations, and the visual perception is less obvious or even may not be felt necessarily for smaller brightness non-uniformities, which to a certain extent will seriously affect the display quality of the graphic images displayed by the display panel.
In order to ensure the brightness uniformity of the display panel, it is generally required that each film layer in the display panel, such as the anode, the light-emitting layer and the cathode, is maintained on the same plane with high flatness, which puts higher demands on the flatness of the array substrate. However, due to design limitations of the existing array substrate such as its own material, structure and manufacturing process, the surface of the array substrate is very easy to be uneven, so that the brightness of the graphic image displayed by the display panel is easily uneven, and the display effect of the display panel is seriously affected.
Referring to fig. 1, the display panel 10 has a display area M and a wiring area N. The display region M is divided into a plurality of sub-pixel regions 1 and a non-sub-pixel region 2 located between two adjacent sub-pixel regions 1.
Note that the display area M is used to display an image. The wiring region N is used for signal lines for applying signals to the display region M. The sub-pixel region 1 may be a region corresponding to a sub-pixel in the display panel 10. The sub-pixel may include at least an anode, a light emitting layer, and a cathode. The non-subpixel region 2 may be a region between any adjacent two subpixels. The division of the display area M and the wiring area N in fig. 1 is only exemplary, and may be adaptively adjusted according to actual requirements. The area O may be any local area within the display area M, and is not limited to the position and shape shown in fig. 1.
Referring to fig. 2, the array substrate 100 generally includes a base 110, an insulating layer 120, a planarization layer 130, and an electrode layer 140, which are sequentially stacked. As a result of careful research, it is found that the surface roughness of the array substrate 100 is caused by a region design, such as metal traces and thin film transistors, in the substrate 110 of the array substrate 100, so that when each film layer, such as the insulating layer 120, the planarization layer 130, and the electrode layer 140, is formed on the substrate 110, each film layer is easily protruded at a position corresponding to the region design structure, for example, a protrusion a is generated at a corresponding position in the insulating layer 120 due to the existence of a protrusion in the substrate 110. In addition, although the planarization layer 130 in the array substrate 100 is designed to be planarized, due to the process variation, a step exists between the position of the planarization layer 130 corresponding to the designed structure and the peripheral position, so that a portion of the planarization layer 130 corresponding to the designed structure protrudes, for example, the thickness of the protruding portion is about 0.2 μm to 1.2 μm, thereby causing the planarization layer 130 to be uneven, and easily causing the surface of the array substrate 110 (for example, the surface of the electrode layer 140 facing away from the planarization layer 130) to be uneven. When light such as light generated by the display panel or light irradiated by an external environment is incident on the array substrate 110, due to the existence of the uneven surface, the light is reflected by the array substrate 110 and then has differences in different directions, so that the light emitting uniformity and the brightness of the display panel are easily poor and uneven, and the display quality of a graphic image displayed by the display panel is seriously affected.
In one case, the planarization layer 130 is usually polished to improve the planarization of the planarization layer 130, however, the polishing agent is inevitably remained during the polishing process, and the polishing agent is generally acidic or alkaline, and thus may corrode the array substrate to a certain extent, and affect the characteristics of the thin film transistors in the array substrate.
In order to solve at least one of the above problems, at least one embodiment of the present invention provides an array substrate and a display panel. The surface of one side of the first insulating layer, which is deviated from the substrate, in the array substrate is flat or the position, which corresponds to the protruding part, in the first insulating layer is provided with the groove, so that the protrusion, which is generated at the corresponding position caused by the protruding part in the first insulating layer, is improved or avoided, the flatness of the surface, which is deviated from one side of the substrate, of the flattening layer is effectively improved, the flatness of the array substrate is improved, the problem of poor light emitting uniformity of the display panel caused by the unevenness of the array substrate is favorably improved or avoided, and the display quality of graphic images displayed by the display panel is improved.
Next, an array substrate and a display panel according to at least one embodiment of the present invention will be described with reference to the accompanying drawings. In addition, in the drawings, a spatial rectangular coordinate system in which the X axis and the Y axis are parallel to the plane of the substrate and the Z axis is perpendicular to the plane of the substrate is established with reference to the substrate in the array substrate to assist in explaining the positional relationship of the respective structures in the array substrate. In addition, in the embodiment of the present invention, the "length" is defined in a direction parallel to the X axis, for example, the difference between the linear distances of the two end points of the object which are farthest from each other in the direction parallel to the X axis is the length of the object; and defines "thickness" in a direction parallel to the Z-axis, for example, the difference between the linear distances of the two end points of the object that are farthest away in the direction parallel to the Z-axis is the thickness of the object. For a groove, the depth of the groove corresponds to the thickness of the object filling the groove.
Referring to fig. 3 to 7, the array substrate 200 includes a base 210, a first insulating layer 220, a planarization layer 230, and a first electrode layer 240. The base 210 includes a substrate 211 and at least one protrusion 219 on one side of the substrate 211. The first insulating layer 220 is located on the side of the substrate 211 having the convex portion 219. The first insulating layer 220 includes a first insulating portion 221 and a second insulating portion 222 corresponding to the protrusion 219. The second insulating part 222 covers at least the back of the protruding part 219A portion of the insulating layer on the side away from the substrate 211. The first insulating portion 221 is another part of the first insulating layer 220 except for the second insulating portion 222. A first distance D between a surface of the first insulating portion 221 on a side facing away from the substrate 211 and a surface of the substrate 211 on a side facing away from the first insulating layer 220 1 Not less than a second distance D between a surface of the second insulating portion 222 on a side facing away from the substrate 211 and a surface of the substrate 211 on a side facing away from the first insulating layer 220 2 . The planarization layer 230 is located on a side of the first insulating layer 220 facing away from the substrate 211. The first electrode layer 240 is located on a side of the planarization layer 230 facing away from the first insulating layer 220. Thus, by setting D 1 Is equal to D 2 The protrusion a generated by the protrusion 219 in the insulating layer 120 is eliminated and no new protrusion is generated, so that the surface of the first insulating portion 221 facing away from the substrate 211 is flush with the surface of the second insulating portion 222 facing away from the substrate 211, and the flatness of the surface of the first insulating layer 220 facing away from the substrate 211 is improved, and further, the flatness of the surface of the planarization layer 230 facing away from the substrate 211 and the flatness of the surface of the first electrode layer 240 facing away from the substrate 211 are improved. By setting D 1 Greater than D 2 Therefore, while the protrusion a of the insulating layer 120 caused by the protrusion 219 is eliminated, a gap exists between the surface of the first insulating portion 221 facing away from the substrate 211 and the surface of the second insulating portion 222 facing away from the substrate 211, so that a groove is formed in the first insulating layer 220 at a position corresponding to the second insulating portion 222, the flattening effect of the flattening layer 230 on the protrusion is smaller than the flattening effect of the flattening layer on the groove, and the larger the flattening effect is, the flatter the surface of the flattening layer 230 facing away from the substrate is, so that when the protrusion a of the insulating layer 120 caused by the protrusion 219 is eliminated by using a process such as etching, the flatness of the surface of the flattening layer 230 facing away from the substrate 211 can be improved without a high process precision requirement. Based on this, the embodiment of the utility model provides a can effectively improve array substrate 200's in sub-pixel region 1 and/or the non-sub-pixel region 2 flatness, can sparingly polish the processing technology that grinds the paper-back edition to planarization layer 230, avoided the influence of polishing agent to thin film transistor characteristic, and be favorable to improving or avoid display panel because of the arrayThe unevenness of the substrate 200 causes a problem of poor uniformity of light emission, thereby improving the display quality of a graphic image displayed on the display panel.
Note that the planarization layer 230 may be in direct contact with the first electrode layer 240, and other film layers such as a reflective layer may also be present between the planarization layer 230 and the first electrode layer 240. The first electrode layer 240 may have a light-reflecting property or a light-transmitting property. If the first electrode layer 240 has light transmittance, a reflective layer may be disposed between the planarization layer 230 and the first electrode layer 240. The protruding portion 219 may be located in the sub-pixel region 1, may be located in the non-sub-pixel region 2, or may be located in both the sub-pixel region 1 and the non-sub-pixel region 2.
The material of the first insulating layer 220 may be any one or more of an organic material and an inorganic material, for example, the organic material may be an organic paste, and the inorganic material may be silicon nitride, silicon oxide, silicon oxynitride, or the like. The first insulating layer 220 may have an insulating function and may further have a function of protecting the substrate 210, and accordingly, the first insulating layer 220 may also be referred to as a protective layer.
D 1 As long as it is not less than D 2 That is, on this basis, the embodiment of the present invention does not specifically limit the preparation manner of the first insulating portion 221 and the second insulating portion 222. For example, in some embodiments, the first insulating portion 221 and the second insulating portion 222 may be respectively prepared by using masks. For another example, in other embodiments, a whole insulating layer 120 may be prepared by depositing or coating, and then performing an etching process such as micro etching or micro half etching on a protrusion a of the insulating layer 120, where the protrusion is generated due to the existence of the protrusion, and the depth of the micro etching is not less than the thickness of the protrusion a, so that the surface of the etched portion of the first insulating layer 220 facing away from the substrate 211 is flush with or slightly lower than the surface of the adjacent un-etched portion facing away from the substrate 211, and then the etched portion of the first insulating layer 220 is classified as the second insulating portion 222, and the un-micro-etched portion of the first insulating layer 220 is classified as the first insulating portion 221.
The second insulating portion 222 may be a part of the first insulating layer 220 that covers a side of the protruding portion 219 away from the substrate 211, or may be a part of the first insulating layer 220 that covers a side of the protruding portion 219 away from the substrate 211 and covers at least one side surface adjacent to a surface of the protruding portion 219 away from the substrate 211. Each second insulating portion 222 may cover a surface of one protruding portion 219 on a side away from the substrate 211 (refer to fig. 3 to 5), or may cover a surface of a plurality of protruding portions 219 on a side away from the substrate 211 (refer to fig. 6 and 7).
Each sub-pixel region 1 may have one convex portion 219 (see fig. 3 to 6) or may have a plurality of convex portions 219 (see fig. 7). The protruding portion 219 may be formed of a structure that is generally designed locally, such as a metal trace and a thin film transistor, or may be caused by an error in a manufacturing process. The structural design of the protruding portion 219 and the relationship between the protruding portion 219 and other film layers in the array substrate 200, such as the second insulating portion 222 and the first electrode layer 240, will be described with reference to several embodiments.
In the array substrate 200 provided by at least one embodiment of the present invention, an orthographic projection of the protruding portion 219 on the substrate 211 is located within an orthographic projection of the second insulating portion 222 on the substrate 211, or the orthographic projection of the protruding portion 219 on the substrate 211 coincides with an orthographic projection of the second insulating portion 222 on the substrate 211. In this way, the second insulating part 222 can completely cover the whole surface of the side of the protruding part 219 facing away from the substrate 211, so that the protrusion a on the insulating layer 120 caused by the protruding part 219 is completely eliminated, and the unevenness of the array substrate 200 caused by the protruding part 219 is further improved.
It should be noted that, taking the length as an example, for an orthogonal projection of the protruding portion 219 on the substrate 211 is located in an orthogonal projection of the second insulating portion 222 on the substrate 211, exemplarily referring to fig. 5 to 7, the length L of the protruding portion 219 is 1 Is smaller than the length L of the second insulating portion 222 2 . If the orthographic projection of the protruding part 219 on the substrate 211 coincides with the orthographic projection of the second insulating part 222 on the substrate 211, taking the length as an example, exemplarily referring to fig. 3 and 4, the length L of the protruding part 219 1 Equal to the second maximumLength L of edge 222 2 。
In the array substrate 200 provided by at least one embodiment of the present invention, the first distance D 1 At a second distance D 2 The difference therebetween is not larger than a third distance D between a surface of the convex portion 219 on a side facing away from the substrate 211 and a surface of the convex portion 219 on a side facing the substrate 211 3 . Thus, by adding D 1 And D 2 The difference therebetween is defined as not more than D 3 So that a step difference existing between a surface of the first insulating portion 221 on a side away from the substrate 211 and a surface of the second insulating portion 222 on a side away from the substrate 211 can be made smaller than or equal to a thickness of the convex portion 219 (that is, the third distance D) 3 ) The problem that the new bump is too thick due to too large step is effectively avoided, and the overall flatness of the planarization layer 230 is improved. In addition, even if the step difference is too large, new bumps are not located at the corresponding positions of the regionalized structures such as metal traces and thin film transistors, and therefore, the light emitting uniformity of the display panel is not affected.
In the array substrate 200 provided by at least one embodiment of the present invention, the first distance D 1 And a second distance D 2 The difference between them ranges from 0.2 μm to 0.3 μm. In this way, by providing the groove in the first insulating layer 220 at the position corresponding to the protruding portion 219, and defining the depth of the groove in a smaller range of 0.2 μm to 0.3 μm, the material of the planarization layer 230 can fill the groove earlier, which is beneficial for using less material of the planarization layer 230 to achieve that the surface of the planarization layer 230 on the side away from the substrate 211 corresponding to the groove is more flush with the adjacent surface. The material of the planarization layer 230 may be one or more of an organic material and an inorganic material, as long as the planarization function can be achieved, and on this basis, the embodiment of the present invention does not specifically limit the material of the planarization layer 230. Next, the material of the planarization layer 230 is described as an example of an organic material.
In the array substrate 200 provided by at least one embodiment of the present invention, the material of the planarization layer 230 includes an organic material, for example, the planarization layer 230 may be made of an organic materialLeveling and curing the mixture. Thus, at D 1 Greater than D 2 In the meantime, a groove is formed at a position corresponding to the second insulating portion 222 in the first insulating layer 220, and since the organic material tends to flow toward the groove in the process of natural leveling, the organic material is stacked after the groove is filled with the organic material, which is beneficial to further improving the flatness of the surface of the planarization layer 230 away from the substrate 211.
It should be noted that, with reference to fig. 2, in the sub-pixel region 1, the protrusion a is generated at the corresponding position of the insulating layer 120 due to the existence of the protrusion, and even if the material of the planarization layer 130 is an organic material, the organic material firstly covers the surface of the protrusion a and then flows to the peripheral groove, so that the planarization layer 130 in the sub-pixel region 1 is easily protruded at the corresponding position of the protrusion a. In contrast, the embodiment of the present invention utilizes the natural leveling of the organic material to planarize and solidify, thereby effectively improving the flatness of the surface of the planarization layer 230 on the side away from the substrate 211 in the sub-pixel region 1.
The first electrode layer 240 may be a single electrode layer (see fig. 3), or may be formed of a plurality of first electrodes (see fig. 4 to 7). Next, the structural design of the first electrode layer 240 is illustrated with reference to specific embodiments.
In the array substrate 200 provided by at least one embodiment of the present invention, the first electrode layer 240 includes a plurality of first electrodes 241 located in the plurality of sub-pixel regions 1. A gap exists between two adjacent first electrodes 241. An orthogonal projection of the second insulating portion 222 on the substrate 211 is located within an orthogonal projection of the first electrode 241 on the substrate 211, or an orthogonal projection of the second insulating portion 222 on the substrate 211 coincides with an orthogonal projection of the first electrode 241 on the substrate 211. Thus, the flatness of the surface of the planarization layer 230 on the side away from the substrate 211, which corresponds to the second insulating portion 222, can be effectively improved, and the flatness of the surface of the first electrode 241 on the side away from the substrate 211 can be further improved.
Note that, if the orthographic projection of the second insulating portion 222 on the substrate 211 is positioned on the orthographic projection of the first electrode 241 on the substrate 211In the shadow, taking the length as an example, exemplarily referring to fig. 4, the length L of the second insulating portion 222 2 Is less than the length L of the first electrode 241 4 . Taking the length as an example, referring to fig. 7, if the orthographic projection of the second insulating portion 222 on the substrate 211 coincides with the orthographic projection of the first electrode 241 on the substrate 211, the length L of the second insulating portion 222 is 2 Is equal to the length L of the first electrode 241 4 。
In some embodiments, an orthographic projection of the second insulating portion 222 on the substrate 211 is within an orthographic projection of the first electrode 241 and an adjacent gap on the substrate 211. In this way, since the surface of the second insulating portion 222 at the corresponding position of each first electrode 241 on the side facing away from the substrate 211 is flush with the surface of the adjacent first insulating portion 221 on the side facing away from the substrate 211, or a groove is formed in the first insulating layer 220 on the surface of the second insulating portion 222 on the side facing away from the substrate 211, the flatness of the surface of the planarization layer 230 on the side facing away from the substrate 211 at the corresponding position of each second insulating portion 222 is improved, and accordingly, the flatness of the surface of the first electrode 241 on the side facing away from the substrate 211 is improved.
It should be noted that an orthographic projection of the second insulating portion 222 on the substrate 211 is located in an orthographic projection of the first electrode 241 and an adjacent gap on the substrate 211, and by taking a length as an example, referring to fig. 4, 5 and 7, a length L of the second insulating portion 222 is illustrated 2 Is less than the length L of the first electrode 241 and the adjacent gap 3 。
In the array substrate 200 according to at least one embodiment of the present invention, the first electrode 241 is an anode. Thus, on the basis of improving the flatness of the surface of the planarization layer 230 on the side away from the substrate 211, when the anode is prepared by deposition or the like, the surface of the anode on the side away from the substrate 211 can be ensured to be smoother, so that the uniformity of the brightness of light emitted through the anode is improved.
In the array substrate 200 provided by at least one embodiment of the present invention, the base 210 includes a plurality of metal traces on one side of the substrate 211. The bump 219 is formed by a metal trace. Thus, the protrusion a of the insulating layer 120 caused by the metal trace can be eliminated, and the unevenness of the planarization layer 230 caused by the metal trace can be improved or avoided.
It should be noted that the metal trace may be a power trace, or may be a connection line between films or devices.
In the array substrate 200 according to at least one embodiment of the present invention, the substrate 210 further includes one or more of a buffer layer 212, a semiconductor layer 213, a second insulating layer 214, a gate electrode 215, a source electrode 216, a drain electrode 217, and a third insulating layer 218 on one side of the substrate 211, and the protrusion 219 is formed of one or more of the semiconductor layer 213, the second insulating layer 214, the gate electrode 215, the source electrode 216, the drain electrode 217, and the third insulating layer 218. Thus, it is possible to design D 1 Not less than D 2 The elimination of the protrusion on the insulating layer 120 caused by any one or more of the semiconductor layer 213, the second insulating layer 214, the gate electrode 215, the source electrode 216, the drain electrode 217, and the third insulating layer 218 improves the flatness of the surface of the planarization layer 230 on the side away from the substrate 211.
For example, referring to fig. 7, a buffer layer 212, a semiconductor layer 213, a second insulating layer 214, and a gate electrode 215 for protection may be sequentially formed on one side of a substrate 211. The semiconductor layer 213, the second insulating layer 214, the gate electrode 215, the source electrode 216, and the drain electrode 217 may collectively form a thin film transistor T. The buffer layer 212 may be a stacked film of silicon nitride and/or silicon oxide. The third insulating layer 218 may serve to insulate the upper and lower plates of the storage capacitor. The third insulating layer 218 may be the same layer as the first insulating layer 220, or may be a layer separate from the first insulating layer 220. For example, in some embodiments, the first insulating layer 220 may be a passivation layer, the second insulating layer 214 may be a gate insulating layer, and the third insulating layer 218 may be an interlayer dielectric layer.
The protruding portion 219 may be formed by a portion of the source electrode 216 or the drain electrode 217 which protrudes into the third insulating layer 218 (see fig. 7), may be formed by a protruding portion of the third insulating layer 218 due to the regionalization of the semiconductor layer 213 or the gate electrode 215, or may be directly formed by one or more of the semiconductor layer 213, the second insulating layer 214, the gate electrode 215, the source electrode 216, and the drain electrode 217.
At least one embodiment of the present invention further provides a display panel 10, where the display panel 10 includes an array substrate 200, a light emitting layer 310, and a second electrode layer 320. The light emitting layer 310 is located on a side of the first electrode layer 240 in the array substrate 200 facing away from the substrate 211. The second electrode layer 320 is located at a side of the light emitting layer 310 facing away from the first electrode layer 240.
For example, referring to fig. 8, the array substrate 200 may be the array substrate in the embodiment shown in fig. 3, and it should be noted that the array substrate 200 may also be the array substrate in any embodiment, such as the embodiment shown in fig. 4 to 7, or the array substrate after being equivalently replaced or obviously modified based on any one of the array substrates in the embodiments shown in fig. 3 to 7.
It should be noted that the first electrode layer 240, the light emitting layer 310 and the second electrode layer 320 may collectively form one sub-pixel L. The orthographic projection of the protrusions 219 on the substrate 211 may be within the orthographic projection of the light emitting layer 310 on the substrate 211, or the orthographic projection of the protrusions 219 on the substrate 211 may coincide with the orthographic projection of the light emitting layer 310 on the substrate 211. The sub-pixel L may be a blue sub-pixel, a yellow sub-pixel, a green sub-pixel, a red sub-pixel, a white sub-pixel, or the like.
The display panel 10 in the embodiment of the present invention may be a flexible display panel, and may also be a rigid display panel. The display panel 10 may be applied to any product or component having a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, an e-book reader, a player, a laptop portable computer, a vehicle-mounted computer, a desktop computer, or a set-top box. In addition, the display panel 10 may further include any one or more of a pixel defining layer, a hole injection layer, a hole transport layer, an electron injection layer, an electron blocking layer, a hole blocking layer, and a touch layer according to actual needs.
Since the display panel 10 of the embodiment of the present invention includes all the technical solutions of the embodiments shown in fig. 3 to fig. 7, all the technical effects can be achieved at least, and are not described herein again.
For clarity, not all structures of the display panel are described. In order to realize the necessary functions of the display panel, those skilled in the art can set other structures according to the specific application scenario.
It should be noted that the combination of the features of the present invention is not limited to the combination described in the claims or the combination described in the specific embodiments of the present invention, and all the features described in the present invention can be freely combined or combined in any way unless contradictory to each other is generated.
The above description is only for the preferred embodiment of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalent replacements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An array substrate for a display panel, the array substrate comprising:
the device comprises a base, a first electrode and a second electrode, wherein the base comprises a substrate and at least one bulge part positioned on one side of the substrate;
the first insulating layer is positioned on one side of the substrate, which is provided with the protruding portion, and comprises a first insulating part and a second insulating part, wherein the second insulating part is a part of the first insulating layer, which at least covers one side of the protruding portion, which is far away from the substrate, the first insulating part is another part of the first insulating layer, which is not the second insulating part, a first distance between the surface of the first insulating part, which is far away from the substrate, and the surface of the substrate, which is far away from the first insulating layer is not smaller than a second distance between the surface of the second insulating part, which is far away from the substrate, and the surface of the substrate, which is far away from the first insulating layer;
the planarization layer is positioned on one side, away from the substrate, of the first insulating layer; and
and the first electrode layer is positioned on one side of the planarization layer, which is far away from the first insulating layer.
2. The array substrate of claim 1,
the orthographic projection of the convex part on the substrate is positioned in the orthographic projection of the second insulating part on the substrate; or alternatively
An orthographic projection of the convex part on the substrate is superposed with an orthographic projection of the second insulating part on the substrate.
3. The array substrate of claim 1,
the difference between the first distance and the second distance is not greater than a third distance between a surface of the projection portion facing away from the substrate and a surface of the projection portion facing toward the substrate.
4. The array substrate of claim 1,
the difference between the first distance and the second distance ranges from 0.2 μm to 0.3 μm.
5. The array substrate of claim 1,
the material of the planarization layer includes an organic material.
6. The array substrate according to any one of claims 1 to 5,
the first electrode layer comprises a plurality of first electrodes, and a gap exists between every two adjacent first electrodes;
wherein an orthographic projection of the second insulating part on the substrate is positioned within an orthographic projection of the first electrode on the substrate; or
An orthographic projection of the second insulating portion on the substrate coincides with an orthographic projection of the first electrode on the substrate.
7. The array substrate of claim 6,
the first electrode is an anode.
8. The array substrate according to any one of claims 1 to 5,
the base comprises a plurality of metal wires positioned on one side of the substrate, and the protruding part is formed by the metal wires.
9. The array substrate according to any one of claims 1 to 5,
the base further includes one or more of a buffer layer, a semiconductor layer, a second insulating layer, a gate electrode, a source electrode, a drain electrode, and a third insulating layer on one side of the substrate,
the protruding portion is formed of any one or more of the semiconductor layer, the second insulating layer, the gate electrode, the source electrode, the drain electrode, and the third insulating layer.
10. A display panel, comprising:
an array substrate according to any one of claims 1 to 9;
the light-emitting layer is positioned on one side, away from the substrate, of the first electrode layer in the array substrate; and
and the second electrode layer is positioned on one side of the light-emitting layer, which is deviated from the first electrode layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222572096.1U CN218160375U (en) | 2022-09-27 | 2022-09-27 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222572096.1U CN218160375U (en) | 2022-09-27 | 2022-09-27 | Array substrate and display panel |
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| Publication Number | Publication Date |
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| CN218160375U true CN218160375U (en) | 2022-12-27 |
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| CN202222572096.1U Active CN218160375U (en) | 2022-09-27 | 2022-09-27 | Array substrate and display panel |
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