CN218159469U - Peripheral wiring structure and substrate - Google Patents
Peripheral wiring structure and substrate Download PDFInfo
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- CN218159469U CN218159469U CN202222216981.6U CN202222216981U CN218159469U CN 218159469 U CN218159469 U CN 218159469U CN 202222216981 U CN202222216981 U CN 202222216981U CN 218159469 U CN218159469 U CN 218159469U
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Abstract
The utility model discloses a line structure is walked to periphery, walk the line and walk the line with the second straight line including first straight line, first straight line walk the line with the second straight line is walked and is provided with the insulating layer between the line and be the turning setting, the insulating layer is including the overlapping region who sets up the via hole, first straight line walk the line with the second straight line is walked the line and is in the local overlap in the overlapping region, and pass through the via hole is connected. The peripheral wiring structure can solve the problem of uneven exposure at the corners of the wiring. The utility model also provides a base plate, walk the line structure including above-mentioned periphery.
Description
Technical Field
The utility model relates to a display technology especially relates to a line structure and base plate are walked to periphery.
Background
The chinese patent discloses a display screen, as shown in fig. 1, including a display area 1' and a peripheral area 2', a display circuit being arranged in the display area 1', a plurality of peripheral wires 21' being arranged in the peripheral area 2 '; a binding region 3' is further arranged in the peripheral region 2', a plurality of binding pins 31' are arranged in the binding region 3', and each peripheral wire 21' is connected between the display circuit and the corresponding binding pin 31' so as to transmit signals between the display circuit and the corresponding binding pin 31 '.
In the prior art, the peripheral trace 21' of the display screen is formed by a mask exposure etching method. When the wiring structure is manufactured, a layer of metal material is paved, a layer of photoresist is covered on the metal material, the photoresist is exposed by a mask plate with shading wiring patterns, the exposed area of the photoresist is subjected to material denaturation, the exposed area of the photoresist is removed by using a developing solution to partially expose the metal material of the lower layer, unexposed photoresist is left, the exposed metal material is etched by using an etching solution, the metal material below the exposed photoresist is protected by the left photoresist to form the peripheral wiring 21', and finally the rest photoresist is stripped.
Since the display area 1 'is much larger than the bonding area 3', the peripheral traces 21 'need corners when being routed, which causes the space between the peripheral traces 21' to change at the corners. When a mask plate is used for exposure, the difference of the wiring pitches can cause the difference of light diffraction degrees, so that the problem of uneven exposure of the peripheral wiring 21' at the corner can occur, and the problem of uneven line width of the etched peripheral wiring 21' at the corner can be caused, for example, the resistance of the peripheral wiring 21' is too large due to too small line width after etching, and further abnormal display is caused.
The technical problem also exists in the peripheral routing of the touch screen.
SUMMERY OF THE UTILITY MODEL
In order to solve the defects of the prior art, the utility model provides a line structure is walked to periphery can solve the inhomogeneous problem of exposure of walking line corner.
The utility model also provides a base plate, walk the line structure including above-mentioned periphery.
The utility model discloses the technical problem that will solve realizes through following technical scheme:
a peripheral wiring structure comprises a first linear wiring and a second linear wiring, wherein an insulating layer is arranged between the first linear wiring and the second linear wiring and is arranged in a corner, the insulating layer comprises an overlapping area provided with a via hole, and the first linear wiring and the second linear wiring are partially overlapped in the overlapping area and are connected through the via hole.
Further, the corner is greater than 0 ° and less than 180 °.
Further, the corner is 90 °.
A peripheral routing structure comprises a first straight line routing, a second straight line routing and a third straight line routing, wherein an insulating layer is arranged between the second straight line routing and the first straight line routing, the second straight line routing and the first straight line routing are arranged in a first corner mode, the second straight line routing and the third straight line routing are arranged in a second corner mode, the insulating layer comprises a first overlapping area with a first through hole and a second overlapping area with a second through hole, the first straight line routing and the second straight line routing are partially overlapped in the first overlapping area and are connected through the first through hole, and the partial area of the second straight line routing and the partial area of the third straight line routing are overlapped in the second overlapping area and are connected through the second through hole.
Further, the first and second corners are greater than 0 ° and less than 180 °.
Further, the first corner and the second corner are 90 °.
A peripheral wiring structure comprises a first linear wiring, a second linear wiring and a third linear wiring, wherein a first insulating layer is arranged between the first linear wiring and the second linear wiring and is arranged at a first corner, a second insulating layer is arranged between the second linear wiring and the third linear wiring and is arranged at a second corner, the first insulating layer comprises a first overlapping area provided with a first through hole, the first linear wiring and the second linear wiring are partially overlapped in the first overlapping area and are connected through the first through hole, the second insulating layer comprises a second overlapping area provided with a second through hole, and the second linear wiring and the third linear wiring are partially overlapped in the second overlapping area and are connected through the second through hole.
Further, the first and second corners are greater than 0 ° and less than 180 °.
Further, the first corner and the second corner are 90 °.
A substrate comprises a functional area and a peripheral area, wherein a binding area is arranged in the peripheral area; a plurality of peripheral wires are further arranged in the peripheral area, each peripheral wire is routed from the functional area to the peripheral area, and at least one peripheral wire adopts the peripheral wire structure; the signal transmission line comprises a functional area, a binding area and peripheral wiring, wherein a plurality of signal lines are arranged in the functional area, a plurality of binding pins are arranged in the binding area, and the peripheral wiring connects the corresponding signal lines with the binding pins.
The utility model discloses following beneficial effect has: according to the peripheral wiring structure, a peripheral wiring is divided into a first linear wiring and a second linear wiring at the corner, the first linear wiring and the second linear wiring are vertically staggered, different films are adopted for manufacturing, then the overlapped part between the first linear wiring and the second linear wiring is connected through a through hole on an insulating layer, and a complete peripheral wiring is formed.
Drawings
FIG. 1 is a schematic diagram of a conventional display screen;
fig. 2 is a schematic view of a peripheral wiring structure provided by the present invention;
fig. 3 is a schematic view of another peripheral wiring structure provided by the present invention;
fig. 4 is a schematic view of the direction of another peripheral wiring structure provided by the present invention;
fig. 5 is a cross-sectional view of the peripheral trace structure shown in fig. 2, 3 and 4;
fig. 6 is a schematic view of the direction of another peripheral wiring structure provided by the present invention;
fig. 7 is a schematic view of another peripheral wiring structure provided by the present invention;
fig. 8 is a schematic view of another peripheral wiring structure provided by the present invention;
fig. 9 is a cross-sectional view of the peripheral trace structure shown in fig. 6, 7 and 8;
fig. 10 is another cross-sectional view of the peripheral trace structure shown in fig. 6, 7 and 8;
fig. 11 is a schematic view of a substrate provided by the present invention.
Detailed Description
The invention is described in detail below with reference to the drawings and embodiments, examples of which are illustrated in the drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present invention, and should not be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the present invention and for simplicity in description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first", "second", "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and "disposed" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the interconnection of two elements or through the interaction of two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
Example one
2-5, an outer peripheral routing structure includes a first linear routing 11 and a second linear routing 12, where an insulating layer 13 is disposed between the first linear routing 11 and the second linear routing 12 and is disposed at a corner a, the insulating layer 13 includes an overlapping region 15 having a via hole 14, and the first linear routing 11 and the second linear routing 12 are partially overlapped in the overlapping region 15 and connected through the via hole 14.
According to the peripheral wiring structure, a peripheral wiring 1 is divided into a first linear wiring 11 and a second linear wiring 12 at the corner a, the first linear wiring 11 and the second linear wiring 12 are vertically staggered, the first linear wiring 11 and the second linear wiring 12 are manufactured by adopting different films, then the first linear wiring 11 and the second linear wiring 12 are connected through a via hole 14 in an insulating layer 13, and the complete peripheral wiring 1 is formed.
As shown in fig. 2 to 4, the first linear trace 11 and the second linear trace 12 can be routed either horizontally or vertically, or obliquely, so that the corner a is greater than 0 ° and less than 180 °, and most preferably, the corner a is 90 °.
The peripheral wiring structure comprises the following manufacturing steps:
depositing a first metal layer on a surface of a substrate base plate;
coating a first photoresist on the first metal layer, firstly, exposing the first photoresist by using a first mask plate, then, dissolving the exposed first photoresist by using a developing solution to leave a first photoresist pattern corresponding to the first linear trace 11, then, etching the first metal layer exposed from the first photoresist pattern by using an etching solution to form the first linear trace 11 on the first metal layer, and finally, stripping the first photoresist pattern;
depositing the insulating layer 13 on the first linear trace 11 and the surface of the substrate base plate;
coating a second photoresist on the insulating layer 13, firstly exposing the second photoresist by using a second mask plate, then dissolving the exposed second photoresist by using a developing solution to leave a second photoresist pattern exposing the position of the via hole 14 of the insulating layer 13, then etching the position of the via hole 14 exposing the insulating layer 13 by using an etching solution to form the via hole 14, and finally stripping the second photoresist pattern;
depositing the second metal layer on the insulating layer 13 and within the via 14;
coating a third photoresist on the second metal layer, firstly exposing the third photoresist by using a third mask plate, then dissolving the exposed third photoresist by using a developing solution to leave a third photoresist pattern corresponding to the second linear trace 12, then etching the second metal layer exposed from the third photoresist pattern by using an etching solution to form the second linear trace 12, connecting the second linear trace 12 with the first linear trace 11 through the via hole 14, and finally stripping the third photoresist pattern.
Example two
A peripheral trace structure, as shown in fig. 6-9, includes a first linear trace 11, a second linear trace 12, and a third linear trace 16, where an insulating layer 13 is disposed between the second linear trace 12 and the first linear trace 11 and the third linear trace 16, the second linear trace 12 and the first linear trace 11 are disposed at a first corner a1, the second linear trace 12 and the third linear trace 16 are disposed at a second corner a2, the insulating layer 13 includes a first overlapping area 15a having a first via hole 14a and a second overlapping area 15b having a second via hole 14b, the first linear trace 11 and the second linear trace 12 are partially overlapped in the first overlapping area 15a and are connected through the first via hole 14a, and a partial area of the second linear trace 12 and a partial area of the third linear trace 16 are overlapped in the second overlapping area 15b and are connected through the second via hole 14 b.
According to the peripheral routing structure, a peripheral routing 1 is divided into three sections of a first straight routing 11, a second straight routing 12 and a third straight routing 16 at a first corner a1 and a second corner a2 respectively, the first straight routing 11 and the second straight routing 12 are staggered up and down and are manufactured by adopting different films, the second straight routing 12 and the third straight routing 16 are staggered up and down and are manufactured by adopting different films, wherein the first straight routing 11 and the third straight routing 16 are manufactured by adopting the same film, then the first straight routing 11 and the second straight routing 12 are connected through a first through hole 14a on an insulating layer 13, the second straight routing 12 and the third straight routing 16 are connected through a second through hole 14b on the insulating layer 13 to form the complete peripheral routing 1, so that not only is the corner of the peripheral routing 1 realized, but also the problem that the first straight routing 11 and the second straight routing 12 forming the first corner a1 are staggered up and down and are positioned on different films, the second straight routing 12 and the third straight routing 12 forming the second corner a2 are not positioned on different films, and the mask is not subjected to exposure by adopting the single straight line 16, so that the mask is not uniform exposure process.
As shown in fig. 6 to 8, the first linear trace 11, the second linear trace 12 and the third linear trace 16 can be routed transversely, longitudinally or obliquely, so that the first corner a1 and the second corner a2 are greater than 0 ° and less than 180 °, and optimally, both the first corner a1 and the second corner a2 are 90 °.
The peripheral wiring structure comprises the following manufacturing steps:
depositing a first metal layer on a surface of a substrate base plate;
coating a first photoresist on the first metal layer, firstly exposing the first photoresist by using a first mask plate, then dissolving the exposed first photoresist by using a developing solution to leave a first photoresist pattern corresponding to the first linear traces 11 and the third linear traces 16, then etching the first metal layer exposed from the first photoresist pattern by using an etching solution to form the first linear traces 11 and the third linear traces 16 on the first metal layer, and finally stripping the first photoresist pattern;
depositing the insulating layer 13 on the first linear trace 11 and the surface of the substrate base plate;
coating a second photoresist on the insulating layer 13, firstly, exposing the second photoresist by using a second mask plate, then, dissolving the exposed second photoresist by using a developing solution to leave a second photoresist pattern exposing the first via hole 14a and the second via hole 14b of the insulating layer 13, then, etching the first via hole 14a and the second via hole 14b exposed on the insulating layer 13 by using an etching solution to form the first via hole 14a and the second via hole 14b, and finally, stripping the second photoresist pattern;
depositing the second metal layer on the insulating layer 13 and within the first and second vias 14a, 14 b;
coating a third photoresist on the second metal layer, firstly exposing the third photoresist by using a third mask plate, then dissolving the exposed third photoresist by using a developing solution to leave a third photoresist pattern corresponding to the second linear trace 12, then etching the second metal layer exposed from the third photoresist pattern by using an etching solution to form the second linear trace 12, connecting the second linear trace 12 with the first linear trace 11 and the third linear trace 16 through the first via hole 14a and the second via hole 14b, and finally stripping the third photoresist pattern.
EXAMPLE III
A peripheral trace structure, as shown in fig. 6-8 and 10, includes a first linear trace 11, a second linear trace 12 and a third linear trace 16, where a first insulating layer 13a is disposed between the first linear trace 11 and the second linear trace 12 and is disposed at a first corner a1, a second insulating layer 13b is disposed between the second linear trace 12 and the third linear trace 16 and is disposed at a second corner a2, the first insulating layer 13a includes a first overlapping area 15a having a first via hole 14a, the first linear trace 11 and the second linear trace 12 are partially overlapped in the first overlapping area 15a and are connected through the first via hole 14a, the second insulating layer 13b includes a second overlapping area 15b having a second via hole 14b, and the second linear trace 12 and the third linear trace 16 are partially overlapped in the second overlapping area 15b and are connected through the second via hole 14 b.
The peripheral wiring structure divides a peripheral wiring 1 into three sections of a first straight wiring 11, a second straight wiring 12 and a third straight wiring 16 at a first corner a1 and a second corner a2 respectively, staggers the first straight wiring 11 and the second straight wiring 12 up and down, adopts different film layers for manufacturing, staggers the second straight wiring 12 and the third straight wiring 16 up and down, adopts different film layers for manufacturing, wherein the first straight wiring 11 and the third straight wiring 16 are also manufactured by different film layers, and then connects the first straight wiring 11 and the second straight wiring 12 through a first through hole 14a on a first insulating layer 13a, and connecting the second linear trace 12 and the third linear trace 16 through the second via hole 14b on the second insulating layer 13b to form a complete peripheral trace 1, so that not only is the corner of the peripheral trace 1 realized, but also because the first linear trace 11 and the second linear trace 12 forming the first corner a1 are staggered up and down on different film layers, and the second linear trace 12 and the third linear trace 16 forming the second corner a2 are staggered up and down on different film layers, the trace in a single film layer has no corner, when the first linear trace 11, the second linear trace 12 and the third linear trace 16 are respectively manufactured by adopting a mask exposure etching method, the trace to be exposed only has a straight line, and the problem of uneven exposure cannot occur.
As shown in fig. 6 to 8, the first linear trace 11, the second linear trace 12 and the third linear trace 16 can be routed transversely, longitudinally or obliquely, so that the first corner a1 and the second corner a2 are greater than 0 ° and less than 180 °, and optimally, both the first corner a1 and the second corner a2 are 90 °.
The peripheral wiring structure comprises the following manufacturing steps:
depositing a first metal layer on a surface of a substrate base plate;
coating a first photoresist on the first metal layer, firstly, exposing the first photoresist by using a first mask plate, then, dissolving the exposed first photoresist by using a developing solution to leave a first photoresist pattern corresponding to the first linear trace 11, then, etching the first metal layer exposed from the first photoresist pattern by using an etching solution to form the first linear trace 11 on the first metal layer, and finally, stripping the first photoresist pattern;
depositing the first insulating layer 13a on the first linear trace 11 and the surface of the substrate base plate;
coating a second photoresist on the first insulating layer 13a, firstly exposing the second photoresist by using a second mask plate, then dissolving the exposed second photoresist by using a developing solution to leave a second photoresist pattern exposing the first via hole 14a of the first insulating layer 13a, then etching the exposed first via hole 14a of the first insulating layer 13a by using an etching solution to form the first via hole 14a, and finally stripping the second photoresist pattern;
depositing the second metal layer on the first insulating layer 13a and within the first via 14 a;
coating a third photoresist on the second metal layer, firstly exposing the third photoresist by using a third mask plate, then dissolving the exposed third photoresist by using a developing solution to leave a third photoresist pattern corresponding to the second linear trace 12, then etching the second metal layer exposed from the third photoresist pattern by using an etching solution to form the second linear trace 12 on the second metal layer, connecting the second linear trace 12 with the first linear trace 11 through the first via hole 14a, and finally stripping the third photoresist pattern;
depositing the second insulating layer 13b on the second linear trace 12 and the first insulating layer 13a;
coating a fourth photoresist on the second insulating layer 13b, firstly exposing the fourth photoresist by using a fourth mask plate, then dissolving the exposed fourth photoresist by using a developing solution to leave a fourth photoresist pattern exposing the second via hole 14b of the second insulating layer 13b, then etching the second via hole 14b exposing the second insulating layer 13b by using an etching solution to form the second via hole 14b, and stripping the fourth photoresist pattern;
depositing the third metal layer on the second insulating layer 13b and within the second via 14 b;
coating a fifth photoresist on the third metal layer, exposing the fifth photoresist by using a fifth mask plate, dissolving the exposed fifth photoresist by using a developing solution to leave a fifth photoresist pattern corresponding to the third linear trace 16, etching the third metal layer exposed from the fifth photoresist pattern by using an etching solution to form the third linear trace 16, connecting the third linear trace 16 with the second linear trace 12 through the second via hole 14b, and finally stripping the fifth photoresist pattern.
Example four
A substrate, as shown in fig. 11, includes a functional region 2 and a peripheral region 3, wherein a binding region 4 is disposed in the peripheral region 3; a plurality of peripheral wires 1 are further disposed in the peripheral area 3, each peripheral wire 1 is routed from the functional area 2 to the peripheral area 3, and at least one peripheral wire 1 adopts the peripheral wire structure described in the first embodiment, the second embodiment, or the third embodiment.
A plurality of signal lines (not shown in the figure) are arranged in the functional region 2, a plurality of binding pins 41 are arranged in the binding region 4, and each peripheral wiring 1 connects the corresponding signal line with the binding pin 41.
If the substrate is an array substrate, the signal lines are scanning signal lines or gray scale signal lines, and if the substrate is a touch substrate, the signal lines are detection signal lines or touch signal lines.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention and not for limiting the same, and although the embodiments of the present invention are described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the embodiments of the present invention can still be modified or replaced with equivalents, and these modifications or equivalent replacements cannot make the modified technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A peripheral routing structure is characterized by comprising a first linear routing line and a second linear routing line, wherein an insulating layer is arranged between the first linear routing line and the second linear routing line and is arranged in a corner mode, the insulating layer comprises an overlapping area with a through hole, and the first linear routing line and the second linear routing line are partially overlapped in the overlapping area and are connected through the through hole.
2. The peripheral routing structure of claim 1, wherein the corner is greater than 0 ° and less than 180 °.
3. The peripheral routing structure of claim 2, wherein the corner is 90 °.
4. A peripheral routing structure is characterized by comprising a first linear routing, a second linear routing and a third linear routing, wherein an insulating layer is arranged between the second linear routing and the first linear routing and between the second linear routing and the third linear routing, the second linear routing and the first linear routing are arranged in a first corner mode, the second linear routing and the third linear routing are arranged in a second corner mode, the insulating layer comprises a first overlapping area with a first through hole and a second overlapping area with a second through hole, the first linear routing and the second linear routing are partially overlapped in the first overlapping area and are connected through the first through hole, and the partial area of the second linear routing and the partial area of the third linear routing are overlapped in the second overlapping area and are connected through the second through hole.
5. The peripheral routing structure of claim 4, wherein the first and second corners are greater than 0 ° and less than 180 °.
6. The peripheral routing structure of claim 5, wherein the first and second corners are 90 °.
7. A peripheral routing structure is characterized by comprising a first linear routing, a second linear routing and a third linear routing, wherein a first insulating layer is arranged between the first linear routing and the second linear routing and is arranged at a first corner, a second insulating layer is arranged between the second linear routing and the third linear routing and is arranged at a second corner, the first insulating layer comprises a first overlapping area provided with a first through hole, the first linear routing and the second linear routing are partially overlapped in the first overlapping area and are connected through the first through hole, the second insulating layer comprises a second overlapping area provided with a second through hole, and the second linear routing and the third linear routing are partially overlapped in the second overlapping area and are connected through the second through hole.
8. The peripheral routing structure of claim 7, wherein the first and second corners are greater than 0 ° and less than 180 °.
9. The peripheral routing structure of claim 7, wherein the first and second corners are 90 °.
10. The substrate is characterized by comprising a functional area and a peripheral area, wherein a binding area is arranged in the peripheral area; a plurality of peripheral wires are further arranged in the peripheral area, each peripheral wire is routed from the functional area to the peripheral area, and at least one peripheral wire adopts the peripheral wire structure of any one of claims 1 to 9; the signal transmission line comprises a functional area, a binding area and peripheral wiring, wherein a plurality of signal lines are arranged in the functional area, a plurality of binding pins are arranged in the binding area, and the peripheral wiring connects the corresponding signal lines with the binding pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222216981.6U CN218159469U (en) | 2022-08-22 | 2022-08-22 | Peripheral wiring structure and substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222216981.6U CN218159469U (en) | 2022-08-22 | 2022-08-22 | Peripheral wiring structure and substrate |
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| CN218159469U true CN218159469U (en) | 2022-12-27 |
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| CN202222216981.6U Active CN218159469U (en) | 2022-08-22 | 2022-08-22 | Peripheral wiring structure and substrate |
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| CN (1) | CN218159469U (en) |
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