CN218124547U - Surge impact prevention circuit and electronic equipment - Google Patents
Surge impact prevention circuit and electronic equipment Download PDFInfo
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- CN218124547U CN218124547U CN202221197472.7U CN202221197472U CN218124547U CN 218124547 U CN218124547 U CN 218124547U CN 202221197472 U CN202221197472 U CN 202221197472U CN 218124547 U CN218124547 U CN 218124547U
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Abstract
The utility model discloses a prevent surge impact circuit and electronic equipment, prevent surge impact circuit includes the live wire, the zero line, bus capacitor, PWM control circuit, the step-down circuit, rectification control circuit and rectifier bridge circuit, control circuit's first input is connected with the live wire, PWM control circuit's second input is connected with the zero line, the input and the current output part of PWM control circuit of step-down circuit are connected, the controlled terminal and the PWM control circuit's of step-down circuit control signal output part are connected, the output and the second end of bus capacitor of step-down circuit are connected, the sampling end and the PWM control circuit's of step-down circuit sampling end are connected, rectification control circuit's sampling end and live wire are connected, rectifier bridge circuit's first input and live wire are connected, rectifier bridge circuit's second input and zero line are connected, rectifier bridge circuit's output and bus capacitor's second end are connected. The technical problem that a buffer device is easily damaged by a charging scheme of a bus capacitor of an alternating-current input power supply in the prior art is solved.
Description
Technical Field
The utility model relates to a electrical power generating system technical field, in particular to prevent surge impact circuit and electronic equipment.
Background
In the prior art, an alternating current input power supply generally comprises a rectifier bridge and a large bus capacitor. When the power is on, the charging current of the bus capacitor needs to be limited so as to avoid overlarge surge impact current. The low power supply is typically connected in series with a negative temperature coefficient thermistor in the circuit. For a high-power supply, the thermistor has high power consumption, and a buffer resistor and a relay or a thyristor are generally connected in parallel. After the control circuit is electrified, the relay or the controlled silicon is closed to finish buffering after the bus voltage and the input alternating voltage meet the set buffering value. However, both of these methods have a technical problem that the buffer device is easily damaged.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a prevent surge impulse circuit and electronic equipment solves among the prior art technical problem that the buffer device is damaged easily to the charging scheme of the generating line electric capacity of alternating current input power.
In order to achieve the above object, the utility model provides a surge protection circuit, surge protection circuit includes:
the live wire is used for connecting a power supply;
a zero line;
a bus capacitor, a first end of the bus capacitor being connected to a load;
the PWM control circuit is provided with a first input end, a second input end, a current output end, a sampling input end and a control signal output end, wherein the first input end of the control circuit is connected with the live wire, the second input end of the PWM control circuit is connected with the zero line, and the PWM control circuit outputs a conducting signal when the power supply is larger than a first preset voltage value;
the input end of the voltage reduction circuit is connected with the current output end of the PWM control circuit, the controlled end of the voltage reduction circuit is connected with the control signal output end of the PWM control circuit, the output end of the voltage reduction circuit is connected with the second end of the bus capacitor, the sampling end of the voltage reduction circuit is connected with the sampling input end of the PWM control circuit, when the conduction signal is received, a path between the rectification circuit and the voltage reduction circuit is conducted, and the rectified power supply is output to the bus capacitor for charging after being subjected to voltage reduction;
the rectifier control circuit is provided with a sampling end, a first rectifier control signal end and a second rectifier control signal end, the sampling end of the rectifier control circuit is connected with the live wire, and a rectifier bridge conduction signal is output when the time for connecting the live wire to a power supply reaches a preset time length;
the rectifier bridge circuit is provided with a first input end, a second input end, a first controlled end, a second controlled end and an output end, the first input end of the rectifier bridge circuit is connected with the live wire, the second input end of the rectifier bridge circuit is connected with the zero line, the output end of the rectifier bridge circuit is connected with the second end of the bus capacitor, and the rectifier bridge circuit is conducted when receiving a rectifier bridge conduction signal so as to output the rectified power.
Optionally, the rectifier bridge circuit includes a first diode, a second diode, a first optocoupler, a second optocoupler, a first thyristor, a second thyristor, a first resistor, and a second resistor, a collector of the first optocoupler and an anode of the first thyristor are interconnected with a cathode of the first diode, a connection node of the first optocoupler is a first input end of the rectifier bridge circuit, and an emitter of the first optocoupler, a first end of the first resistor, and a control electrode of the first thyristor are interconnected; a collector of the second optocoupler and an anode of the second thyristor are interconnected with a cathode of the second diode, a connection node of the second optocoupler is a second input end of the rectifier bridge circuit, and an emitter of the second optocoupler, a first end of the second resistor and a control electrode of the second thyristor are interconnected; the cathode of the first controllable silicon, the second end of the first resistor, the cathode of the second controllable silicon and the second end of the second resistor are interconnected, and the connection node of the first controllable silicon, the second resistor and the second controllable silicon is the output end of the rectifier bridge circuit.
Optionally, the voltage reduction circuit includes a first switch tube, a first inductor and a third diode, a first end of the first switch tube is an input end of the voltage reduction circuit, a second end of the first switch tube is respectively interconnected with the first end of the first inductor and a cathode of the third diode, a connection node of the first switch tube is a sampling end of the voltage reduction circuit, a controlled end of the first switch tube is a controlled end of the voltage reduction circuit, a second end of the first inductor is an output end of the voltage reduction circuit, and an anode of the third diode is grounded.
Optionally, the PWM control circuit includes a rectifier module and a control module, the rectifier module has a first input, a second input and an output, the control module has an input, a sampling input and a control signal output, the first input of the rectifier module is the first input of the PWM control circuit, the second input of the rectifier module is the second input of the PWM control circuit, the output of the rectifier module is connected with the control signal output of the control module, the connection node is the current output of the PWM control circuit, the sampling input of the control module is the sampling input of the PWM control circuit, the control signal output of the control module is the control signal output of the PWM control circuit.
Optionally, the rectifier module includes a fourth diode, a fifth diode, and a third resistor, an anode of the fourth diode is a first input end of the rectifier module, and a cathode of the fourth diode is interconnected with a cathode of the fifth diode and a first end of the third resistor, respectively; the anode of the fifth diode is the second input end of the rectifying module, and the second end of the third resistor is the output end of the rectifying module.
Optionally, the surge impact prevention circuit further includes a follow current circuit, an input end of the follow current circuit is connected to an output end of the rectifier bridge circuit, and an output end of the follow current circuit is connected to the first end of the bus capacitor.
Optionally, the surge protection circuit further includes a sampling circuit, and the sampling circuit is disposed between the second end of the first switching tube and the cathode of the third diode.
In order to achieve the above object, the present invention further provides an electronic device including the surge protection circuit.
The utility model discloses a time of inserting the power at the live wire does not reach when predetermineeing the duration and is in when the power is greater than first predetermined magnitude of voltage, PWM control circuit direct control step-down circuit switches on rectifier circuit with route between the step-down circuit, and to the rectification after the power steps down the back and exports to bus-bar capacitance and charges. Therefore, initial constant-current charging can be achieved, when the time that the live wire is connected to the power supply reaches the preset time length, the rectifier control circuit outputs a rectifier bridge conduction signal, and the rectifier bridge circuit is conducted when receiving the rectifier bridge conduction signal so as to rectify and output the power supply. Because the voltage of the bus capacitor after being charged for a period of time is close to the rectified voltage, the rectifier bridge circuit does not generate surge impact current when starting to work. Therefore, the technical problem that a buffer device is easily damaged by a charging scheme of a bus capacitor of an alternating-current input power supply in the prior art can be solved.
Drawings
The present invention will be further described with reference to the accompanying drawings and examples;
fig. 1 is a block diagram of an anti-surge circuit according to an embodiment.
Fig. 2 is a circuit diagram of an anti-surge circuit in one embodiment.
Detailed Description
This section will describe in detail the embodiments of the present invention, preferred embodiments of the present invention are shown in the attached drawings, which are used to supplement the description of the text part of the specification with figures, so that one can intuitively and vividly understand each technical feature and the whole technical solution of the present invention, but they cannot be understood as the limitation of the protection scope of the present invention.
In order to solve the technical problem that the buffer device is damaged easily to the charging scheme of the bus capacitor who exchanges input power among the prior art, the utility model provides an anti-surge impact circuit and device and electronic equipment.
In one embodiment, as shown in fig. 1, the surge protection circuit includes a live line L, a neutral line N, a bus capacitor C1, a PWM control circuit 10, a voltage reduction circuit 20, and a rectification control circuit 30: the first end of bus capacitor C1 is connected to the load, and PWM control circuit 10 has first input, second input, current output, sampling input and control signal output, control circuit's first input with live wire L connects, PWM control circuit 10's second input with zero line N connects, and step-down circuit 20 has input, controlled end, sampling end and output, step-down circuit 20's input with PWM control circuit 10's current output end is connected, step-down circuit 20's controlled end with PWM control circuit 10's control signal output is connected, step-down circuit 20's output with bus capacitor C1's second end is connected, step-down circuit 20's sampling end with PWM control circuit 10's sampling input is connected, and rectification control circuit 30 has sampling end, first rectification control signal end and second rectification control signal end, rectification control circuit 30's sampling end with live wire L connects. The rectifier bridge circuit is provided with a first input end, a second input end, a first controlled end, a second controlled end and an output end, the first input end of the rectifier bridge circuit is connected with the live wire L, the second input end of the rectifier bridge circuit is connected with the zero line N, and the output end of the rectifier bridge circuit is connected with the second end of the bus capacitor C1.
The live line L and the zero line N are connected to a power supply; the PWM control circuit 10 outputs a conducting signal when the power supply is larger than a first preset voltage value; when receiving the conducting signal, the voltage reducing circuit 20 conducts a path between the rectifying circuit and the voltage reducing circuit 20, and outputs the rectified power supply to the bus capacitor C1 for charging after reducing the voltage; the rectification control circuit 30 outputs a rectification bridge conduction signal when the time for the live wire L to be connected to the power supply reaches a preset time; and the rectifier bridge circuit is conducted when receiving the rectifier bridge conduction signal so as to rectify and output the power supply. When the time of the live wire L accessing the power supply does not reach the preset time duration and the power supply is greater than the first preset voltage value, the PWM control circuit 10 directly controls the voltage reduction circuit 20 to conduct the rectifying circuit and the passage between the voltage reduction circuits 20, and outputs the rectified power supply to the bus capacitor C1 for charging after voltage reduction. Thereby realizing the initial constant current charging, when the time of connecting the live wire L to the power supply reaches the preset time,
the rectifier control circuit 30 outputs a rectifier bridge conduction signal, the rectifier bridge circuit is conducted when receiving the rectifier bridge conduction signal to rectify the power supply and then output, and at this time, the rectifier circuit stops working due to insufficient voltage. Because the voltage of the bus capacitor C1 after being charged for a period of time is close to the rectified voltage, the rectifier bridge circuit does not generate surge impact current when starting to work. Therefore, the technical problem that the buffer device is easily damaged by the charging scheme of the bus capacitor C1 of the alternating-current input power supply in the prior art can be solved.
In addition, the circuit in the mode is small in size and simple to control, when a load exists in output, the bus capacitor C1 can be charged, and the buffer device at the moment is replaced by the voltage reduction circuit 20, so that the buffer device can be prevented from being burnt.
It should be noted that the rectification control circuit 30 may be implemented by using a common control chip or a timing circuit with a timing trigger function.
Optionally, as shown in fig. 2, the rectifier bridge circuit includes a first diode D1, a second diode D2, a first optocoupler OT1 (only one half of the optocoupler is shown in fig. 2), a second optocoupler OT2, a first thyristor SC1, a second thyristor SC2, a first resistor R1, and a second resistor R2, where a collector of the first optocoupler OT1 and an anode of the first thyristor SC1 are interconnected with a cathode of the first diode D1, a connection node thereof is a first input end of the rectifier bridge circuit, and an emitter of the first optocoupler OT1, a first end of the first resistor R1, and a control electrode of the first thyristor SC1 are interconnected; a collector of the second optocoupler OT2 and an anode of the second thyristor SC2 are interconnected with a cathode of the second diode D2, and a connection node of the second optocoupler OT2 is a second input end of the rectifier bridge circuit, and an emitter of the second optocoupler OT2, a first end of the second resistor R2 and a control electrode of the second thyristor SC2 are interconnected; the cathode of the first controllable silicon SC1, the second end of the first resistor R1, the cathode of the second controllable silicon SC2 and the second end of the second resistor R2 are interconnected, and the connection node of the first controllable silicon SC1, the second end of the first resistor R1 and the second end of the second resistor R2 is the output end of the rectifier bridge circuit.
In the above embodiment, the rectifier bridge circuit is composed of discrete devices, and the rectifier bridge includes four bridge arm diodes, two of which are ordinary diodes D1 and D2, and the other two of which are thyristors SC1 and SC2 and control optocouplers OT1 and OT 2. The rectifier bridge circuit can be switched on at a proper time through the current, and surge impact current generated when the bus capacitor C1 is charged at the initial starting stage is avoided.
Optionally, the voltage-reducing circuit 20 includes a first switch tube Q1, a first inductor L1 and a third diode D3, the first end of the first switch tube Q1 is the input end of the voltage-reducing circuit 20, the second end of the first switch tube Q1 is respectively interconnected with the first end of the first inductor L1 and the cathode of the third diode D3, the connection node thereof is the sampling end of the voltage-reducing circuit 20, the controlled end of the first switch tube Q1 is the controlled end of the voltage-reducing circuit 20, the second end of the first inductor L1 is the output end of the voltage-reducing circuit 20, and the anode of the third diode D3 is grounded.
The voltage reducing circuit 20 is also a Buck circuit, and can adjust the pulse width output by the PWM control circuit 10 according to the current value after the PWM control circuit 10 samples the current value output by the second end of the first switching tube Q1, so as to implement constant current output. The bus voltage is stably charged.
Optionally, the first switching tube Q1 is an NMOS tube.
Optionally, the PWM control circuit 10 includes a rectifier module 101 and a control module 102, the rectifier module 101 has a first input end, a second input end and an output end, the control module 102 has an input end, a sampling input end and a control signal output end, the first input end of the rectifier module 101 is the first input end of the PWM control circuit 10, the second input end of the rectifier module 101 is the second input end of the PWM control circuit 10, the output end of the rectifier module 101 is connected with the control signal output end of the control module 102, the connection node is the current output end of the PWM control circuit 10, the sampling input end of the control module 102 is the sampling input end of the PWM control circuit 10, and the control signal output end of the control module 102 is the control signal output end of the PWM control circuit 10.
The rectifying module 101 rectifies a power supply, and the control module 102 outputs a conducting signal when the voltage of the power supply is greater than a first preset voltage value. It should be noted that, at this time, the bus capacitor C1 is turned on to perform initial charging under the condition that the input voltage is sufficient, so as to avoid undervoltage operation.
Optionally, the rectifier module 101 includes a fourth diode D4, a fifth diode D5, and a third resistor R3, an anode of the fourth diode D4 is a first input end of the rectifier module 101, and a cathode of the fourth diode D4 is respectively interconnected with a cathode of the fifth diode D5 and a first end of the third resistor R3; an anode of the fifth diode D5 is a second input end of the rectifier module 101, and a second end of the third resistor R3 is an output end of the rectifier module 101.
Wherein, fourth diode D4, fifth diode D5 can carry out the rectification to the power of live wire L and zero line N input respectively, and third resistance R3 can realize the step-down effect to a certain extent.
Optionally, the surge impact prevention circuit further includes a follow current circuit, an input end of the follow current circuit is connected to an output end of the rectifier bridge circuit, and an output end of the follow current circuit is connected to the first end of the bus capacitor C1.
The follow current circuit is used for rectifying the current output by the rectifier bridge circuit.
Optionally, the freewheel circuit is implemented with a seventh diode D7.
Optionally, the surge protection circuit further includes a sampling circuit, and the sampling circuit is disposed between the second end of the first switching tube Q1 and the cathode of the third diode D3.
The sampling circuit divides the voltage output by the second end of the first switch tube Q1, so as to facilitate current sampling of the PWM control circuit 10. To achieve real-time current sensing. Alternatively, the sampling circuit may be implemented using an eighth resistor R8.
Optionally, the control module 102 employs a first chip U1, a sixth diode D6, a second switch tube Q2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a first voltage regulator tube, and a specific connection relationship therebetween is shown in fig. 2. In addition, the model of the first chip is UC2843, and the second switch tube is an NMOS tube and works in a normally open state.
The working principle of the present invention is described below with reference to fig. 1 and 2:
after the zero line N and the live line L are powered on, since the accumulated time of the rectification control circuit 30 does not reach the preset time, the control optocouplers OT1 and OT2 of the thyristors SC1 and SC2 have no control signal input, and the thyristors are turned off. At this time, the input voltage is rectified by the D4 and the D5 and then starts the PWM control circuit 10 by the D6 and the Q2, the voltage reduction circuit starts to work, the PWM control circuit 10 controls the output current of the voltage reduction circuit 20 to be constant current output, and surge impact current cannot be generated. This current charges the bus capacitor C1. At this time, the preset time duration may be set as a time duration required for the voltage of the bus capacitor C1 to approach the input rectified voltage, so that the accumulated time duration of the rectification control circuit 30 reaches the preset time duration, and when the voltage of the bus capacitor C1 approaches the input rectified voltage, OT1 and OT2 receive the control signal, and the thyristor is turned on. At this time, surge current is not generated. The PWM control circuit 10 automatically stops operating due to insufficient power supply while the bus voltage approaches the rectifier bridge voltage. In addition, when the anti-surge circuit continues to operate, if the load exists in the output, if the load current is larger than the output current of the voltage reduction circuit 20, the voltage of the bus capacitor C1 will not rise, the bus voltage cannot approach the rectified voltage, and the power supply is still in a charging state and is not started. Only after the load is unloaded can the bus voltage rise. The process does not cause any device damage, and the reliability of the system is improved. The technical problem that a buffer device is easily damaged by a charging scheme of a bus capacitor C1 of an alternating-current input power supply in the prior art is solved.
In order to solve the above problem, the present invention further provides an electronic device, including the above surge protection circuit.
It should be noted that, because the electronic device of the present application includes all the steps of the above-mentioned surge protection circuit, the electronic device may also implement all the schemes of the surge protection circuit, and has the same beneficial effects, and details are not described herein again.
All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
Claims (8)
1. An anti-surge protection circuit, comprising:
the live wire is used for connecting a power supply;
a zero line;
a bus capacitor, a first end of the bus capacitor being connected to a load;
the PWM control circuit is provided with a first input end, a second input end, a current output end, a sampling input end and a control signal output end, wherein the first input end of the control circuit is connected with the live wire, the second input end of the PWM control circuit is connected with the zero line, and the PWM control circuit outputs a conducting signal when the power supply is larger than a first preset voltage value;
the input end of the voltage reduction circuit is connected with the current output end of the PWM control circuit, the controlled end of the voltage reduction circuit is connected with the control signal output end of the PWM control circuit, the output end of the voltage reduction circuit is connected with the second end of the bus capacitor, the sampling end of the voltage reduction circuit is connected with the sampling input end of the PWM control circuit, when the conduction signal is received, a path between the rectification circuit and the voltage reduction circuit is conducted, and the rectified power supply is output to the bus capacitor for charging after being subjected to voltage reduction;
the rectifier control circuit is provided with a sampling end, a first rectifier control signal end and a second rectifier control signal end, the sampling end of the rectifier control circuit is connected with the live wire, and a rectifier bridge conduction signal is output when the time for connecting the live wire into a power supply reaches a preset time length;
the rectifier bridge circuit is provided with a first input end, a second input end, a first controlled end, a second controlled end and an output end, the first input end of the rectifier bridge circuit is connected with the live wire, the second input end of the rectifier bridge circuit is connected with the zero line, the output end of the rectifier bridge circuit is connected with the second end of the bus capacitor, and the rectifier bridge circuit is conducted when receiving a rectifier bridge conduction signal so as to output the rectified power.
2. The surge protection circuit according to claim 1, wherein said rectifier bridge circuit comprises a first diode, a second diode, a first optocoupler, a second optocoupler, a first thyristor, a second thyristor, a first resistor, and a second resistor, wherein a collector of said first optocoupler and an anode of said first thyristor are interconnected with a cathode of said first diode, and a connection node thereof is a first input terminal of said rectifier bridge circuit, and wherein an emitter of said first optocoupler, a first terminal of said first resistor, and a control terminal of said first thyristor are interconnected; a collector of the second optocoupler and an anode of the second thyristor are interconnected with a cathode of the second diode, a connection node of the second optocoupler is a second input end of the rectifier bridge circuit, and an emitter of the second optocoupler, a first end of the second resistor and a control electrode of the second thyristor are interconnected; the cathode of the first controllable silicon, the second end of the first resistor, the cathode of the second controllable silicon and the second end of the second resistor are interconnected, and the connection node of the first controllable silicon and the second controllable silicon is the output end of the rectifier bridge circuit.
3. The surge protection circuit according to claim 1, wherein the voltage reduction circuit comprises a first switch tube, a first inductor, and a third diode, a first end of the first switch tube is an input end of the voltage reduction circuit, a second end of the first switch tube is respectively interconnected with the first end of the first inductor and a cathode of the third diode, a connection node thereof is a sampling end of the voltage reduction circuit, a controlled end of the first switch tube is a controlled end of the voltage reduction circuit, a second end of the first inductor is an output end of the voltage reduction circuit, and an anode of the third diode is grounded.
4. The surge-protection circuit according to claim 1, wherein said PWM control circuit comprises a rectifier module and a control module, said rectifier module has a first input terminal, a second input terminal and an output terminal, said control module has an input terminal, a sampling input terminal and a control signal output terminal, said first input terminal of said rectifier module is said first input terminal of said PWM control circuit, said second input terminal of said rectifier module is said second input terminal of said PWM control circuit, said output terminal of said rectifier module is connected to said control signal output terminal of said control module, the connection node thereof is said current output terminal of said PWM control circuit, said sampling input terminal of said control module is said sampling input terminal of said PWM control circuit, and said control signal output terminal of said control module is said control signal output terminal of said PWM control circuit.
5. The surge protection circuit according to claim 4, wherein said rectifying module comprises a fourth diode, a fifth diode and a third resistor, an anode of said fourth diode is a first input terminal of said rectifying module, and a cathode of said fourth diode is interconnected with a cathode of said fifth diode and a first terminal of said third resistor, respectively; the anode of the fifth diode is the second input end of the rectifying module, and the second end of the third resistor is the output end of the rectifying module.
6. The surge protection circuit according to any of claims 1-5, wherein said surge protection circuit further comprises a freewheeling circuit, an input of said freewheeling circuit being connected to an output of said rectifier bridge circuit, an output of said freewheeling circuit being connected to a first end of said bus capacitor.
7. The surge protection circuit according to claim 3, further comprising a sampling circuit, wherein said sampling circuit is disposed between the second terminal of said first switching tube and the cathode of said third diode.
8. An electronic device, characterized by comprising the surge protection circuit according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221197472.7U CN218124547U (en) | 2022-05-17 | 2022-05-17 | Surge impact prevention circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221197472.7U CN218124547U (en) | 2022-05-17 | 2022-05-17 | Surge impact prevention circuit and electronic equipment |
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| Publication Number | Publication Date |
|---|---|
| CN218124547U true CN218124547U (en) | 2022-12-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221197472.7U Active CN218124547U (en) | 2022-05-17 | 2022-05-17 | Surge impact prevention circuit and electronic equipment |
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| Country | Link |
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| CN (1) | CN218124547U (en) |
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- 2022-05-17 CN CN202221197472.7U patent/CN218124547U/en active Active
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