CN218123386U

CN218123386U - Device structure for fan-out type wafer level chip

Info

Publication number: CN218123386U
Application number: CN202221874629.5U
Authority: CN
Inventors: 曹宇; 易光
Original assignee: Shenzhen Weijaming Technology Co ltd
Current assignee: Shenzhen Weijaming Technology Co ltd
Priority date: 2022-07-11
Filing date: 2022-07-11
Publication date: 2022-12-23
Anticipated expiration: 2032-07-11

Abstract

The utility model discloses a device structure for fan-out type wafer level chip, which comprises a substrate, wherein a first welding pad is arranged at the top of the substrate, a solder mask is formed on the first welding pad, a solder ball bump is arranged at the top of the first welding pad, an insulating medium layer is arranged at the top of the solder ball bump, a second welding pad is arranged on the insulating medium layer, a conductive metal layer is arranged between the second welding pad and the solder ball bump, a chip body is arranged at the top of the second welding pad, a fan-out structure is arranged on the chip body, and conductive heating panels are arranged on two sides of the bottom of the chip body; the utility model discloses a be equipped with insulating medium layer and conductive heating panel outside the chip, the shape fit of solder ball bump and conductive metal layer, the angularity of reduction chip that can be great, the wire in the fan-out structure simultaneously and the cooperation between the perforation in the conductive metal layer, under guaranteeing the holistic condition of chip, can effectually dispel the heat to the chip, the increase that reduces density makes the heat sharply increased that produces on the unit area.

Description

Device structure for fan-out type wafer level chip

Technical Field

The utility model relates to a technical field of chip device structure specifically is a device structure for fanning out type wafer level chip.

Background

Wafer level fan-out package structures are widely used in the semiconductor industry. The fan-out wafer level chip package is a fan-out package for realizing a main chip at a wafer size level, and how to reduce warpage generated in a manufacturing process and have mass production capability in the fan-out package is increasingly important.

In the traditional packaging process of a fan-out wafer level chip, after a crystal grain is subjected to plastic packaging, a semiconductor chip device is easy to warp on a packaging structure due to material characteristics, so that subsequent chip processing is difficult, meanwhile, in order to avoid warping of the packaging structure, the density of the chip is generally improved, but the increase of the density enables heat generated on a unit area to be increased rapidly, and if the heat cannot be dissipated rapidly, metal in the chip is further melted to fail.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a device structure for fan-out type wafer level chip to solve the problem that proposes among the above-mentioned background art.

In order to achieve the above purpose, the utility model provides a following technical scheme: the utility model provides a device structure for fan-out type wafer level chip, includes the base plate, the top of base plate is provided with first pad, forms the solder mask on the first pad, and the top of first pad is provided with the solder ball bump, and the top of solder ball bump is provided with insulating medium layer, is provided with the second pad on the insulating medium layer, is provided with the conductive metal layer between second pad and the solder ball bump, and the top of second pad is provided with the chip body, is provided with the fan-out structure on the chip body, and the bottom both sides of chip body all are provided with conductive heating panel.

Preferably, the bottom of the solder ball salient point is of a trapezoid structure, and filling glue is arranged between the solder ball salient point and the solder mask layer.

Preferably, a groove is formed in the insulating medium layer, and the conductive metal layer is of a trapezoid block structure and is embedded in the groove.

Preferably, the conductive metal layer is provided with a plurality of through holes, and the plurality of through holes are distributed along the conductive metal layer.

Preferably, the bottom of the chip body is provided with a contact point, the fan-out structure wraps around the chip body, and the fan-out structure comprises a wire.

Preferably, the conducting wires are provided with a plurality of conducting wires, the conducting wires are formed in the insulating medium layer, and the conducting wires penetrate through the conducting heat dissipation plate and are connected to the contact points of the chip body.

Compared with the prior art, the beneficial effects of the utility model are that:

1. the utility model discloses a be equipped with insulating medium layer and conductive heating panel outside the chip, the shape cooperation of solder ball bump and conductive metal layer, the angularity that reduces the chip that can be great, the wire in the fan-out structure simultaneously and the cooperation between the perforation in the conductive metal layer, under guaranteeing the holistic condition of chip, can effectually dispel the heat to the chip, the increase that reduces density makes the heat that produces sharply increase on the unit area, guarantees the performance of chip.

Drawings

FIG. 1 is a schematic view of the present invention;

fig. 2 is a schematic view of a partial structure of the insulating medium layer of the present invention.

In the figure: 1. a substrate; 2. a first bonding pad; 3. a solder resist layer; 4. solder bump; 41. filling glue; 5. an insulating dielectric layer; 51. a trench; 6. a second pad; 7. a conductive metal layer; 71. perforating; 8. a chip body; 81. a contact point; 9. a fan-out structure; 91. a wire; 10. an electrically conductive heat sink plate.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Deformation amount of the substrate 3 when the environmental temperature changes rapidly can be effectively reduced by arranging the supporting piece 5, and the reliability failure risk caused by thermal mismatch among packaging materials of all layers is reduced.

Referring to fig. 1 to 2, the present invention provides a technical solution: a device structure for a fan-out wafer level chip comprises a substrate 1, wherein the chip is in an inverted structure, a first bonding pad 2 is arranged at the top of the substrate 1, a solder mask layer 3 is formed on the first bonding pad 2, and the solder mask layer 3 is solder mask ink and is used as a protective film of a circuit when an electronic component is welded;

the top of the first bonding pad 2 is provided with a solder ball salient point 4, the solder ball salient point 4 is usually made of tin materials, the bottom of the solder ball salient point 4 is in a trapezoidal structure, filling glue 41 is arranged between the solder ball salient point 4 and the solder mask layer 3, and the space occupied by the solder ball salient point 4 can be greatly reduced, the volume of an electronic component is reduced, the integration level of a semiconductor device is increased, and meanwhile, the welding stability is ensured;

an insulating medium layer 5 is arranged on the top of the solder ball salient point 4, a second bonding pad 6 is arranged on the insulating medium layer 5, a conductive metal layer 7 is arranged between the second bonding pad 6 and the solder ball salient point 4, a groove 51 is arranged on the insulating medium layer 5, the conductive metal layer 7 is in a trapezoid block structure and is embedded in the groove 51, the shape of the solder ball salient point 4 is matched with that of the conductive metal layer 7, the tensile stress of the metal electrode on the conductive metal layer 7 is reduced, the connection is tighter, the integration level of the semiconductor device is increased, and the height of the conductive metal layer 7 is higher than that of the insulating medium layer 5 with the groove 51, so that the signal connection with other chips is facilitated;

the conductive metal layer 7 is provided with a plurality of through holes 71, the through holes 71 are distributed along the conductive metal layer 7, the through holes 71 are a laser through hole technology and provide a heat dissipation effect, the top of the second bonding pad 6 is provided with a chip body 8, and the bottom of the chip body 8 is provided with a contact point 81;

the fan-out structure 9 is arranged on the chip body 8, the fan-out structure 9 is wrapped around the chip body 8, the conductive heat dissipation plates 10 are arranged on two sides of the bottom of the chip body 8, heat of the chip body 8 is conveniently conveyed to the conductive heat dissipation plates 10, the fan-out structure 9 comprises wires 91, the wires 91 are provided with a plurality of wires, the plurality of wires 91 are formed in the insulating medium layer 5, the wires 91 penetrate through the conductive heat dissipation plates 10 and are connected to contact points 81 of the fan-out structure 9, and the wires 91 form heat dissipation channels, so that the conductive heat dissipation plates 10 are transmitted to the outside through the heat dissipation channels formed by the wires 91 and the through holes 71;

in actual operation, a wafer-level chip is inversely packaged, the solder ball salient points 4 are located between the first bonding pad 2 and the second bonding pad 6, the solder ball salient points 4 are connected with the conductive metal layer 7 in the grooves 51 in an embedded mode, the space occupied by the solder ball salient points 4 is greatly reduced, meanwhile, the solder ball salient points 4 are matched with the conductive metal layer 7 in shape, the pulling stress of the metal electrodes on the conductive metal layer 7 is reduced, the connection is tighter, the integration level of a semiconductor device is increased, the insulating medium layer 5 and the conductive heat dissipation plate 10 are connected with the chip body 8, the fan-out structure wraps the chip body 8, and the warping degree of the chip is greatly reduced; the heat of chip body 8 is carried to conductive heat dissipation board 10 on, wire 91 runs through conductive heat dissipation board 10 and connects on fan-out structure 9's contact point 81, wire 91 forms heat dissipation channel, make the heat dissipation channel that forms conductive heat dissipation board 10 through wire 91 and perforation 71 transmit to the outside, under the holistic condition of assurance chip, can effectually dispel the heat to the chip, the increase that reduces density makes the heat that produces sharply increase on the unit area, guarantee the performance of chip.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A device structure for fan-out wafer level chips, comprising a substrate (1), characterized in that: the novel packaging structure is characterized in that a first bonding pad (2) is arranged at the top of the substrate (1), a solder mask layer (3) is formed on the first bonding pad (2), solder ball bumps (4) are arranged at the top of the first bonding pad (2), an insulating medium layer (5) is arranged at the top of the solder ball bumps (4), a second bonding pad (6) is arranged on the insulating medium layer (5), a conductive metal layer (7) is arranged between the second bonding pad (6) and the solder ball bumps (4), a chip body (8) is arranged at the top of the second bonding pad (6), a fan-out structure (9) is arranged on the chip body (8), and conductive heat dissipation plates (10) are arranged on two sides of the bottom of the chip body (8).

2. The device structure for the fan-out wafer level chip of claim 1, wherein: the bottom of the solder ball salient point (4) is of a trapezoidal structure, and filling glue (41) is arranged between the solder ball salient point and the solder mask layer (3).

3. The device structure for the fan-out wafer level chip of claim 1, wherein: the insulating medium layer (5) is provided with a groove (51), and the conductive metal layer (7) is in a trapezoid block structure and is embedded in the groove (51).

4. The device structure for the fan-out wafer level chip of claim 1, in which: the conductive metal layer (7) is provided with a plurality of through holes (71), and the through holes (71) are distributed along the conductive metal layer (7).

5. The device structure for the fan-out wafer level chip of claim 1, in which: the bottom of chip body (8) is provided with contact point (81), and fan-out structure (9) parcel is around chip body (8), and fan-out structure (9) include wire (91).

6. The device structure for the fan-out wafer level chip of claim 5, wherein: the plurality of conducting wires (91) are formed in the insulating medium layer (5), and the conducting wires (91) penetrate through the conductive heat dissipation plate (10) and are connected to the contact points (81) of the chip body (8).