CN2181009Y - Portable dc grounding resistance measurer - Google Patents

Abstract

The utility model discloses a DC resistance detector which solves the measurement problem of the ground resistance of a DC bus. The DC resistance detector is characterized in that a plurality of frequency sine signals are added on a DC bus, a signal detecting part is used to detect the signal voltage equivalent to the value of a grounded resistance, and a signal processing part composed of a single-chip microcomputer is used to work out the actual value of the resistance. The utility model can effectively distinguish the resistive component and the capacitive impedance component in the ground impedance of the DC bus, so that false alarms are avoided. The utility model is useful to the judgment and the prevention of the ground faults of the DC bus and can be widely used in the power industry and other DC power supply systems.

Description

Portable dc grounding resistance measurer

The utility model has related to a kind of device of measuring DC power-supply circuit resistance to earth value.

DC power-supply system is the important component part of power industry, measures DC power-supply system resistance to earth value exactly, and is very important for the normal operation that ensures consumer.At present commercially available DC earthing detection instrument adopts the sinusoidal signal that adds a single-frequency in DC power-supply system, detects DC power-supply system resistance value over the ground and judges whether ground connection of this system.This method often is DC earthing to the little also erroneous judgement of capacitive reactance owing to active component and capacitive reactance part that can not judge in the resistance value, causes false alarm, brings loss to work.Existing DC earthing detection instrument can only be indicated grounding alarm, brings loss to work.Existing DC earthing detection instrument can only be indicated grounding alarm, does not reflect actual resistance to earth value, thereby can not prevent the generation of DC ground fault.

Task of the present utility model is to provide a kind of device that can directly measure DC power-supply system resistance to earth value.

The technical scheme of finishing the utility model task is the low frequency sinusoidal signal that adds a plurality of frequencies in DC power-supply system, the size of the induced signal of sinusoidal signal in DC power-supply system by measuring each frequency detects the size of this DC power-supply system resistance to earth and capacitive reactance with microsystem.

Fig. 1 is the block scheme of input part of the present utility model.

Give 50HZ trapper after the signal voltage that contains f1 and two frequencies of f2 that the inductance type detection head obtains by induction amplifies through the prime amplifier difference, the component of 50HZ is attenuated.Through low-pass active filter the frequency component that is higher than f2 is curbed,, further suppress 50HZ component and the frequency component that is lower than f1 again through a 50HZ trapper and a high pass active filter.Low-pass active filter and high pass active filter have been formed a bandpass filter, and its cutoff frequency is f1, f2.Proportional amplifier divides two-way output.One the tunnel through arrowband trapper I and arrowband frequency selector I, suppresses the frequency component of f2, selects the frequency component of f1, through the detection signal of proportion adjustable amplifier I output f1.Another road curbs the f1 signal through arrowband trapper II, arrowband frequency selector II, selects the frequency component of f2, through the detection signal of proportion adjustable amplifier II output f2.

Fig. 2 is the utility model signal processing block scheme.

IC7 is that an analog switching ic is selected in 4052 both-ends input four.The frequency of proportion adjustable amplifier I and the output of proportion adjustable amplifier II is that the signal of f1 and f2 is delivered to IC71 pin and 5 pin respectively.

IC5 is an A/D converter, and model is AD375, exports 12 position digital signals.F1 signal of being selected by the gating signal of 10 pin of IC7 or f2 signal are delivered to 14 pin of IC5 through 3 pin of IC7, are exported by 16 pin-27 pin after the IC5A/D conversion.

IC1 is 8031 single-chip microcomputers.The digital signal of the 16 pin-27 pin output of IC5 is given 31 pin-39 pin of IC1.

IC2 is 8 latchs of 74LS373.

IC3 is 2764EPROM.

IC4 is 2864EFPROM.

IC6 is 8155 integrated circuit, is the interface of 8031 single-chip microcomputers and display, keyboard.

Fig. 3 is the electrical schematic diagram of the signal source of the utility model embodiment.

Ic chip 1:A, IC1:D and the element around it are formed the sinusoidal oscillation circuit of 13HZ, and oscillation frequency is by resistance R 11, R13, capacitor C 11, C13 decision.

IC2:B, IC2:C and the element around it are formed the sinusoidal oscillation circuit of 7HZ, and oscillation frequency is by resistance R 21, R23, capacitor C 21, C23 decision.

IC1:C and the element around it are formed summitor.The sinusoidal signal of the f1=7HZ of IC1:B output is delivered to 10 pin of IC1:C, and the f2=13HZ sinusoidal signal of IC2:A output is delivered to 9 pin of IC1:C, forms the composite signal output of f1+f2 after the IC1:C addition.

Fig. 4 is the schematic diagram of inductance type detection head of the present utility model.

When signal source voltage VS is added on the dc bus by CO, R and C are dc bus resistance, electric capacity over the ground, and at this moment the inductance L by the inductance type detection head can detect the detection voltage corresponding to resistance R, capacitor C size.

Fig. 5 is the electrical schematic diagram of input part of the present utility model.

The differential amplifier that integrated circuit (IC) 1:D and the element around it are formed is a prime amplifier, and gain is 50 times.

IC1:A and form the 50HZ trapper by the twin-T network that R15, R16, C13, C14, C15, R17 form exchanges the component of 50HZ with filtering.

IC1:B and form low-pass active filter by the network that R110, R111, C16, C17 form is higher than the frequency component of 13HZ with filtering.

IC1:D and C21, C22, R21, R22 form the high pass active filter, are used for filtering to be lower than the frequency component of 7HZ.

IC1:C and element are on every side formed the 50HZ trapper, with the component of the 50HZ in the filtered signal once more.

IC2:A and element proportion of composing amplifier on every side.

After the signal one tunnel of pin 1 output of proportional amplifier IC2:A passes through the component of the arrowband trapper I filtering 13HZ that is made up of IC2:B and twin-T network, select the component of 7HZ through IC3:A arrowband frequency selector I.The signal of 7HZ is exported through proportion adjustable amplifier IC3:B.Another road arrowband trapper II filtering 7HZ component through being made up of IC2:C and twin-T network is selected the component of 13HZ through IC3:D arrowband frequency selector II, is exported by proportion adjustable amplifier II.

Fig. 6 is a signal processing schematic diagram of the present utility model.

IC1 is 8031 single-chip microcomputers.

IC2 is the 74LS373 latch.

IC3 is 2764 EPROM.

IC4 is 2864 EEPROM.

IC5 is the AD574 A/D converter.

IC6 is 8155 interface chips.

IC7 4,052 four selects an analog switch.

IC8:A, IC8:B, IC8:C form reset signal generator.

It is the signal processing at center that IC1-IC8 has formed with single-chip microcomputer 8031.

F1 that the signal detecting part branch is sent here and f2 sinusoidal signal are delivered to 1 pin and 5 pin of IC7 respectively.The signal voltage of alternately being exported f1 or f2 by 3 pin converts 12 digital signal to AD574 and enters 8031 Single Chip Microcomputer (SCM) system at twice and handle.

8031 single-chip microcomputers adopt inquiry mode to read in the converter data of AD574.The data result of handling through 8031 single-chip microcomputers is through 8155 interface driving display printers.8031 by 8155 interfaces connection keyboard, realizes man-machine conversation.

Fig. 7 is a signal handler block diagram of the present utility model.

Dc bus grounding resistance and capacitor value are obtained by following formula:

$\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="932143245\_DRIMG2.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">R</figure-callout>}2=\frac{(P^2-1)(1+{\mathrm{<figure-callout\; id="0"\; label="X"\; filenames="932143245\_DRIMG3.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">X</figure-callout>}}_0^2{\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="932143245\_DRIMG1.png,932143245\_DRIMG3.png"\; state="\{\{state\}\}">K</figure-callout>}}_1^2{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="932143245\_DRIMG1.png,932143245\_DRIMG3.png"\; state="\{\{state\}\}">V</figure-callout>}}_1^2)(1+{\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="932143245\_DRIMG2.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">P</figure-callout>}}^2+{\mathrm{<figure-callout\; id="0"\; label="X"\; filenames="932143245\_DRIMG3.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">X</figure-callout>}}_0^2{\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="932143245\_DRIMG2.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">K</figure-callout>}}_2^2{\mathrm{<figure-callout\; id="2"\; label="V"\; filenames="932143245\_DRIMG2.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">V</figure-callout>}}_2^2)}{P^2{\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="932143245\_DRIMG2.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">K</figure-callout>}}_2^2{\mathrm{<figure-callout\; id="2"\; label="V"\; filenames="932143245\_DRIMG2.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">V</figure-callout>}}_2^2-{\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="932143245\_DRIMG1.png,932143245\_DRIMG3.png"\; state="\{\{state\}\}">K</figure-callout>}}_1^2{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="932143245\_DRIMG1.png,932143245\_DRIMG3.png"\; state="\{\{state\}\}">V</figure-callout>}}_1^2}$

$\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="932143245\_DRIMG2.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">X</figure-callout>}2=\frac{(1+{\mathrm{<figure-callout\; id="0"\; label="X"\; filenames="932143245\_DRIMG3.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">X</figure-callout>}}_0^2{\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="932143245\_DRIMG1.png,932143245\_DRIMG3.png"\; state="\{\{state\}\}">K</figure-callout>}}_1^2{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="932143245\_DRIMG1.png,932143245\_DRIMG3.png"\; state="\{\{state\}\}">V</figure-callout>}}_1^2)(1+P^2{\mathrm{<figure-callout\; id="0"\; label="X"\; filenames="932143245\_DRIMG3.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">X</figure-callout>}}_0^2{\mathrm{<figure-callout\; id="0"\; label="K"\; filenames="932143245\_DRIMG3.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">K</figure-callout>}}_0^2{\mathrm{<figure-callout\; id="0"\; label="V"\; filenames="932143245\_DRIMG3.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">V</figure-callout>}}_0^2)}{{\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="932143245\_DRIMG1.png,932143245\_DRIMG3.png"\; state="\{\{state\}\}">K</figure-callout>}}_1^2{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="932143245\_DRIMG1.png,932143245\_DRIMG3.png"\; state="\{\{state\}\}">V</figure-callout>}}_1^2-{\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="932143245\_DRIMG2.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">K</figure-callout>}}_2^2{\mathrm{<figure-callout\; id="2"\; label="V"\; filenames="932143245\_DRIMG2.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">V</figure-callout>}}_2^2+(P^2-1){\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="932143245\_DRIMG1.png,932143245\_DRIMG3.png"\; state="\{\{state\}\}">K</figure-callout>}}_1^2{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="932143245\_DRIMG1.png,932143245\_DRIMG3.png"\; state="\{\{state\}\}">V</figure-callout>}}_1^2{\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="932143245\_DRIMG2.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">K</figure-callout>}}_2^2{\mathrm{<figure-callout\; id="2"\; label="V"\; filenames="932143245\_DRIMG2.png,932143245\_DRIMG5.png"\; state="\{\{state\}\}">V</figure-callout>}}_2^2}$

Wherein: X0 is the capacitive reactance of the coupling capacitance C0 between signal source and the dc bus.P is the value of f2/f1

K ₁＝V ₁₀R ₀

K ₂＝V ₂₀R ₀

R ₀The measured resistance value of setting during for the utility model verification

V ₁₀V ₂₀Be the detection signal magnitude of voltage that records after the measured resistance setting

V ₁, V ₂Be respectively the signal voltage value that detected frequency is f1, f2.

Because the utility model has adopted the method that adds two-frequency signal on dc bus, thereby effectively dc bus resistance to earth value and capacitor value difference are come, can correctly provide the size of dc bus resistance to earth.The utility model not only can be measured fault easily on which branch road of dc bus, also can dc bus over the ground actual resistance measure, this is for the necessary great economy heavy economic losses of being avoided of preventing accident.Measurement range of the present utility model is 0-500K Ω, and precision can reach 0.1K Ω, can be widely used in the power industry.

Claims (4)

1, a kind of Portable DC stake resistance detection instrument, it is characterized in that forming by signal source, input part, signal processing part branch, signal source with two low frequency sinusoidal signal oscillatory circuits is connected by electric capacity with tested direct current supply line, and two low frequency sinusoidal signals that signal source produces are by being capacitively coupled on the tested direct current supply line; Tested direct current supply line is connected with the signal detecting part branch by the inductance type detection head of input part, and the input part detects two low frequency sinusoidal signal voltages respectively from the voltage of inductance type detection head induction; The input part is connected with the signal processing with signal handler, and direct current supply line resistance value is over the ground handled and provided to two low frequency sinusoidal signal voltages that signal processing is sent here the signal detecting part branch.

2, Portable DC stake resistance detection instrument according to claim 1, it is characterized in that having in the signal source summitor to be connected with two low frequency sinusoidal signal circuit respectively, summitor is capacitively coupled on the tested direct current supply line after the addition of two low frequency sinusoidal signals.

3, Portable DC stake resistance detection instrument according to claim 1, it is characterized in that the input part is made up of inductance type detection head, prime amplifier, 50HZ trapper, low-pass active filter, high pass active filter, proportional amplifier and two-way arrowband trapper, arrowband frequency selector, proportion adjustable amplifier, the voltage of inductance type detection head induction is delivered to the prime amplifier that is connected with it and is amplified; Prime amplifier is connected with the 50HZ trapper, filters out the component of voltage of 50HZ and is fed to low-pass active filter, the high pass active filter that is connected with it voltage of 50HZ trapper after prime amplifier amplifies; The bandpass filter that low-pass active filter and high pass active filter are formed is passed through the interior frequency component of two low frequency sinusoidal signal frequency bands, and delivers to the proportional amplifier that is connected with it; Proportional amplifier is connected with two-way arrowband trapper, arrowband frequency selector, proportion adjustable amplifier respectively; Two-way arrowband trapper, arrowband frequency selector, proportion adjustable amplifier are selected two low frequency sinusoidal signal voltages respectively.

4, Portable DC stake resistance detection instrument according to claim 1, it is characterized in that signal processing selects an analog switch, interface circuit to be made up of single-chip microcomputer with the A/D converter that is connected with it, EPROM, EEPROM memory, latch, four, two low frequency sinusoidal signal voltages that the signal detecting part branch is sent here four select an analog switch alternately to export two low frequency sinusoidal signal voltages and deliver to A/D converter through what be connected with it; A/D conversion back is handled by single-chip microcomputer.

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