CN218037937U

CN218037937U - Isolation feedback type initialization circuit and electronic equipment

Info

Publication number: CN218037937U
Application number: CN202220605653.2U
Authority: CN
Inventors: 黄子洋
Original assignee: Guangzhou Shiyuan Innovation Technology Co ltd; Guangzhou Shiyuan Electronics Thecnology Co Ltd
Current assignee: Guangzhou Shiyuan Innovation Technology Co ltd; Guangzhou Shiyuan Electronics Thecnology Co Ltd
Priority date: 2022-03-18
Filing date: 2022-03-18
Publication date: 2022-12-13
Anticipated expiration: 2032-03-18

Abstract

The embodiment of the disclosure provides an isolation feedback type initialization circuit and electronic equipment, and relates to the technical field of automatic control. Wherein the circuit comprises: a reset unit for: generating a reset signal and sending the reset signal to a target chip so as to reset the target chip; a feedback unit connected to the reset unit for: acquiring the level state of the reset signal, and generating a control signal according to the level state; and a control unit connected to the feedback unit for: and sending a control instruction to the target chip according to the control signal. Through the circuit, the problem that the chip cannot normally receive the control instruction due to the change of the reset time caused by the temperature change can be solved.

Description

Isolation feedback type initialization circuit and electronic equipment

Technical Field

The present disclosure relates to the field of automatic control technologies, and in particular, to an isolation feedback type initialization circuit and an electronic device.

Background

As the degree of integration of integrated circuits becomes higher and larger, the scale becomes larger and the circuits become more and more complex. In order to avoid the circuit from generating an abnormality during operation, a reset circuit is usually implanted in the integrated circuit.

The function of the reset IC (Integrated Circuit) is: when the functional chip and the reset IC are powered on simultaneously, the reset IC can continuously pull down the reset pin of the functional chip to enable the functional chip to be continuously reset for a period of time. However, the reset IC has different reset times under different environmental temperatures, and the time for pulling down the reset pin by some reset ICs under low temperature is lengthened. If the time for the SOC (System On Chip) to send an instruction to the functional Chip is not changed, and the SOC sends an instruction to the functional Chip through the Inter-Integrated Circuit (IIC) when the ambient temperature is low, the reset IC still resets the functional Chip, so that the functional Chip cannot receive the instruction and cannot normally operate.

It is noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure and therefore may include information that does not constitute prior art that is already known to a person of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

The present disclosure provides an isolated feedback type initialization circuit and an electronic device. Aiming at the influence of temperature change on the functions of the chip, the method and the device at least can solve the problem that the control instruction cannot be normally received due to the change of reset time caused by the temperature change.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure. According to an aspect of the present disclosure, there is provided an isolated feedback type initialization circuit, including: a reset unit for: generating a reset signal and sending the reset signal to a target chip so as to reset the target chip; a feedback unit connected to the reset unit, for: acquiring the level state of the reset signal, and generating a control signal according to the level state; and a control unit connected to the feedback unit, for: and sending a control instruction to the target chip according to the control signal.

Illustratively, the feedback unit includes: the power supply, the N-channel type field effect transistor and the resistor are connected in series; the power supply is connected to the grid electrode of the N-channel type field effect transistor, and the resistor is connected between the grid electrode of the N-channel type field effect transistor and the drain electrode of the N-channel type field effect transistor in parallel; the source of the N-channel FET is connected to the reset unit, and the drain of the N-channel FET is connected to the control unit.

Illustratively, the control unit includes: a detection subunit; the detection unit is configured to: and detecting the level of the control signal, and sending a control command to the target chip when the level is changed from low level to high level.

Illustratively, the target chip includes: a first pin and a second pin; wherein, the first pin is connected with the reset unit and used for: receiving the reset signal; the second pin is connected to the control unit, and is configured to: and receiving the control command.

Illustratively, the isolation feedback initialization circuit further includes: a temperature detection unit connected with the feedback unit, and a temperature control unit connected with the feedback unit; the temperature detection unit is configured to: detecting the ambient temperature of the reset unit; the temperature control unit is configured to: under the condition that the environment temperature is out of a preset temperature range, adjusting the environment temperature to be within the preset temperature range; wherein the ambient temperature is a temperature within 2 cm from the reset unit.

Illustratively, the temperature detecting unit includes: an alarm; the alarm is used for: and sending alarm information under the condition that the environment temperature is higher than the dangerous temperature so as to enable a user to disconnect the power supply of the isolation feedback type initialization circuit.

Illustratively, the feedback unit includes: a photoelectric converter; the photoelectric converter is used for: and receiving a light source of the external environment where the isolation feedback type initialization circuit is located, converting the light source into electric energy, and supplying power to the temperature control unit.

Illustratively, the feedback unit includes: a timer; the timer is configured to: acquiring the reset state of the target chip, and timing the reset time of the target chip; the reset time refers to: the time taken for the reset signal to transition from a low level to a high level.

Exemplarily, the feedback unit includes: resetting the control for the second time; the secondary reset control is configured to: acquiring the reset state of the target chip by taking a preset time interval as a period, and sending a reset signal to the target chip under the condition that the reset state is reset failure; and when the reset state is the successful reset state, stopping sending the reset signal to the target chip.

According to another aspect of the present disclosure, an electronic device is provided, wherein the electronic device includes the isolated feedback type initialization circuit in the above embodiment.

The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:

some embodiments of the present disclosure provide circuits, including the following circuits: a reset unit to: generating a reset signal and sending the reset signal to a target chip so as to reset the target chip; the feedback unit is connected with the reset unit and is used for: acquiring the level state of the reset signal, and generating a control signal according to the level state; and a control unit connected to the feedback unit, for: and sending a control instruction to the target chip according to the control signal. Through the circuit, the problem that the chip cannot normally receive the control instruction due to the change of the reset time caused by the temperature change can be solved, and further, the stability of the circuit in working under various environments can be improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. It should be apparent that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived by those of ordinary skill in the art without inventive effort.

Fig. 1 schematically illustrates a circuit schematic of a reset unit in an exemplary embodiment according to the present disclosure.

Fig. 2 schematically illustrates a schematic structural diagram of an isolated feedback initialization circuit according to an exemplary embodiment of the present disclosure.

Fig. 3 schematically illustrates a circuit schematic of an isolated feedback initialization circuit in an exemplary embodiment according to the present disclosure.

FIG. 4 schematically illustrates a block diagram of an electronic device in an exemplary embodiment according to the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more clear, embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings.

The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of electronic devices and isolated feedback initialization circuits consistent with certain aspects of the present disclosure, as detailed in the appended claims.

In the description of the present disclosure, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present disclosure can be understood in a specific case to those of ordinary skill in the art. Further, in the description of the present disclosure, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

The reset circuit is widely applied to a plurality of circuits, however, the reset IC has different reset times under different environmental temperatures, and the time for pulling down the reset pin by some reset ICs under the condition of low temperature is prolonged. If the time for the SOC to send the instruction to the functional chip is not changed, the reset IC still resets the functional chip when the SOC sends the instruction to the functional chip through the IIC under the condition of low environmental temperature, so that the functional chip cannot receive the instruction and cannot work normally.

Fig. 1 schematically illustrates a circuit diagram of a reset unit according to an exemplary embodiment of the present disclosure.

Referring to fig. 1, the electronic device includes a reset button 3V3-MN869120, a reset chip UH503, a resistor RH510, a resistor RH511, a capacitor CH537, a capacitor CH538, and a TVS (Transient Voltage Suppressor) DH501. Wherein, the reset chip UH503 includes: pin 1 GND, pin 2 RESET, pin 3 VCC, where the VCC is connected to the RESET button 3V3-MN869120, the GND is grounded, one end of the capacitor CH537 is grounded, the other end is connected to the above, one end of the RH511 is grounded, the other end is connected to RESET, the CH538 and the DH501 are connected in parallel between the RH510 and GND, one end of the RH510 is connected to RESET, and the other end is connected to CH538. The capacitor CH537 is used for: when the reset key 3V3-MN869120 is switched on, noise signals in input current are filtered. The resistor RH510 and the capacitor CH538 form a frequency-selecting branch for: the frequency of the output voltage of the RESET end of the RESET chip UH503 is selected, the voltage on CH538 after frequency selection is stabilized through the DH501, and the voltage of the DH501 is output to the MN869120NRESET, so that the chip MN869120 is RESET.

When the circuit works, if the chip MN869120 is still in a reset state, the SOC sends an initialization command, which may cause abnormal boot of the electronic device applying the chip. If the chip MN869120 has been successfully reset early, but the SOC does not issue an initialization command late, this may result in the chip being initialized too slowly.

Therefore, in order to solve the above problems, the present disclosure proposes an isolated feedback type initialization circuit. The isolated feedback initialization circuit is described in detail below with reference to fig. 2 and 3.

Referring to fig. 2, a schematic diagram of an isolated feedback initialization circuit according to an exemplary embodiment of the present disclosure is schematically illustrated.

As shown in fig. 2, the isolation feedback type initialization circuit 200 includes a reset unit 210, a feedback unit 220, a control unit 230, and a target chip 240. The feedback unit 220 is connected to the reset unit 210 and the control unit 230, respectively, and the target chip refers to a main control chip in an electronic device, and is configured to load an operating system, run the operating system, receive an operating instruction, and execute the operating instruction.

The reset unit 210 is configured to: a reset signal is generated and transmitted to the target chip 240 to reset the target chip 240.

The feedback unit 220 is configured to: and acquiring the level state of the reset signal, and generating a control signal according to the level state.

The control unit 230 is configured to: and sends a control command to the target chip 240 according to the control signal.

Through the scheme, the problem that the control instruction cannot be normally received due to the change of the reset time caused by the temperature change can be solved.

Fig. 3 schematically illustrates a circuit schematic of an isolated feedback initialization circuit according to an exemplary embodiment of the present disclosure.

Referring to fig. 3, the feedback unit 220 is shown as 330 in fig. 3, and includes: a power supply VCC (voltage Controlled Carrier), an N-channel type field effect transistor Q1, and a resistor R1.

In an exemplary embodiment, the power source VCC is connected to the G pole of the N-channel fet Q1, and the resistor R1 is connected in parallel between the G pole and the D pole of the N-channel fet Q1; the S-pole of the N-channel fet Q1 is connected to the reset unit 110 (reset IC), and the D-pole of the N-channel fet is connected to the control unit 130 (SOC). Wherein, the G pole refers to the grid of the N-channel field effect transistor Q1, the S pole refers to the source of the N-channel field effect transistor Q1, and the D pole refers to the drain of the N-channel field effect transistor Q1.

In the working process of the isolation feedback type initialization circuit, the SOC uses GPIO (General-Purpose-programmable Input/Output) X to check the level state of GPIOX in a GPIO interrupt manner. When the circuit board is powered on, because the RESET IC can continue to pull down the RESET pin for a period of time, according to the conduction condition of an NMOSFET (Metal Oxide Semiconductor Field Effect Transistor) tube, the S pole is at a low potential, the G pole is higher than the S pole, and the NMOSFET tube is conducted, namely the S pole and the D pole are at the same level and are both at the low potential. The GPIOX input to the SOC is naturally also low. After the RESET function of the RESET IC is finished, the RESET level is pulled high, the NMOSFET tube is not conducted at the moment, and GPIOX is naturally pulled up to be high level by the R1 resistor. When the SOC detects a rising edge process of GPIOX, i.e., a process of changing from low to high, the functional chip is initialized using IIC communication or a subsequent command is sent.

Through the scheme, linkage can be formed between the reset unit and the control unit, and the problem that the reset time is too fast or too slow due to inconsistent reset time of the reset unit under different environmental temperatures is solved. The control unit sends the instruction to the target chip after the feedback unit detects that the target chip is successfully reset, so that the problem that the target chip works abnormally due to the fact that the control chip sends the instruction to the target chip when the target chip is not successfully reset is avoided. And because the input impedance of the NMOSFET integrated circuit is very high and has an isolation effect, the level interference of GPIOX can not affect the RESET reversely, and only can be transmitted to the GPIOX end from the RESET end in a one-way mode, so that the working stability and efficiency of the circuit are improved.

In an exemplary embodiment, the control unit 230 includes, as shown in the SOC of fig. 3: and a detection subunit.

The detection subunit is configured to: the level of the control signal is detected, and when the level changes from low level to high level, a control command is transmitted to the target chip 240.

In an exemplary embodiment, the target chip 240 includes: a first lead and a second lead. The first pin is connected to the reset unit 210, and is configured to: and receiving the reset signal. The second pin is connected to the control unit 230, and is configured to: and receiving the control command.

Illustratively, referring to fig. 3, the target chip 240 is the functional chip in fig. 3, the reset unit 210 is the reset IC in fig. 3, the control unit 230 is the SOC in fig. 3, the first pin is shown as 310, and the second pin is shown as 320.

In an exemplary embodiment, the isolation feedback initialization circuit further includes: the temperature control device comprises a temperature detection unit connected with the feedback unit and a temperature control unit connected with the feedback unit.

The temperature detection unit is configured to: the ambient temperature at which the reset unit 110 is located is detected.

The temperature control unit is configured to: and under the condition that the environment temperature is out of a preset temperature range, adjusting the environment temperature to be within the preset temperature range.

Wherein the ambient temperature is a temperature within 2 cm from the reset unit. The temperature control unit includes but is not limited to: infrared temperature measuring devices, or thermistors.

Through the scheme, the ambient temperature of the reset unit can be controlled within a preset temperature range, so that the normal work of the reset unit is not influenced by the temperature.

In an exemplary embodiment, the temperature detecting unit includes: an alarm.

The alarm is used for: and sending alarm information under the condition that the environment temperature is higher than the dangerous temperature so as to enable a user to disconnect the power supply of the isolation feedback type initialization circuit. The above-mentioned alarm includes but is not limited to: voice alarm device, light alarm device.

Through the scheme, the working environment temperature of the isolation feedback type initialization circuit is monitored in real time and subjected to temperature early warning, and the probability of circuit board damage caused by overhigh environment temperature is reduced.

Illustratively, the temperature control unit has a power self-regulating function, and when the temperature detection unit detects that the temperature of the chip is too high, the operating frequency of the chip can be reduced, so as to reduce the temperature.

For example, the temperature control unit may be externally connected with an air-cooled heat sink, a water-cooled heat sink, or a temperature-raising resistor. Assuming that the preset working temperature range of the reset unit is 5 to 50 degrees, when the temperature detection unit detects that the ambient temperature is 0 degree, the temperature control unit starts the temperature-increasing resistor to increase the ambient temperature to the preset working temperature range. When the temperature detection unit detects that the ambient temperature is 60 ℃, the temperature control unit starts the air-cooled radiator or the water-cooled radiator so as to reduce the ambient temperature to a preset working temperature range.

In an exemplary embodiment, the feedback unit includes: a photoelectric converter.

The photoelectric converter is configured to: and receiving a light source of an external environment where the isolation feedback type initialization circuit is positioned, converting the light source into electric energy and supplying power to the temperature control unit.

Exemplarily, the feedback unit further includes: and the energy storage battery is connected with the photoelectric converter. The energy storage battery is used for: the energy collected by the photoelectric converter is stored, so that the isolation feedback type initialization circuit has independent power supply, and the working stability of the circuit is improved.

In an exemplary embodiment, the feedback unit includes: a timer.

The timer is configured to: and acquiring the reset state of the target chip and timing the reset time of the target chip. Wherein, the reset time means: the time taken for the reset signal to transition from a low level to a high level.

By the scheme, the reset time of the target chip can be monitored, so that a user can visually find that the reset time of the target chip is abnormal, and the user is reminded to detect the working state and working environment of the reset unit.

In an exemplary embodiment, the feedback unit includes: and resetting the control for the second time.

The secondary reset control is configured to: acquiring the reset state of the target chip by taking a preset time interval as a period, and sending a reset signal to the target chip under the condition that the reset state is reset failure; and stopping sending the reset signal to the target chip when the reset state is the successful reset.

For example, the on or off of the secondary reset control may be set by a user in advance.

By the scheme, the abnormal condition of the working state of the chip caused by the failure of chip reset can be solved.

The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.

An embodiment of the present disclosure further provides an electronic device, where the electronic device includes the isolation feedback type initialization circuit in any of the embodiments.

FIG. 4 schematically illustrates a block diagram of an electronic device in an exemplary embodiment according to the present disclosure. Referring to fig. 4, the electronic device 400 includes the isolated feedback initialization circuit according to the above embodiment. That is to say, the electronic device adopts the isolation feedback type initialization circuit and has the corresponding technical effect.

Exemplary, the electronic devices include, but are not limited to: the intelligent mobile phone comprises a smart mobile phone, a smart tablet and intelligent electrical equipment with a reset function. The working principle and technical effect of the above-mentioned electronic device using the above-mentioned isolation feedback type initialization circuit are the same as those described in the above-mentioned embodiments, and are not described herein again.

Claims

1. An isolated feedback initialization circuit, comprising:

a reset unit for: generating a reset signal and sending the reset signal to a target chip to reset the target chip;

a feedback unit connected to the reset unit, for: acquiring the level state of the reset signal, and generating a control signal according to the level state;

a control unit connected to the feedback unit for: sending a control instruction to the target chip according to the control signal;

the temperature detection unit is connected with the feedback unit and is used for: detecting the ambient temperature of the reset unit;

and a temperature control unit connected to the feedback unit for: and under the condition that the environment temperature is out of a preset temperature range, adjusting the environment temperature to be within the preset temperature range.

2. The isolated feedback initialization circuit of claim 1, wherein the feedback unit comprises:

a power supply, an N-channel type field effect transistor, and a resistor;

the power supply is connected to the grid electrode of the N-channel type field effect transistor, and the resistor is connected between the grid electrode of the N-channel type field effect transistor and the drain electrode of the N-channel type field effect transistor in parallel;

the source electrode of the N-channel type field effect transistor is connected to the reset unit, and the drain electrode of the N-channel type field effect transistor is connected to the control unit.

3. The isolated feedback initialization circuit of claim 1, wherein the control unit comprises: a detection subunit;

the detection subunit is configured to: and detecting the level of the control signal, and sending a control instruction to the target chip when the level is changed from low level to high level.

4. The isolated feedback initialization circuit of claim 1, wherein the target chip comprises: a first pin and a second pin;

wherein the first pin is connected to the reset unit and configured to: receiving the reset signal;

the second pin is connected with the control unit and is used for: and receiving the control instruction.

5. The isolated feedback initialization circuit of claim 1, wherein the ambient temperature is a temperature within 2 centimeters from the reset unit.

6. The isolated feedback initialization circuit of claim 1, wherein the temperature detection unit comprises: an alarm;

the alarm is used for: and sending alarm information under the condition that the environment temperature is higher than the dangerous temperature so as to enable a user to disconnect the power supply of the isolation feedback type initialization circuit.

7. The isolated feedback initialization circuit of claim 1, wherein the feedback unit comprises: a photoelectric converter;

the photoelectric converter is used for: and receiving a light source of the external environment where the isolation feedback type initialization circuit is located, converting the light source into electric energy, and supplying power to the temperature control unit.

8. The isolated feedback initialization circuit of claim 1, wherein the feedback unit comprises: a timer;

the timer is configured to: acquiring the reset state of the target chip, and timing the reset time of the target chip;

the reset time refers to: the time it takes for the reset signal to transition from a low level to a high level.

9. The isolated feedback initialization circuit of any of claims 1-8, wherein the feedback unit comprises: a secondary reset control;

the secondary reset control is configured to: acquiring a reset state of the target chip by taking a preset time interval as a period, and sending a reset signal to the target chip under the condition that the reset state is reset failure;

and stopping sending a reset signal to the target chip under the condition that the reset state is the successful reset.

10. An electronic device, characterized in that the electronic device comprises an isolated feedback initialization circuit according to any of claims 1 to 9.