CN218005924U - Battery backup unit - Google Patents

Abstract

The utility model provides a battery backup unit, including main control chip, power state collection module and communication circuit, wherein, power state collection module electricity is connected between battery backup unit's power and main control chip for gather the state of power and transmit to main control chip, main control chip disposes the communication pin, and connect communication circuit through the communication pin electricity, communication circuit's output is applicable to the status signal of the power that output main control chip obtained, like this, alright in time read the operating condition of power from main control chip through communication circuit.

Description

Battery backup unit

Technical Field

The present disclosure relates to the field of power supply technologies, and in particular, to a battery backup unit.

Background

On the storage server, reliability of the data is particularly important. In order to ensure that data on the storage server is not lost, a Battery Backup Unit (BBU) is mostly configured on the storage server. Under the condition that the mains supply is powered off, the BBU supplies power to the storage server to maintain the storage of normal service data of the system and avoid data loss. However, the existing BBU does not have a communication function, and the working state of the BBU is not convenient to acquire in time.

Disclosure of Invention

In view of this, the present disclosure provides a battery backup unit, which has a communication function, and therefore, can acquire an operating state of an internal power supply in time.

According to a first aspect of the present disclosure, there is provided a battery backup unit comprising: the power supply state acquisition module is connected with the master control chip;

the power state acquisition module is electrically connected between a power supply of the battery backup unit and the main control chip and is used for acquiring the state of the power supply and transmitting the state to the main control chip;

the main control chip is provided with a communication pin and is electrically connected with the communication circuit through the communication pin;

and the output end of the communication circuit is suitable for outputting the state signal of the power supply acquired by the main control chip.

In one possible implementation, the power state acquisition module includes a voltage sampling circuit;

the input end of the voltage sampling circuit is electrically connected to two ends of the power supply, and the output end of the voltage sampling circuit is electrically connected to the voltage input pin of the main control chip.

In a possible implementation manner, when the power supply includes at least two single batteries, the voltage sampling circuit correspondingly includes at least two voltage sampling sub-circuits;

and each voltage sampling sub-circuit is arranged in one-to-one correspondence with each single battery.

In a possible implementation manner, when the power supply includes three single batteries connected in series, the voltage sampling circuit includes a first voltage sampling sub-circuit, a second voltage sampling sub-circuit, and a third voltage sampling sub-circuit, and the main control chip is configured with a VC1 pin, a VC2 pin, and a VC3 pin;

the first voltage sampling sub-circuit comprises a first resistor and a first capacitor, the first resistor is electrically connected between the positive terminal of the first single battery and the VC1 pin, and the VC1 pin is grounded through the first capacitor;

the second voltage sampling sub-circuit comprises a second resistor and a second capacitor, the second resistor is electrically connected between the positive terminal of the second single battery and the VC2 pin, and the VC2 pin is also electrically connected to the VC1 pin through the second capacitor;

the third voltage sampling sub-circuit comprises a third resistor and a third capacitor, the third resistor is electrically connected between the positive terminal of a third single battery and the VC3 pin, and the VC3 pin is also electrically connected to the VC2 pin through the third capacitor.

In one possible implementation, the power state acquisition module includes a current sampling circuit;

the current sampling circuit includes: the master control chip is provided with an SRP pin and an SRN pin;

a first end of the fourth resistor is electrically connected to a negative end of the power supply, and a second end of the fourth resistor is grounded as a ground port of the battery backup unit;

the fifth resistor is electrically connected between the SRP pin and a first end of the fourth resistor;

the sixth resistor is electrically connected between the SRN pin and the second end of the fourth resistor;

the fourth capacitor is electrically connected between the SRP pin and the SRN pin;

and the SRP pin and the SRN pin are also grounded through the fifth capacitor and the sixth capacitor respectively.

In one possible implementation, the battery backup unit further includes a temperature sampling circuit;

the temperature sampling circuit comprises a first thermistor, a second thermistor and a third thermistor, and the main control chip is provided with a TS1 pin, a TS2 pin and a TS3 pin;

the TS1 pin, the TS2 pin and the TS3 pin are grounded through the first thermistor, the second thermistor and the third thermistor respectively.

In one possible implementation manner, the communication circuit comprises a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first zener diode and a second zener diode, and the communication pins comprise an SMBC pin and an SMBD pin;

the SMBC pin is electrically connected to a first end of the seventh resistor, a second end of the seventh resistor is electrically connected to a first end of the eighth resistor, a second end of the eighth resistor is used as a first output end of the communication circuit, and a second end of the seventh resistor is grounded through a first voltage stabilizing diode;

the SMBD pin is electrically connected with a first end of the ninth resistor, a second end of the ninth resistor is electrically connected with a first end of the tenth resistor, a second end of the tenth resistor serves as a second output end of the communication circuit, and the second end of the ninth resistor is grounded through a second voltage stabilizing diode.

In one possible implementation, the battery backup unit further includes a power control circuit;

the power supply control circuit comprises a first field effect tube, a second field effect tube, a third field effect tube, a fourth field effect tube, a resistor and a capacitor, and the main control chip is provided with a PCHG pin, a DSG pin and a CHG pin;

the grids of the first field effect transistor, the second field effect transistor and the third field effect transistor are electrically connected to the PCHG pin, the DSG pin and the CHG pin respectively through resistors;

resistors are respectively electrically connected among the grid electrodes and the source electrodes of the first field effect tube, the second field effect tube and the third field effect tube;

the source electrode of the second field effect transistor is set as the anode of the battery backup unit, the drain electrode of the second field effect transistor is electrically connected to the drain electrode of the third field effect transistor, and the source electrode of the third field effect transistor is electrically connected to the anode end of the power supply; a series capacitor is arranged in parallel between the source electrode of the second field effect transistor and the source electrode of the third field effect transistor;

the source electrode of the first field effect transistor is electrically connected to the drain electrode of the second field effect transistor, and the drain electrode of the first field effect transistor is electrically connected to the source electrode of the third field effect transistor through a resistor;

the grid electrode of the fourth field effect transistor is grounded through a resistor, the source electrode of the fourth field effect transistor is electrically connected to the source electrode of the second field effect transistor, and the drain electrode of the fourth field effect transistor is electrically connected to the grid electrode of the second field effect transistor.

In one possible implementation, the battery backup unit further includes an overvoltage protection circuit;

the overvoltage protection circuit comprises an overvoltage protection chip, a fifth field effect transistor, a three-terminal fuse, a resistor and a capacitor, wherein the overvoltage protection chip is provided with a VDD pin, an OUT pin, a V1 pin, a V2 pin, a V3 pin, an REG pin, a VSS pin and a PWPD pin;

a first end of the three-terminal fuse is electrically connected to a source electrode of the third field effect transistor, a second end of the three-terminal fuse is electrically connected to a positive electrode end of the power supply, and a third end of the three-terminal fuse is electrically connected to a drain electrode of the fifth field effect transistor;

the source electrode of the fifth field effect transistor is grounded, and the grid electrode of the fifth field effect transistor is grounded through a resistor and a capacitor which are connected in parallel;

the VDD pin is electrically connected to the positive terminal of the power supply through a resistor, the VDD pin is also grounded through a capacitor, and the OUT pin is electrically connected to the grid electrode of the fifth field-effect tube through a resistor;

the V1 pin is electrically connected to the positive terminal of the first single battery through an eleventh resistor, and the V1 pin is grounded through a seventh capacitor; the V2 pin is electrically connected to the positive end of the second single battery through a twelfth resistor, and the V2 pin is also electrically connected to the V1 pin through an eighth capacitor; the V3 pin is electrically connected to the positive terminal of the third single battery through a thirteenth resistor, and the V3 pin is also electrically connected to the V2 pin through a ninth capacitor;

the REG pin is grounded through a resistor and a capacitor which are connected in parallel, and the VSS pin and the PWPD pin are grounded.

In one possible implementation, the battery backup unit further includes a charging display circuit;

the main control chip is provided with a display control pin and is electrically connected to the charging display circuit through the display control pin.

In this disclosure, the battery backup unit includes main control chip, power state collection module and communication circuit, wherein, power state collection module electricity is connected between the power and the main control chip of battery backup unit, a state for gathering the power is transmitted to main control chip, main control chip disposes the communication pin, and connect communication circuit through the communication pin electricity, communication circuit's output is applicable to the state signal of the power that output main control chip obtained, like this, alright in time read the operating condition of power in following main control chip through communication circuit.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 illustrates a circuit diagram of a battery backup unit of an embodiment of the present disclosure;

FIG. 2 shows a circuit diagram of a voltage sampling circuit of an embodiment of the present disclosure;

FIG. 3 illustrates a circuit diagram of a current sampling circuit of an embodiment of the present disclosure;

FIG. 4 shows a circuit diagram of a temperature sampling circuit of an embodiment of the present disclosure;

fig. 5 shows a circuit diagram of a communication circuit of an embodiment of the present disclosure;

FIG. 6 shows a circuit diagram of a power control circuit of an embodiment of the present disclosure;

FIG. 7 shows a circuit diagram of an over-voltage protection circuit of an embodiment of the present disclosure;

fig. 8 shows a circuit diagram of a charging display circuit according to an embodiment of the disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

It will be understood, however, that the terms "central," "longitudinal," "lateral," "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing or simplifying the description, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the subject matter of the present disclosure.

Fig. 1 shows a circuit diagram of a battery backup unit of an embodiment of the present disclosure. As shown in fig. 1, the battery backup unit includes a main control chip 110, a power state acquisition module, and a communication circuit 130. The power state acquisition module is electrically connected between the power source 120 of the battery backup unit and the main control chip 110, and is configured to acquire a working state of the power source 120 and transmit the working state to the main control chip 110, where the acquired working state of the power source 120 may include at least one of a voltage signal, a current signal, and a temperature signal. The main control chip 110 is configured with a communication pin and is electrically connected to the communication circuit 130 through the communication pin, and an output end of the communication circuit 130 is adapted to output a state signal of the power supply 120 acquired by the main control chip 110, so that the working state of the power supply 120 can be read from the main control chip in time through the communication circuit.

In one possible implementation, the power state acquisition module may include a voltage sampling circuit 140. The input end of the voltage sampling circuit 140 is electrically connected to the two ends of the power supply 120, and the output end of the voltage sampling circuit 140 is electrically connected to the voltage input pin of the main control chip 110, so that the voltage sampling circuit 140 can obtain the voltage signal of the power supply 120 and transmit the voltage signal to the main control chip 110 for storage. The power source 120 may be a single lithium battery, or may be a battery pack formed by connecting at least two lithium batteries in series, which is not limited herein.

When the power source 120 includes at least two single batteries, the voltage sampling circuit 140 correspondingly includes at least two voltage sampling sub-circuits, wherein each voltage sampling sub-circuit is arranged in one-to-one correspondence with each single battery, so that the voltage signals of at least two single batteries can be respectively sampled by the at least two voltage sampling sub-circuits.

For example, the power supply 120 includes three battery cells connected in series, which are a first battery cell BAT1, a second battery cell BAT2, and a third battery cell BAT3, wherein a negative terminal of the first battery cell BAT1 is used as a negative terminal of the power supply 120, and a positive terminal of the third battery cell BAT3 is used as a positive terminal of the power supply 120.

In this implementation manner, in order to sample the voltage signals of the three single batteries respectively, the voltage sampling circuit 140 may specifically include a first voltage sampling sub-circuit, a second voltage sampling sub-circuit, and a third voltage sampling sub-circuit as shown in fig. 2, and the corresponding main control chip 110 is configured with at least three voltage sampling pins, a VC1 pin, a VC2 pin, and a VC3 pin.

The first voltage sampling sub-circuit includes a first resistor R11 and a first capacitor C9, the first resistor R11 is connected between the positive terminal of the first battery cell BAT1 and the VC1 pin of the main control chip 110, and the VC1 pin is grounded through the first capacitor C9.

The second voltage sampling sub-circuit includes a second resistor R12 and a second capacitor C10, the second resistor R12 is electrically connected between the positive terminal of the second battery cell BAT2 and the VC2 pin of the main control chip 110, and the VC2 pin is electrically connected to the VC1 pin through the second capacitor C10.

The third voltage sampling sub-circuit includes a third resistor R13 and a third capacitor C11, the third resistor R13 is electrically connected between the positive terminal of the third battery cell BAT3 and the VC3 pin of the main control chip 110, and the VC3 pin is electrically connected to the VC2 pin through the third capacitor C11.

When the main control chip 110 is further configured with a voltage sampling pin VC4, the voltage sampling pin VC4 can be electrically connected to the voltage sampling pin VC3, and then used as a voltage sampling pin.

In a possible implementation manner, the power state collecting module may further include a current sampling circuit 150, so as to collect a current signal of the power source 120 through the current sampling circuit 150, and transmit the current signal to the main control chip 110 and store the current signal.

In this implementation, the current sampling circuit 150 may specifically include, as shown in fig. 3: a fourth resistor R10, a fifth resistor R8, a sixth resistor R9, a fourth capacitor C7, a fifth capacitor C15, and a sixth capacitor C17, and the corresponding main control chip 110 is further configured with at least two current sampling pins, which are an SRP pin and an SRN pin, respectively.

A first end of the fourth resistor R10 is electrically connected to the negative terminal of the power supply 120, and a second end of the fourth resistor R10 is grounded as a ground port of the battery backup unit, wherein when the output port of the battery backup unit includes six connection terminals J1-1 to J1-6, two connection terminals J1-5 and J1-6 may be electrically connected to serve as the ground port of the battery backup unit.

The fifth resistor R8 is electrically connected between the SRP pin of the main control chip and the first end of the fourth resistor R10, the sixth resistor R9 is electrically connected between the SRN pin of the main control chip and the second end of the fourth resistor R10, the fourth capacitor is electrically connected between the SRP pin and the SRN pin of the main control chip, and the SRP pin and the SRN pin of the main control chip are further grounded through a fifth capacitor C15 and a sixth capacitor C17, respectively.

In a possible implementation manner, the battery backup unit may further include a temperature sampling circuit 160, so as to collect a temperature signal of the power source 120 through the temperature sampling circuit 160, and transmit the temperature signal to the main control chip 110 and store the temperature signal.

In this implementation manner, the temperature sampling circuit 160 may specifically include, as shown in fig. 4: the first thermistor RT1, the second thermistor RT2, and the third thermistor RT3, and the corresponding main control chip 110 are further configured with at least three temperature sampling pins, which are a TS1 pin, a TS2 pin, and a TS3 pin, respectively. The TS1 pin of the main control chip 110 is grounded through the first thermistor RT1, the TS2 pin of the main control chip 110 is grounded through the second thermistor RT2, and the TS3 pin of the main control chip 110 is grounded through the third thermistor RT 3.

When the temperature sampling pin of the main control chip 110 further includes a TS4 pin and an NC pin, the TS4 pin and the NC pin may be directly grounded.

In a possible implementation manner, the communication circuit 130 may be as shown in fig. 5, and specifically includes: a seventh resistor R14, an eighth resistor R27, a ninth resistor R15, a tenth resistor R28, a first zener diode D1, and a second zener diode D2, and the corresponding communication pins of the main control chip 110 include an SMBC pin and an SMBD pin.

The SMBC pin of the main control chip 110 is electrically connected to the first end of the seventh resistor R14, the second end of the seventh resistor R14 is electrically connected to the first end of the eighth resistor R27, the second end of the eighth resistor R27 is used as the first output end of the communication circuit 130, and the second end of the seventh resistor R14 is further grounded through the first zener diode D1. When the output port of the battery backup unit includes six connection terminals J1-1 to J1-6, the first output terminal of the communication circuit 130 is the first communication terminal J1-3 of the battery backup unit.

The SMBD pin of the main control chip is electrically connected to the first end of the ninth resistor R15, the second end of the ninth resistor R15 is electrically connected to the first end of the tenth resistor R28, the second end of the tenth resistor R28 is used as the second output end of the communication circuit, and the second end of the ninth resistor R15 is further grounded through the second zener diode D2. When the output port of the battery backup unit includes six connection terminals J1-1 to J1-6, the second output terminal of the communication circuit 130 is the second communication terminal J1-4 of the battery backup unit.

In one possible implementation, the battery-backup unit further includes a power control circuit 170. As shown in fig. 6, the power control circuit 170 may specifically include: the first field effect transistor Q1, the second field effect transistor Q2, the third field effect transistor Q3, the fourth field effect transistor Q4, the resistance and the capacitance, the corresponding main control chip 110 is configured with at least three charge and discharge control pins, which are a PCHG pin, a DSG pin and a CHG pin respectively.

The first fet Q1 is electrically connected to the PCHG pin of the main control chip 110 through a resistor R23, the second fet Q2 is electrically connected to the DSG pin of the main control chip 110 through a resistor R25, and the gate of the third fet Q3 is electrically connected to the CHG pin of the main control chip 110 through a resistor R18. And a resistor R22, a resistor R20 and a resistor R17 are respectively electrically connected among the grid electrodes and the source electrodes of the first field-effect tube Q1, the second field-effect tube Q2 and the third field-effect tube Q3 so as to ensure that the first field-effect tube Q1, the second field-effect tube Q2 and the third field-effect tube Q3 can be completely closed when the driving is not performed.

The source of the second field effect transistor Q2 is set as the positive electrode of the battery backup unit, and when the output port of the battery backup unit includes six connection terminals J1-1 to J1-6, the two connection terminals J1-1 and J1-2 can be electrically connected to serve as the positive electrode port of the battery backup unit. The drain of the second fet Q2 is electrically connected to the drain of the third fet Q3, and the source of the third fet Q3 is electrically connected to the positive terminal of the power supply 120. A capacitor C14 and a capacitor C13 which are connected in series are arranged between the source electrode of the second field effect transistor Q2 and the source electrode of the third field effect transistor Q3 in parallel, so that the second field effect transistor Q2 and the third field effect transistor Q3 are protected when the ESD impact happens. The source of the first fet Q1 is electrically connected to the drain of the second fet Q2, the drain of the first fet Q1 is electrically connected to the source of the third fet Q3 through a resistor R21, and the source of the second fet Q2 is also connected to ground through series connected capacitors C16 and C18.

The grid electrode of the fourth field effect transistor Q4 is grounded through a resistor R19, the source electrode of the fourth field effect transistor Q4 is electrically connected to the source electrode of the second field effect transistor Q2, and the drain electrode of the fourth field effect transistor Q4 is electrically connected to the grid electrode of the second field effect transistor Q2.

It should be noted that, the main control chip 110 is further configured with a PACK pin, the PACK pin is electrically connected to the source of the second fet Q2 through a resistor R26 to collect the input voltage of the positive terminal of the battery backup unit, and when the main control chip 110 determines that the voltage at the positive terminal of the power supply 120 is lower than the voltage at the positive terminal of the battery backup unit (i.e., meets the charging condition), high voltages are respectively input to the gates of the second fet Q2 and the third fet Q3 through the DSG pin and the CHG pin to turn on the second fet Q2 and the third fet Q3, so that the power supply 120 can be charged through the input voltage at the positive terminal of the battery backup unit. When the voltage of the positive terminal of the power supply 120 is higher than the voltage of the positive terminal of the battery backup unit (i.e., the discharge condition is satisfied), the second field effect transistor Q2 and the third field effect transistor Q3 are still in a conducting state, and at this time, the power supply 120 can output the supply voltage to the electric equipment through the path formed by the second field effect transistor Q2 and the third field effect transistor Q3. When the main control chip judges that the voltage of the positive terminal of the power supply 120 is lower than the discharge protection voltage or higher than the charge protection voltage, low voltages are respectively input to the gates of the second field-effect tube Q2 and the third field-effect tube Q3 through the DSG terminal and the CHG terminal, so that the second field-effect tube Q2 and the third field-effect tube Q3 are turned off, and then the overcharge and the overdischarge of the power supply 120 are prevented, so that the service life of the power supply 120 is prolonged.

In this implementation manner, the main control chip 110 is further configured with two power supply pins, which are a VCC pin and a BAT pin, respectively, where the VCC pin is electrically connected to the drain of the second field effect transistor Q2 through a resistor R24, and the BAT pin is electrically connected to the positive terminal of the power supply 120 through a third zener diode D3, so that when the voltage ratio of the power supply 120 is higher (e.g., the voltage is greater than 3.1V), power can be supplied to the main control chip 110 mainly through the power supply 120; when the voltage of the power supply 120 is too low (e.g., less than 2.1V), since the VCC pin can take power from the positive electrode of the battery backup unit, even if the voltage of the power supply 120 is too low to operate the main control chip 110, the main control chip 110 can still operate by supplying power through the VCC pin as long as the charger is inserted.

In one possible implementation, the battery-backup unit further includes an overvoltage protection circuit 180.

When the power supply 120 includes 3 serially connected single batteries, the overvoltage protection circuit 180 may specifically include, as shown in fig. 7: the overvoltage protection circuit comprises an overvoltage protection chip, a fifth field effect transistor Q5, a three-terminal fuse, a resistor and a capacitor, wherein the overvoltage protection chip is provided with a VDD pin, an OUT pin, a V1 pin, a V2 pin, a V3 pin, an REG pin, a VSS pin and a PWPD pin.

The first end of the three-terminal fuse is electrically connected to the source electrode of the third field effect transistor Q3, the second end of the three-terminal fuse is electrically connected to the positive electrode terminal of the power supply 120, the third end of the three-terminal fuse is electrically connected to the drain electrode of the fifth field effect transistor Q5, the source electrode of the fifth field effect transistor Q5 is grounded, and the grid electrode of the fifth field effect transistor Q5 is grounded through the resistor R5 and the capacitor C12 which are connected in parallel.

The VDD pin of the overvoltage protection chip is electrically connected to the positive terminal of the power supply 120 through a resistor R4, the VDD pin is also grounded through a capacitor C5, and the OUT pin is electrically connected to the gate of the fifth field effect transistor Q5 through a resistor R6. The V1 pin is electrically connected to the positive terminal of the first battery cell BAT1 through an eleventh resistor R3, and the V1 pin is also grounded through a seventh capacitor C2. The V2 pin is electrically connected to the positive terminal of the second battery cell BAT2 through a twelfth resistor R2, and the V2 pin is also electrically connected to the V1 pin through an eighth capacitor C3. The V3 pin is electrically connected to the positive terminal of the third battery cell BAT3 through a thirteenth resistor R1, and the V3 pin is also electrically connected to the V2 pin through a ninth capacitor C4. The REG pin is grounded through a resistor R5 and a capacitor C2 which are connected in parallel, and the VSS pin and the PWPD pin are grounded.

In this implementation, the overvoltage protection chip respectively collects the voltages of the first battery cell BAT1, the second battery cell BAT2 and the third battery cell BAT3 through the V1 pin, the V2 pin and the V3 pin, when the voltage of any battery cell is greater than a preset threshold (such as 4.35V), the overvoltage protection chip outputs a high voltage through the OUT pin, so that the fifth field effect transistor Q5 is turned on, the third end of the three-end fuse is grounded, and the fuse F1 is fused due to heating, thereby realizing overvoltage protection of the power supply 120. In this implementation, the overvoltage protection of the power supply 120 is triggered by hardware, so that the overvoltage protection is safer and more reliable.

In one possible implementation, the model of the overvoltage protection chip may be BQ296103DSGT.

In a possible implementation manner, the battery backup unit may further include a charging display circuit 190, and the charging display circuit 190 may be as shown in fig. 8, which specifically includes: the main control chip 110 is configured with three display control pins, namely an led cltla pin, an led cltlb pin and an led cltlc pin, corresponding to the light emitting diodes D4, D5, D6, D7 and D8.

The cathode of the led D5 is electrically connected to the LEDCNTLA pin of the main control chip 110, the anode is electrically connected to the cathode of the led D7, and the anode of the led D7 is electrically connected to the LEDCNTLC pin of the main control chip 110. The anode of the led D4 is electrically connected to the cathode of the led D5, the cathode is electrically connected to the anode of the led D6, and the anode of the led D6 is electrically connected to the anode of the led D7. The cathode of the led D8 is electrically connected to the cathode of the led D5, and the anode is electrically connected to the anode of the led D7. The LEDCNTLB terminal of the main control chip 110 is electrically connected with the anode of the light emitting diode D5 and the cathode of the light emitting diode D4.

The main control chip 110 further has a DISP pin, and the DISP pin is grounded through a resistor R30 as a trigger terminal of the charging display module 190.

The charging display circuit 190 may indicate the charge amount SOC and the fault information of the power source 120 according to the electrical signal of the main chip 110.

In one possible implementation, the model of the main control chip 110 may be BQ40Z50.

In the implementation mode, the FBI pin of the main control chip is grounded through a capacitor C1, the PWPD pin, the NC-1 pin, the VSS pin, the PTC pin, the PTCEN pin, the PUSE pin and the NC-2 pin are all grounded, the BTP INT pin is grounded through a resistor R29, and the PRES/SHUTDN pin is grounded through a capacitor C8.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. A battery backup unit, comprising: the power supply state acquisition module is connected with the master control chip;

the power state acquisition module is electrically connected between a power supply of the battery backup unit and the main control chip and is used for acquiring the state of the power supply and transmitting the state to the main control chip;

the main control chip is provided with a communication pin and is electrically connected with the communication circuit through the communication pin;

and the output end of the communication circuit is suitable for outputting the state signal of the power supply acquired by the main control chip.

2. The battery backup unit of claim 1, wherein the power state acquisition module comprises a voltage sampling circuit;

the input end of the voltage sampling circuit is electrically connected to two ends of the power supply, and the output end of the voltage sampling circuit is electrically connected to the voltage input pin of the main control chip.

3. The battery backup unit of claim 2, wherein when the power supply comprises at least two cells, the voltage sampling circuit comprises at least two voltage sampling sub-circuits;

and each voltage sampling sub-circuit is arranged in one-to-one correspondence with each single battery.

4. The battery backup unit according to claim 3, wherein when the power supply comprises three cells connected in series, the voltage sampling circuit comprises a first voltage sampling sub-circuit, a second voltage sampling sub-circuit and a third voltage sampling sub-circuit, and the main control chip is configured with a VC1 pin, a VC2 pin and a VC3 pin;

the first voltage sampling sub-circuit comprises a first resistor and a first capacitor, the first resistor is electrically connected between the positive terminal of the first single battery and the VC1 pin, and the VC1 pin is grounded through the first capacitor;

the second voltage sampling sub-circuit comprises a second resistor and a second capacitor, the second resistor is electrically connected between the positive terminal of the second single battery and the VC2 pin, and the VC2 pin is also electrically connected to the VC1 pin through the second capacitor;

the third voltage sampling sub-circuit comprises a third resistor and a third capacitor, the third resistor is electrically connected between the positive terminal of the third single battery and the VC3 base pin, and the VC3 base pin is electrically connected to the VC2 base pin through the third capacitor.

5. The battery backup unit of claim 1, wherein the power state acquisition module comprises a current sampling circuit;

the current sampling circuit includes: the master control chip is provided with an SRP pin and an SRN pin;

a first end of the fourth resistor is electrically connected to a negative end of the power supply, and a second end of the fourth resistor is grounded as a ground port of the battery backup unit;

the fifth resistor is electrically connected between the SRP pin and a first end of the fourth resistor;

the sixth resistor is electrically connected between the SRN pin and the second end of the fourth resistor;

the fourth capacitor is electrically connected between the SRP pin and the SRN pin;

and the SRP pin and the SRN pin are also grounded through the fifth capacitor and the sixth capacitor respectively.

6. The battery-backup unit of claim 1, further comprising a temperature sampling circuit;

the temperature sampling circuit comprises a first thermistor, a second thermistor and a third thermistor, and the main control chip is provided with a TS1 pin, a TS2 pin and a TS3 pin;

the TS1 pin, the TS2 pin and the TS3 pin are grounded through the first thermistor, the second thermistor and the third thermistor respectively.

7. The battery-backup unit of claim 1, wherein the communication circuit comprises a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first zener diode, and a second zener diode, the communication pins comprising an SMBC pin and an SMBD pin;

the SMBC pin is electrically connected to a first end of the seventh resistor, a second end of the seventh resistor is electrically connected to a first end of the eighth resistor, a second end of the eighth resistor is used as a first output end of the communication circuit, and a second end of the seventh resistor is grounded through a first voltage stabilizing diode;

the SMBD pin is electrically connected to a first end of the ninth resistor, a second end of the ninth resistor is electrically connected to a first end of the tenth resistor, a second end of the tenth resistor serves as a second output end of the communication circuit, and the second end of the ninth resistor is grounded through a second voltage stabilizing diode.

8. The battery-backup unit of claim 4, further comprising a power control circuit;

the power supply control circuit comprises a first field effect tube, a second field effect tube, a third field effect tube, a fourth field effect tube, a resistor and a capacitor, and the main control chip is provided with a PCHG pin, a DSG pin and a CHG pin;

the grid electrodes of the first field effect transistor, the second field effect transistor and the third field effect transistor are electrically connected to the PCHG pin, the DSG pin and the CHG pin respectively through resistors;

resistors are respectively and electrically connected among the grids and the sources of the first field effect tube, the second field effect tube and the third field effect tube;

the source electrode of the second field effect transistor is set as the anode of the battery backup unit, the drain electrode of the second field effect transistor is electrically connected to the drain electrode of the third field effect transistor, and the source electrode of the third field effect transistor is electrically connected to the anode end of the power supply; a series capacitor is arranged in parallel between the source electrode of the second field effect transistor and the source electrode of the third field effect transistor;

the source electrode of the first field effect transistor is electrically connected to the drain electrode of the second field effect transistor, and the drain electrode of the first field effect transistor is electrically connected to the source electrode of the third field effect transistor through a resistor;

the grid electrode of the fourth field effect transistor is grounded through a resistor, the source electrode of the fourth field effect transistor is electrically connected to the source electrode of the second field effect transistor, and the drain electrode of the fourth field effect transistor is electrically connected to the grid electrode of the second field effect transistor.

9. The battery-backup unit of claim 8, further comprising an over-voltage protection circuit;

the overvoltage protection circuit comprises an overvoltage protection chip, a fifth field effect transistor, a three-terminal fuse, a resistor and a capacitor, wherein the overvoltage protection chip is provided with a VDD pin, an OUT pin, a V1 pin, a V2 pin, a V3 pin, an REG pin, a VSS pin and a PWPD pin;

a first end of the three-terminal fuse is electrically connected to a source electrode of the third field effect transistor, a second end of the three-terminal fuse is electrically connected to a positive electrode end of the power supply, and a third end of the three-terminal fuse is electrically connected to a drain electrode of the fifth field effect transistor;

the source electrode of the fifth field effect transistor is grounded, and the grid electrode of the fifth field effect transistor is grounded through a resistor and a capacitor which are connected in parallel;

the VDD pin is electrically connected to the positive terminal of the power supply through a resistor, the VDD pin is also grounded through a capacitor, and the OUT pin is electrically connected to the grid electrode of the fifth field-effect tube through a resistor;

the V1 pin is electrically connected to the positive terminal of the first single battery through an eleventh resistor, and the V1 pin is grounded through a seventh capacitor; the V2 pin is electrically connected to the positive end of the second single battery through a twelfth resistor, and the V2 pin is also electrically connected to the V1 pin through an eighth capacitor; the V3 pin is electrically connected to the positive terminal of the third single battery through a thirteenth resistor, and the V3 pin is also electrically connected to the V2 pin through a ninth capacitor;

the REG pin is grounded through a resistor and a capacitor which are connected in parallel, and the VSS pin and the PWPD pin are grounded.

10. The battery backup unit of claim 1, further comprising a charge indication circuit;

the main control chip is provided with a display control pin and is electrically connected to the charging display circuit through the display control pin.

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