CN2179593Y - Real time tracing contrast integrated circuit testing device - Google Patents
Real time tracing contrast integrated circuit testing device Download PDFInfo
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- CN2179593Y CN2179593Y CN 93230839 CN93230839U CN2179593Y CN 2179593 Y CN2179593 Y CN 2179593Y CN 93230839 CN93230839 CN 93230839 CN 93230839 U CN93230839 U CN 93230839U CN 2179593 Y CN2179593 Y CN 2179593Y
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Abstract
The utility model relates to a real time tracing contrast measurer of an integrated circuit, which is composed of an SCM circuit, a shift register circuit, a tristate buffer circuit, a level conversion circuit, a data selector circuit, a data comparator circuit and a display circuit which are connected with each other, wherein, the level conversion circuit is provided with a measured chip interface which is connected with a measured chip; the tristate buffer circuit is provided with a standard chip interface which is connected with a standard chip, and the tristate buffer circuit is connected with a programmable modular circuit. The utility model does not need complex signal source and uses the hardware comparison to replace the software analysis. The utility model has the advantages of simple structure, complete function and convenient use.
Description
The utility model relates to a kind of real-time follow-up comparison expression measurement mechanism of integrated circuit, especially relates to the online or off-line real-time follow-up comparison expression metering circuit of a kind of digital integrated circuit chip.
Known digital IC tester, it is that integrated device to online or off-line state applies with test signal, the resulting output response signal of this device is analyzed with software, thereby whether the logic function of judging this device is normal.There are some shortcomings like this in above-mentioned surveying instrument: the one, need complicated signal source, i.e. the test signal complexity; The 2nd, to the analysis and judgement more complicated of output response signal; The 3rd, need strict control to apply the state and the character of signal during on-line testing, otherwise may damage relevant chip; The 4th, can not detect by real-time follow-up, powerless to the diagnosis of the sort of unsettled intermittent defect.
The purpose of this utility model is exactly to overcome and to avoid the shortcoming of prior art, and a kind of new real-time follow-up comparison expression arrangement for testing integrated circuit is provided, and this device does not need complicated signal source, and exciting signal source is directly from original machine; Simultaneously, also do not need that complicated software analysis is carried out in the output response and judge, but directly relatively replace software analysis with hardware; This device should be able to carry out the real-time follow-up test to chip in addition, diagnoses indication immediately to unsettled intermittent defect occurring, and this apparatus structure is simple, and is multiple functional, should be able to improve test speed, and can be adapted to the high-frequency test of integrated circuit, easy to use.
The utility model is to adopt following measure to realize its purpose.
The utility model is by single chip circuit, shift-register circuit, three-state buffer circuit, level-conversion circuit, data selector circuit, data comparator circuit and display circuit are formed by connecting, and level-conversion circuit is provided with the chip under test interface that is connected with chip under test, and three-state buffer circuit is provided with the standard chips interface that is connected with standard chips.Three-state buffer circuit is connected with the programmable module circuit.And single chip circuit is to be made of integrated chip 8751, shift-register circuit is to be made of integrated chip 9125, three-state buffer circuit is to be made of integrated chip 74HC125, level-conversion circuit is to be made of integrated chip LM324 and 74HC4050, data selector circuit is to be made of integrated chip 74HC157, the data comparator circuit is to be made of integrated chip 74HC688, and display circuit is to be made of integrated chip 74HC00 and light emitting diode.The programmable module circuit is by integrated chip ISPGAL16Z8, integrated chip 74HC164,9125 and CD4067 connect and compose.The chip under test interface is connected with standard chips interface or programmable module circuit interface with three-state buffer circuit by level-conversion circuit.Singlechip chip 8751 is connected with RS-232 interface by the level shifting circuit of being made up of integrated chip MC1489 and UA1488.
The drawing of accompanying drawing is described as follows:
Fig. 1 is a circuit side connector block diagram of the present utility model,
Fig. 2 is connection side's block diagram of programmable module circuit,
Fig. 3 is level-conversion circuit figure,
Fig. 4 is three-state buffer circuit figure,
Fig. 5 is single chip circuit, communication interface circuit and shift-register circuit figure,
Fig. 6 is data selector, data comparator and display circuit figure,
Fig. 7, Fig. 8, Fig. 9, Figure 10 connect and compose the programmable module circuit diagram,
Figure 11 be with universal microcomputer that RS-232 interface links to each other in the process flow diagram of supervisory routine,
Figure 12 is the process flow diagram of single-chip microcomputer internal processes.
Below in conjunction with accompanying drawing the utility model is described further.
The utility model is by single chip circuit (DP), shift-register circuit (YG), three-state buffer circuit (SH), level-conversion circuit (DB), data selector circuit (SX), data comparator circuit (SB) and display circuit (XS) are formed by connecting, and level-conversion circuit (DB) is provided with a chip under test interface (G who is connected with chip under test1), three-state buffer circuit (SH) is provided with the standard chips interface (G that is connected with standard chips2), three-state buffer circuit (SH) is connected with programmable module circuit (KB). Single chip circuit (DP) is by collection Become chip 8751 to consist of, shift-register circuit (YG) is to be made of two integrated chips 9125, and three-state buffer circuit (SH) is to be made of integrated chip 74HC125, and level-conversion circuit (DB) is to be made of integrated chip LM324 and 74HC4050. Data selector circuit (SX) is to be made of integrated chip 74HC157A, and data comparator circuit (SB) is to be made of integrated chip 74HC688, and display circuit (XS) is to be made of integrated chip 74HC00 and light emitting diode. Programmable module circuit (KB) is by integrated chip ISPGAL16Z8, integrated chip 74HC164,9125 and CD4067 connect and compose. Chip under test interface (G1) by level-conversion circuit (DB) and three-state buffer circuit (SH) and standard chips interface (G2) or programmable module circuit (KB) interface be connected. Singlechip chip 8751 is connected with RS-232 interface by the level shifting circuit that is made up of integrated chip MC1489 and UA1488.
The basic principle of the utility model institute foundation is: if apply simultaneously identical input stimulus for two identical digital circuits of logic function, then its output response must be identical. Otherwise if it is different to apply its output response of identical input stimulus for two logic circuits, then the logic function of these two circuit must be different.
Use this principle, for the function of surveying certain device whether normal, can get the standard chips identical with this device normal function, apply identical input signal for simultaneously this two device, their output one by one correspondence compare, can judge that the measured device function is undesired in case the level on certain output pin is inconsistent.This method can be referred to as " relative method ".Wherein standard chips can be the normal chip with former chip same model, the also emulation chip that can be made up of other chips is as coming the function of emulation chip under test with programmable logic array (PLA), programmable logic array (PAL), generic array logic (GAL), programmable gate array (PGA), FPGA (Field Programmable Gate Array) sequential machine (PLS) or some other programming device by programming.Wherein the ISPGAL16Z8 in the GAL device has on-the-spot electrically programmable characteristic, and only need+5V program voltage can be rewritten more than 10,000 times.ISPGAL16Z8 can realize the function of a large amount of small-scale digit chips by field programming, uses ISPGAL16Z8 can partly solve the trouble that a kind of slice, thin piece of every survey just needs the standard chips of a same model.
Relative method can be used for the on-line testing of digital integrated circuit.Pumping signal is directly from original machine, promptly the input signal of chip under test in the former machine works process drawn to be added on the standard chips, standard chips compared with the output of chip under test, thereby judge whether device is normal.Its advantage of the tester of this forecast scheme configuration is: do not need complicated signal source, machine originally is exactly a perfect signal source; Also do not need complicated software analysis is carried out in the output response, it has relatively replaced software analysis with hardware.Thereby the tester that constitutes in this way it is simple in structure, can survey nearly all digital device.And this method can be carried out the real-time follow-up test to device, provides indication immediately in case go wrong, and is very effective for the sort of unsettled intermittent defect.This on-line testing can be described as whole again and, because whole of the circuit at chip under test place must be connected on the original machine and will start shooting in machine test, so the test environment of chip under test is exactly its working environment, and therefore the test result that provides accurately and reliably.Test at machine with respect to this whole, relative method is equally applicable to whole off line test, be that whole of chip under test place breaks away from machine, apply power supply and test signal by tester to measured device, test signal also is added to standard chips simultaneously, the output of chip under test and standard chips is compared, thereby judges whether chip under test is normal.
Relative method also can be used for the off-line test of digital integrated circuit.At this moment need signal source that chip under test and standard chips are applied pumping signal, output is compared, thereby judges the quality of chip under test.Whether this off-line test method does not need software analysis is carried out in output response, thereby can improve test speed, normal when can the test component high frequency using.
An example of the present utility model is described below.This example is the online at the machine tester of a kind of digital integrated circuit, and it can test the following conventional chip except that memory of 16 pin.
Present embodiment uses the field programmable logic module of being made up of ISPGAL16Z8 (Programmable block) to come the function of emulation chip under test as standard chips, the chip that can not simulate for programmable module circuit (KB), then get normal chip with former device same model as standard chips, the block scheme of composition and electrical schematic diagram, program flow diagram are seen accompanying drawing.
Level-conversion circuit (LEVEL SHIFT UNIT) is called for short DB; Because chip under test may be CMOS or TTL circuit, the power supply of cmos circuit is varied again, for making the signal level coupling, need carry out level translation from the signal on the chip under test pin.Level-conversion circuit (DB) is made of LM324 and 74HC4050.Potentiometer RV1 is used for adjusting the high level thresholding according to the situation of chip under test, when the positive terminal voltage of amplifier surpasses thresholding, the high level of the approaching+15V of amplifier output, 74HC4050 is the level conversion of this approaching+15V the standard CMOS level of approaching+5V, thereby has realized the level match with back level.
Three-state buffer circuit (three-state outputs buffer ga-tes unit) is called for short SH, it is made up of 74HC125, three-state buffer is transported to the signal that belongs to input on the chip under test (having passed through level translation) on the standard chips (same model chip or programmable module), the signal that belongs to output is then isolated with standard chips, and the control signal of three-state buffer is from shift-register circuit (YG) IC22, IC23.
Universal microcomputer (MC) can be any IBMPC and compatible thereof, also can be the single-chip board of various models.The control data that has the programming data of ISPGAL16Z8 and each analog switch, data selector, three-state buffer in the universal microcomputer (MC), and supervisory routine, communication program.The supervisory routine flow process is seen accompanying drawing 11.Single-chip microcomputer 8751 is realized communication by RS-232 interface and microcomputer (MC), simultaneously the relevant controlling data is sent to each shift register and programming device ISPGAL16Z8.Single-chip microcomputer (DP) internal program flow process is seen accompanying drawing 12.Data selector IC16, IC17, IC18, IC19(74HC157) be used for the leg signal of gating programmable module circuit (KB) or standard chips and be sent to comparer IC20, IC21(74HC688) 16 bit data comparers formed, the data of data selector output are compared with chip under test leg signal data, output test result.Here the signal on all pins of chip under test and standard chips is compared simultaneously, the signal on the input pin does not influence the output result, has so just simplified circuit design.IC27B, C have formed rest-set flip-flop, and lock has instantaneous error message, button SW1 that rest-set flip-flop is resetted.The integrator that R23 and C4 form avoids occurring false triggering in order to eliminate owing to the burst pulse that signal delay produced.
The core of programmable module circuit (KB) is that logical device ISPGAL16Z8 can be compiled in a slice scene.Because the pin function of ISPGAL16Z8 can not combination in any (being that some pin can only be fixed as output or input), therefore select 1 analog switch (CD4067) to realize the corresponding one by one of 16 lead-in wires of programmable module and chip under test pin function by 18 two-way 16.Analog switch is controlled by shift register 9125 and 74HC164, and the data of shift register are from single-chip microcomputer 8751.
The utility model is simple in structure, and is multiple functional, easy to use.
Claims (6)
1, a kind of real-time follow-up comparison expression arrangement for testing integrated circuit, it is characterized in that it is by single chip circuit, shift-register circuit, three-state buffer circuit, level-conversion circuit, data selector circuit, data comparator circuit and display circuit are formed by connecting, level-conversion circuit is provided with the chip under test interface that is connected with chip under test, and three-state buffer circuit is provided with the standard chips interface that is connected with standard chips.
2, real-time follow-up comparison expression arrangement for testing integrated circuit according to claim 1 is characterized in that three-state buffer circuit is connected with the programmable module circuit.
3, real-time follow-up comparison expression arrangement for testing integrated circuit according to claim 1 and 2, it is characterized in that described single chip circuit is to be made of integrated chip 8751, shift-register circuit is to be made of integrated chip 9125, three-state buffer circuit is to be made of integrated chip 74HC125, level-conversion circuit is to be made of integrated chip LM324 and 74HC4050, data selector circuit is to be made of integrated chip 74HC157A, the data comparator circuit is to be made of integrated chip 74HC688, and display circuit is to be made of integrated chip 74HC00 and light emitting diode.
4, real-time follow-up comparison expression arrangement for testing integrated circuit according to claim 3, it is characterized in that described programmable module circuit be by integrated chip ISPGAL16Z8, integrated chip 74HC164,9125 and CD4067 connect and compose.
5, real-time follow-up comparison expression arrangement for testing integrated circuit according to claim 4 is characterized in that described chip under test interface is connected with standard chips interface or programmable module circuit interface with three-state buffer circuit by level-conversion circuit.
6, real-time follow-up comparison expression arrangement for testing integrated circuit according to claim 5 is characterized in that described singlechip chip 8751 is connected with RS-232 interface by the level shifting circuit of being made up of integrated chip MC1489 and VA1488.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 93230839 CN2179593Y (en) | 1993-04-27 | 1993-04-27 | Real time tracing contrast integrated circuit testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 93230839 CN2179593Y (en) | 1993-04-27 | 1993-04-27 | Real time tracing contrast integrated circuit testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2179593Y true CN2179593Y (en) | 1994-10-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 93230839 Expired - Fee Related CN2179593Y (en) | 1993-04-27 | 1993-04-27 | Real time tracing contrast integrated circuit testing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2179593Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108663592A (en) * | 2018-06-08 | 2018-10-16 | 河南森源电气股份有限公司 | It is a kind of to towed SVG modular debuggings platform and method |
| CN108663592B (en) * | 2018-06-08 | 2024-05-14 | 河南森源电气股份有限公司 | Opposite-dragging type SVG module debugging platform and method |
-
1993
- 1993-04-27 CN CN 93230839 patent/CN2179593Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108663592A (en) * | 2018-06-08 | 2018-10-16 | 河南森源电气股份有限公司 | It is a kind of to towed SVG modular debuggings platform and method |
| CN108663592B (en) * | 2018-06-08 | 2024-05-14 | 河南森源电气股份有限公司 | Opposite-dragging type SVG module debugging platform and method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |