CN217903115U - Substrate, circuit board and electronic equipment - Google Patents
Substrate, circuit board and electronic equipment Download PDFInfo
- Publication number
- CN217903115U CN217903115U CN202222325086.8U CN202222325086U CN217903115U CN 217903115 U CN217903115 U CN 217903115U CN 202222325086 U CN202222325086 U CN 202222325086U CN 217903115 U CN217903115 U CN 217903115U
- Authority
- CN
- China
- Prior art keywords
- layer
- fan
- sub
- out line
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application provides a base plate, circuit board and electronic equipment, the base plate includes: a base layer comprising a first surface and a second surface; a first redistribution layer on the first surface; a second redistribution layer on the second surface, wherein the line width of at least part of the fan-out lines in the first redistribution layer is smaller than the line width of at least part of the fan-out lines in the second redistribution layer; at least part of the first fan-out lines in the first redistribution layer are electrically connected with at least part of the second fan-out lines in the second redistribution layer through holes penetrating through the base layer. Through in the base plate of two-sided build-up, set up the linewidth of at least part fan-out line in the first rewiring layer to be less than the linewidth of at least part fan-out line in the second rewiring layer, so, can guarantee the fineness of wire winding line under the condition that does not increase the number that the rewiring layer piles up by a large amount to can reduce the manufacturing degree of difficulty, improve the product yield.
Description
Technical Field
The application relates to the technical field of chip manufacturing, in particular to a substrate, a circuit board and electronic equipment.
Background
With the continuous development of chip manufacturing technology, the requirements on chip size and integration level are higher and higher. However, in some scenarios, different pins of the chip need to be connected to different other devices, or pins densely arranged on the chip need to be led out and dispersed for facilitating subsequent bonding with other devices. Therefore, fan-out (fan out) of the chip pins is required. And, according to the actual use scenario, the chip may need to be fanned out in multiple layers.
In some fan-out package structures of chips, the chips may be disposed on a substrate having multiple redistribution layers, and fan-out of chip pins may be achieved through fan-out lines of the substrate. However, in the existing substrate with multiple redistribution layers, the line widths of the redistribution layers are generally the same and thicker, and if a complicated routing is to be implemented, the number of the redistribution layers to be stacked is larger, which increases the difficulty of substrate manufacturing and reduces the product yield.
SUMMERY OF THE UTILITY MODEL
In order to overcome the above-mentioned deficiencies in the prior art, the present application aims to provide a substrate, comprising:
a base layer comprising a first surface and a second surface;
a first redistribution layer on the first surface;
a second redistribution layer on the second surface, wherein the line widths of at least part of the fan-out lines in the first redistribution layer are smaller than the line widths of at least part of the fan-out lines in the second redistribution layer;
at least part of the first fan-out lines in the first redistribution layer are electrically connected with at least part of the second fan-out lines in the second redistribution layer through holes penetrating through the base layer.
In a possible implementation manner, a line width of the fan-out line on the side of the first redistribution layer far from the base layer is smaller than a line width of the fan-out line on the side of the second redistribution layer near the base layer.
In one possible implementation, the first redistribution layer includes:
a first sub-layer formed on a first surface of the base layer, the first sub-layer including a first fan-out line therein;
the first insulating layer is formed on one side, far away from the base layer, of the first sub-layer;
the second sub-layer is formed on one side, far away from the first sub-layer, of the first insulating layer and comprises a second fan-out line; at least part of the second fan-out lines are electrically connected with at least part of the first fan-out lines through holes penetrating through the first insulating layer;
the second rewiring layer includes:
a third sub-layer formed on the second surface of the base layer, the third sub-layer including a third fan-out line therein;
the second insulating layer is formed on one side, far away from the base layer, of the third sub-layer;
a fourth sub-layer formed on one side, far away from the third sub-layer, of the second insulating layer, wherein the fourth sub-layer comprises a fourth fan-out line; at least part of the fourth fan-out lines are electrically connected with at least part of the third fan-out lines through holes penetrating through the second insulating layer;
wherein a line width of the second fan-out line and the fourth fan-out line is smaller than a line width of the first fan-out line and the third fan-out line.
In a possible implementation manner, a first connection contact point is arranged on one side of the second sub-layer away from the base layer, and the first connection contact point is electrically connected with at least part of the second fan-out line;
and one side of the fourth sub-layer, which is far away from the base layer, is provided with a second connecting contact, and the second connecting contact is electrically connected with at least part of the fourth fan-out line.
In one possible implementation, the first sub-layer includes a plurality of layers of the first fan-out line; the second sublayer comprises a plurality of layers of the second fan-out lines; the third sublayer comprises a plurality of layers of the third fan-out lines; the fourth sublayer includes a plurality of layers of the fourth fan-out line.
In one possible implementation, the first redistribution layer includes:
the connecting wiring layer is formed on the first surface of the substrate layer;
a third insulating layer formed on the connection wiring layer;
a fifth sub-layer formed on one side, far away from the base layer, of the third insulating layer, wherein the fifth sub-layer comprises a fifth fan-out line; at least part of the fifth fan-out line is electrically connected with the connecting wiring layer through a through hole penetrating through the third insulating layer;
the second rewiring layer includes:
the sixth sub-layer is formed on the second surface of the base layer and comprises a sixth fan-out line, and at least part of the sixth fan-out line is electrically connected with the connecting wiring layer through a through hole penetrating through the base layer;
wherein a linewidth of the fifth fan-out line is less than a linewidth of the sixth fan-out line.
In a possible implementation manner, a third connection contact is arranged on a side of the fifth sub-layer away from the base layer, and the third connection contact is electrically connected with at least part of the fifth fan-out line; a fourth connecting contact is arranged on one side, away from the base layer, of the sixth sub-layer, and the fourth connecting contact is electrically connected with at least part of the sixth fan-out line;
the substrate further includes:
a fourth insulating layer formed on a side of the sixth sub-layer away from the base layer, the fourth insulating layer exposing the fourth connection contact;
and the solder balls are formed on one side of the fourth insulating layer, which is far away from the sixth sublayer, and are electrically connected with the fourth connecting contacts.
In one possible implementation, the fifth sublayer includes a plurality of layers of the fifth fan-out line; the sixth sublayer includes a plurality of layers of the sixth fan-out line.
Another objective of the present application is to provide a circuit board, which includes the substrate provided in the present application and a chip or a chip package structure disposed on the substrate.
Another object of the present application is to provide an electronic device, which includes the substrate provided in the present application.
Compared with the prior art, the method has the following beneficial effects:
the substrate, the circuit board and the electronic equipment provided by the embodiment of the application have the advantages that the linewidth of at least part of fan-out lines in the first rewiring layer is set to be smaller than the linewidth of at least part of fan-out lines in the second rewiring layer in the double-sided layer-added substrate, so that the fineness of the wire winding and routing can be guaranteed under the condition that the stacking number of the rewiring layers is not increased greatly, the manufacturing difficulty can be reduced, and the product yield is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a substrate according to an embodiment of the present disclosure;
fig. 2 is a second schematic structural diagram of a substrate according to an embodiment of the present disclosure;
fig. 3 is a third schematic structural diagram of a substrate according to an embodiment of the present disclosure;
fig. 4 is a fourth schematic structural diagram of a substrate according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience of describing the present application and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Furthermore, the terms "horizontal", "vertical", "suspended" and the like do not imply that the components are absolutely horizontal or suspended, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the present application, it should also be noted that, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and can include, for example, fixed connections, detachable connections, or integral connections; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 1 or fig. 2, the present embodiment provides a substrate including a base layer 100, a first redistribution layer 201, and a second redistribution layer 202.
The substrate layer 100 includes a first surface and a second surface, which are opposite sides.
The first redistribution layer 201 is located on the first surface, and the second redistribution layer 202 is located on the second surface. In this embodiment, the first redistribution layer 201 and the second redistribution layer 202 may respectively include one or more sub-layers, where the sub-layers may include a plurality of fan-out lines, and different fan-out lines are isolated from each other by an insulating material.
The line width of at least part of the fan-out lines in the first redistribution layer 201 is smaller than that of at least part of the fan-out lines in the second redistribution layer 202. At least part of the first fan-out lines 211 in the first redistribution layer 201 and at least part of the second fan-out lines 221 in the second redistribution layer 202 are electrically connected through a through hole penetrating through the base layer 100.
The above-mentioned base plate of this application embodiment, through in the base plate of two-sided increase layer, set up the linewidth of at least part fan-out line in first rewiring layer 201 into being less than the linewidth of at least part fan-out line in second rewiring layer 202, so, can guarantee the fineness of wire winding line under the condition that does not increase the number that the rewiring layer piles up by a large amount to can reduce the manufacturing degree of difficulty, improve the product yield.
In a possible implementation manner, a line width of the fan-out line on the side of the first redistribution layer 201 away from the base layer 100 is smaller than a line width of the fan-out line on the side of the second redistribution layer 202 close to the base layer 100.
Specifically, referring to fig. 1 again, in a possible implementation manner, the first redistribution layer 201 includes a first sub-layer 210, a first insulating layer 310, and a second sub-layer 220.
The first sub-layer 210 is formed on a first surface of the substrate layer 100, and the first sub-layer 210 includes a first fan-out line 211 therein.
The first insulating layer 310 is formed on a side of the first sub-layer 210 away from the base layer 100.
The second sub-layer 220 is formed on the side of the first insulating layer 310 away from the first sub-layer 210, and the second sub-layer 220 includes a second fan-out line 221 therein; at least a portion of the second fan-out lines 221 are electrically connected to at least a portion of the first fan-out lines 211 through vias that extend through the first insulating layer 310.
The second redistribution layer 202 includes a third sublayer 230, a second insulating layer 320, and a fourth sublayer 240.
The third sub-layer 230 is formed on the second surface of the substrate layer 100, and the third sub-layer 230 includes a third fan-out line 231 therein.
The second insulating layer 320 is formed on a side of the third sub-layer 230 away from the base layer 100.
The fourth sub-layer 240 is formed on the second insulating layer 320 at a side away from the third sub-layer 230, and the fourth sub-layer 240 includes a fourth fan-out line 241 therein; at least a portion of the fourth fan-out line 241 is electrically connected to at least a portion of the third fan-out line 231 through a via hole penetrating the second insulating layer 320.
In this embodiment, line widths of the second and fourth fan-out lines 221 and 241 are smaller than line widths of the first and third fan-out lines 211 and 231.
Through the second fan-out line 221 and the fourth fan-out line 241 in the second sublayer 220 and the fourth sublayer 240 with smaller line widths, finer wire winding and routing can be realized, so that the number of rewiring layers required to be stacked on the whole substrate can be reduced, the manufacturing difficulty is reduced, and the product yield is improved.
Further, referring to fig. 3, a first connection point 410 is disposed on a side of the second sub-layer 220 away from the substrate layer 100, and the first connection point 410 is electrically connected to at least a portion of the second fan-out line 221. A second connection contact 420 is disposed on a side of the fourth sub-layer 240 away from the substrate layer 100, and the second connection contact 420 is electrically connected to at least a part of the fourth fan-out line 241. The first connection contact 410 and the second connection contact 420 may be used for soldering or bonding with a chip, a chip package structure, or other devices.
In this embodiment, the first sub-layer 210 includes a plurality of layers of the first fan-out lines 211, the second sub-layer 220 includes a plurality of layers of the second fan-out lines 221, the third sub-layer 230 includes a plurality of layers of the third fan-out lines 231, and the fourth sub-layer 240 includes a plurality of layers of the fourth fan-out lines 241. More complicated routing can be realized through the multilayer fan-out circuit.
Referring to fig. 2 again, in another possible implementation manner, the first redistribution layer 201 may include a connection routing layer, a third insulation layer 330, and a fifth sub-layer 250.
The connection routing layer is formed on a first surface of the substrate layer 100.
The third insulating layer 330 is formed on the connection wiring layer.
The fifth sub-layer 250 is formed on the side of the third insulating layer 330 away from the base layer 100, and the fifth sub-layer 250 includes a fifth fan-out line 251 therein; at least a portion of the fifth fan-out line 251 is electrically connected to the connecting routing layer through a via hole penetrating the third insulating layer 330.
The second redistribution layer 202 may include a sixth sublayer 260.
The sixth sub-layer 260 is formed on the second surface of the substrate layer 100, the sixth sub-layer 260 includes a sixth fan-out line 261, and at least a portion of the sixth fan-out line 261 is electrically connected to the connection routing layer through a through hole penetrating through the substrate layer 100.
In this embodiment, the line width of the fifth fan-out line 251 is smaller than the line width of the sixth fan-out line 261.
Through the fifth fan-out line 251 in the fifth sublayer 250 with a smaller line width, finer winding and routing can be realized, so that the number of rewiring layers required to be stacked on the whole substrate can be reduced, the manufacturing difficulty is reduced, and the product yield is improved.
Further, referring to fig. 4, a third connection contact 430 is disposed on a side of the fifth sub-layer 250 away from the substrate layer 100, and the third connection contact 430 is electrically connected to at least a portion of the fifth fan-out line 251; a fourth connection contact 440 is disposed on a side of the sixth sub-layer 260 away from the substrate layer 100, and the fourth connection contact 440 is electrically connected to at least a part of the sixth fan-out line 261.
The substrate further includes a fourth insulating layer 340 and solder balls 450.
The fourth insulating layer 340 is formed on a side of the sixth sub-layer 260 away from the base layer 100, and the fourth insulating layer 340 exposes the fourth connection contact 440.
The solder balls 450 are formed on the side of the fourth insulating layer 340 away from the sixth sub-layer 260, and the solder balls 450 are electrically connected to the fourth connection contacts 440.
The third connection contacts 430 and the solder balls 450 may be used for soldering or bonding with a chip, a chip package structure or other devices.
In this embodiment, the fifth sublayer 250 includes a plurality of layers of the fifth fan-out lines 251; the sixth sublayer 260 includes a plurality of layers of the sixth fan-out lines 261. More complicated routing can be realized through the multilayer fan-out circuit.
Based on the same concept, the present embodiment further provides a circuit board, where the circuit board is provided with the substrate and a chip or a chip package structure disposed on the substrate.
The embodiment also provides an electronic device, which includes the substrate provided by the embodiment.
To sum up, a base plate, circuit board and electronic equipment of this application embodiment through in the base plate of two-sided increase layer, sets up the linewidth of at least part fan-out circuit in the first rewiring layer to be less than the linewidth of at least part fan-out circuit in the second rewiring layer, so, can guarantee the fineness of wire winding line under the condition that does not increase the number that the rewiring layer piles up by a large amount to can reduce the manufacturing degree of difficulty, improve the product yield.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The above description is only for various embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and all such changes or substitutions are included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A substrate, comprising:
a base layer comprising a first surface and a second surface;
a first redistribution layer on the first surface;
a second redistribution layer on the second surface, wherein the line width of at least part of the fan-out lines in the first redistribution layer is smaller than the line width of at least part of the fan-out lines in the second redistribution layer;
at least part of the first fan-out lines in the first redistribution layer are electrically connected with at least part of the second fan-out lines in the second redistribution layer through holes penetrating through the base layer.
2. The substrate of claim 1, wherein a linewidth of a fan-out line in the first redistribution layer on a side away from the base layer is smaller than a linewidth of a fan-out line in the second redistribution layer on a side close to the base layer.
3. The substrate according to claim 1, wherein the first redistribution layer comprises:
a first sub-layer formed on a first surface of the base layer, the first sub-layer including a first fan-out line therein;
the first insulating layer is formed on one side, far away from the base layer, of the first sub-layer;
the second sub-layer is formed on one side, far away from the first sub-layer, of the first insulating layer and comprises a second fan-out line; at least part of the second fan-out lines are electrically connected with at least part of the first fan-out lines through holes penetrating through the first insulating layer;
the second rewiring layer includes:
a third sub-layer formed on a second surface of the base layer, the third sub-layer including a third fan-out line therein;
the second insulating layer is formed on one side, far away from the base layer, of the third sub-layer;
a fourth sub-layer formed on one side, far away from the third sub-layer, of the second insulating layer, wherein the fourth sub-layer comprises a fourth fan-out line; at least part of the fourth fan-out lines are electrically connected with at least part of the third fan-out lines through holes penetrating through the second insulating layer;
wherein a line width of the second fan-out line and the fourth fan-out line is smaller than a line width of the first fan-out line and the third fan-out line.
4. The substrate of claim 3,
a first connecting contact point is arranged on one side, away from the base layer, of the second sublayer, and the first connecting contact point is electrically connected with at least part of the second fan-out circuit;
and one side of the fourth sub-layer, which is far away from the base layer, is provided with a second connecting contact, and the second connecting contact is electrically connected with at least part of the fourth fan-out line.
5. The substrate of claim 3, wherein the first sub-layer comprises a plurality of layers of the first fan-out line; the second sublayer comprises a plurality of layers of the second fan-out lines; the third sublayer comprises a plurality of layers of the third fan-out lines; the fourth sublayer includes a plurality of layers of the fourth fan-out line.
6. The substrate according to claim 1, wherein the first redistribution layer comprises:
the connecting wiring layer is formed on the first surface of the substrate layer;
a third insulating layer formed on the connection wiring layer;
a fifth sub-layer formed on one side, far away from the base layer, of the third insulating layer, wherein the fifth sub-layer comprises a fifth fan-out line; at least part of the fifth fan-out line is electrically connected with the connecting wiring layer through a through hole penetrating through the third insulating layer;
the second rewiring layer includes:
the sixth sub-layer is formed on the second surface of the base layer and comprises a sixth fan-out line, and at least part of the sixth fan-out line is electrically connected with the connecting wiring layer through a through hole penetrating through the base layer;
wherein a linewidth of the fifth fan-out line is less than a linewidth of the sixth fan-out line.
7. The substrate of claim 6, wherein a side of the fifth sub-layer remote from the base layer is provided with a third connection contact, and the third connection contact is electrically connected with at least part of the fifth fan-out line; a fourth connecting contact is arranged on one side, away from the base layer, of the sixth sub-layer, and the fourth connecting contact is electrically connected with at least part of the sixth fan-out line;
the substrate further includes:
a fourth insulating layer formed on a side of the sixth sub-layer away from the base layer, the fourth insulating layer exposing the fourth connection contact;
and the solder balls are formed on one side of the fourth insulating layer, which is far away from the sixth sublayer, and are electrically connected with the fourth connecting contacts.
8. The substrate of claim 7, wherein the fifth sublayer comprises a plurality of layers of the fifth fan-out line; the sixth sublayer includes a plurality of layers of the sixth fan-out line.
9. A circuit board, characterized in that the circuit board comprises the substrate of any one of claims 1-8 and a chip or chip package structure disposed on the substrate.
10. An electronic device, characterized in that the electronic device comprises a substrate according to any one of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222325086.8U CN217903115U (en) | 2022-08-30 | 2022-08-30 | Substrate, circuit board and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222325086.8U CN217903115U (en) | 2022-08-30 | 2022-08-30 | Substrate, circuit board and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217903115U true CN217903115U (en) | 2022-11-25 |
Family
ID=84108066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222325086.8U Active CN217903115U (en) | 2022-08-30 | 2022-08-30 | Substrate, circuit board and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217903115U (en) |
-
2022
- 2022-08-30 CN CN202222325086.8U patent/CN217903115U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103165555B (en) | Package structure of stacked package and manufacturing method thereof | |
| TWI444120B (en) | Mainboard assembly including a package overlying a die directly attached to the mainboard,a method of fabricating a mainboard assembly,and a computing system | |
| TW530377B (en) | Structure of laminated substrate with high integration and method of production thereof | |
| JPH0220848Y2 (en) | ||
| KR100833589B1 (en) | Stack package | |
| US10068847B2 (en) | Package substrate and method of fabricating the same | |
| US7989940B2 (en) | System and method for increasing the number of IO-s on a ball grid package by wire bond stacking of same size packages through apertures | |
| EP2822369A1 (en) | Multilayer circuit board and production method thereof and communication device | |
| US20100218364A1 (en) | Packaging substrate having pattern-matched metal layers | |
| JPS582054A (en) | Semiconductor device | |
| US10573614B2 (en) | Process for fabricating a circuit substrate | |
| JP5017872B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN105304584A (en) | Interposer substrate and method of manufacturing the same | |
| JP3899059B2 (en) | Electronic package having low resistance and high density signal line and method of manufacturing the same | |
| US20090133917A1 (en) | Multilayered Circuit Board for Connection to Bumps | |
| CN105323948A (en) | Interposer substrate and method of manufacturing the same | |
| JP3721893B2 (en) | Semiconductor devices and electronic devices | |
| EP2849226B1 (en) | Semiconductor package | |
| US10453787B2 (en) | Method and apparatus for forming multi-layered vias in sequentially fabricated circuits | |
| CN217903115U (en) | Substrate, circuit board and electronic equipment | |
| CN218414563U (en) | Packaging structure, circuit board and electronic equipment | |
| US9253880B2 (en) | Printed circuit board including a plurality of circuit layers and method for manufacturing the same | |
| JP3617264B2 (en) | Electrolytic plating method for plastic circuit boards | |
| CN214014642U (en) | Printed circuit board structure | |
| US20240304534A1 (en) | Thermally improved substrate structure and package assembly with the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: No.12 Shangyang Road, high tech Zone, Chengdu, Sichuan 610000 Patentee after: Chengdu ESWIN SYSTEM IC Co.,Ltd. Address before: No.12 Shangyang Road, high tech Zone, Chengdu, Sichuan 610000 Patentee before: Chengdu yisiwei system integrated circuit Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |