CN217901868U - Three-state level state detection circuit - Google Patents
Three-state level state detection circuit Download PDFInfo
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- CN217901868U CN217901868U CN202221171140.1U CN202221171140U CN217901868U CN 217901868 U CN217901868 U CN 217901868U CN 202221171140 U CN202221171140 U CN 202221171140U CN 217901868 U CN217901868 U CN 217901868U
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Abstract
The utility model provides a tristate level state detection circuitry for detect the level state of outside level signal input. The signal processing module comprises a first signal processing unit and a second signal processing unit, wherein one end of the first signal processing unit is connected with an A/D port, one end of the second signal processing unit is connected with another A/D port, the other ends of the first signal processing unit and the second signal processing unit are connected with a level signal input end, and the first signal processing unit and the second signal processing unit are respectively connected into an internal power supply. When the level signal input end inputs high level, low level and suspension input respectively, the size of a sampling value between two A/D ports connected with the first signal processing unit and the second signal processing unit is different from that of an internal power supply value. The embodiment occupies 2A/D ports of the microcontroller, so that the effective detection of three states of high, low and suspension of external input is realized, and system resources are greatly saved.
Description
Technical Field
The utility model relates to a detection circuitry technical field, in particular to tristate level state detection circuitry.
Background
In the field of electronic information or automation control technology, there is usually an application of external level state detection, such as vehicle level state detection. Generally, an external level input can be generally classified into three states: high level, low level and floating state. The traditional external level input detection circuit generally only detects one state, namely only high level input or only low level input can be detected to be effective, and the suspended state input cannot be detected.
In view of the above, it is desirable to design a circuit capable of detecting the state of a tri-state level.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a tristate level state detection circuitry.
The utility model discloses it is solved that current outside level input detection circuitry can only detect the problem of a state.
In order to solve the problem, the utility model discloses a following technical scheme realizes:
a tri-state level state detection circuit is used for detecting the level state of an external level signal input end. The power supply comprises a microcontroller with at least two A/D ports and a signal processing module, wherein the signal processing module comprises a first signal processing unit and a second signal processing unit, one end of the first signal processing unit is connected with the A/D port, one end of the second signal processing unit is connected with the other A/D port, the other ends of the first signal processing unit and the second signal processing unit are connected with a level signal input end, and the first signal processing unit and the second signal processing unit are respectively connected with an internal power supply. The high level voltage input by the level signal input end is greater than the power supply voltage; when the level signal input end inputs high level, low level and suspension input respectively, the size of a sampling value between two A/D ports connected with the first signal processing unit and the second signal processing unit is different from that of an internal power supply value.
Furthermore, when the level signal input end inputs a high level, the sampling values of the two A/D ports are equal and equal to the internal power supply; when the level signal input end inputs a low level, the sampling values of the two A/D ports are less than one half of the internal power supply and are equal; when the level signal input end is input in a suspension mode, the sampling value of one A/D port is smaller than the value of the internal power supply and larger than the sampling value of the other A/D port.
Furthermore, the first signal processing unit comprises a first switch connected with the level signal input end, a second switch connected with the first switch, a first resistor connected between the second switch and the A/D port, and a second resistor connected with the common end of the first switch and the second switch. The other end of the first resistor is connected with an internal power supply, and the other end of the second resistor is grounded; the resistance value of the first resistor is larger than that of the second resistor, so that when the first switch is closed and the second switch is opened, the voltage division value of the second resistor and the second switch is smaller than that of the first resistor.
Furthermore, the second signal processing unit comprises a third switch connected with the level signal input end, a fourth resistor connected between the third switch and the A/D port and a third resistor connected with the A/D port. The other end of the third resistor is connected with an internal power supply; the resistance value of the third resistor is larger than that of the fourth resistor, so that when the third switch is switched on at a low level, the voltage division value of the fourth resistor and the third switch is smaller than that of the third resistor.
Furthermore, the resistance of the first resistor is equal to the resistance of the third resistor, and the resistance of the second resistor is equal to the resistance of the fourth resistor.
Furthermore, the first switch is a diode with the anode connected with the level signal input end, and the second switch is a diode with the anode connected with the A/D port.
Furthermore, the first signal processing unit further comprises a first filter capacitor and a first transient diode which are connected to the A/D port, the other end of the first filter capacitor is grounded, and the anode of the first transient diode is grounded.
Further, the third switch is a diode having a cathode connected to the level signal input terminal.
Furthermore, the second signal processing unit further comprises a second filter capacitor and a second transient diode connected to the a/D port, the other end of the second filter capacitor is grounded, and the anode of the second transient diode is grounded.
Compared with the prior art, the utility model discloses technical scheme and beneficial effect as follows:
(1) The utility model discloses a three state detection circuit, when level signal input part inputed high level, low level and three kinds of states of unsettled input respectively, through the size of the sample value of 2 AD mouth and with internal power supply VDD's big or small relation, can judge the level state of level signal input part fast. The embodiment occupies 2A/D ports of the microcontroller, so that the effective detection of three states of high, low and suspension of external input is realized, and system resources are greatly saved.
(2) The utility model discloses a numerical value that the numerical value of AD mouth 1 collection, the numerical value of AD mouth 2 collection and the fixed size relation between the internal power supply VDD three can the quick judgement external input's level state.
(3) The utility model discloses a three state detection circuitry adopts the ordinary components and parts of general type just can realize high, low level and unsettled three kinds of states and effectively detect, has saved system resource greatly, and the circuit is simple makes the cost of manufacture reduce, has compensatied the not enough of prior art greatly.
Drawings
Fig. 1 is a block diagram of a tri-state level state detection circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a tri-state level state detection circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a tri-state level state detection circuit according to an embodiment of the present invention.
Illustration of the drawings:
level signal input-100; a signal processing module-200; a microcontroller-300.
Detailed Description
To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the attached drawings in the embodiments of the present invention are combined to clearly and completely describe the technical solution in the embodiments of the present invention, and obviously, the described embodiments are part of the embodiments of the present invention, rather than all embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1, a tri-state level state detection circuit for detecting the level state of an external level signal input terminal 100 includes a microcontroller 300 and a signal processing module 200. Microcontroller 300 has at least two A/D ports, A/D port 1 and A/D port 2. The signal processing module 200 includes a first signal processing unit connected between the level signal input terminal 100 and the a/D port 1 and a second signal processing unit connected between the level signal input terminal 100 and the a/D port 2. The first signal processing unit and the second signal processing unit are both connected with an internal power supply VDD, and a high level VCC input by a level signal input end 100 is larger than the internal power supply VDD.
When the level signal input end 100 inputs three states of high level, low level and suspension input respectively, the level state of the level signal input end 100 can be judged quickly through the magnitude relation among the numerical value collected by the A/D port 1, the numerical value collected by the A/D port 2 and the internal power supply VDD. The embodiment occupies 2A/D ports of the microcontroller, so that the effective detection of three states of high, low and suspension of external input is realized, and system resources are greatly saved.
More specifically, when the level signal input terminal 100 inputs the high level VCC, the sampling values of the a/D port 1 and the a/D port 2 are equal and equal to the internal power supply VDD, and it can be understood that the difference of the equality here is very small and is within the error tolerance range. When the level signal input terminal 100 is grounded, the sampling values of the A/D port 1 and the A/D port 2 are equal and smaller than the internal power supply VDD/2. When the level signal input end is input in a suspension mode, the sampling value of the A/D port 2 is smaller than the value of the internal power supply and larger than the sampling value of the A/D port 1. The level state of external input can be quickly judged through the fixed size relation among the numerical value collected by the A/D port 1, the numerical value collected by the A/D port 2 and the internal power supply VDD.
Referring to fig. 2, the first signal processing unit includes a first switch D1 connected to the level signal input terminal 100, a second switch D2 connected to the first switch D1, a first resistor R1 connected between the second switch D2 and the a/D port 1, and a second resistor R2 connected to a common terminal of the first switch D1 and the second switch D2. The other end of the first resistor R1 is connected with an internal power supply VDD, and the other end of the second resistor R2 is grounded; the resistance of the first resistor R1 is several times or even several tens times of the resistance R2 of the second resistor, so that when the first switch D1 is turned off and the second switch D2 is turned on, that is, the internal power supply VDD, the first resistor R1, the second switch D2, the second resistor R2 and the ground form a path, the voltage dividing values of the second resistor R2 and the second switch are smaller than the voltage dividing value of the first resistor R1.
The second signal processing unit includes a third switch D3 connected to the level signal input terminal 100, a fourth resistor R4 connected between the third switch D3 and the a/D port 2, and a third resistor R3 connected to the a/D port 2. The other end of the third resistor R3 is connected to the internal power supply VDD, and the resistance of the third resistor R3 is several times or even several tens of times of the resistance of the fourth resistor R4, so that when the third switch is turned on at a low level, that is, after the internal power supply VDD, the third resistor R3, the fourth resistor R4, the third switch D3 and the ground form a path, the voltage division values of the fourth resistor R4 and the third switch D3 are smaller than the voltage division value of the third resistor R3.
In this embodiment, the resistance values R1= R3 > R2= R4 are taken.
When the level signal input end inputs high level VCC: the first switch D1 is switched on, the second switch tube D2 is switched off, the A/D port 1 is pulled up to the internal power supply VDD through the first resistor R1, and at the moment, the sampling value of the A/D port 1 is the voltage value of the internal power supply VDD. The third switch D3 is turned off, the a/D port 2 is pulled up to the internal power supply VDD through the third resistor R3, and at this time, the sampling value of the a/D port 2 is the voltage value of the internal power supply VDD. It can be obtained that when the level signal input end inputs the high level VCC, the sampling value of the A/D port 1 is equal to the sampling value of the A/D port 2 and is equal to the internal power supply VDD.
When the level signal input end is grounded (low level): first switch D1 ends, and second switch tube D2 switches on, internal power supply VDD, first resistance R1, second switch D2, second resistance R2 and form the route, because first resistance R1 is far greater than second resistance R2, here R1 and R2's value can set up by oneself, it can to satisfy second resistance R2 and second switch D2 partial pressure value and be less than first resistance R1's partial pressure value, at this moment, the sampling value of AD mouth 1 is less than internal power supply VDD/2. Similarly, since the third resistor R3 is much larger than the fourth resistor R4, the voltage division value of the fourth resistor R4 and the third switch D3 is smaller than the voltage division value of the first resistor R1, and at this time, the sampling value of the a/D port 2 is smaller than the internal power supply VDD/2. It can be known that when the signal input terminal inputs low level, the sampling value of the A/D port 1 is equal to the sampling value of the A/D port 2 and is less than the internal power supply VDD/2.
When the level signal input end is suspended, the internal power supply VDD, the first resistor R1, the second switch D2, the second resistor R2 and a ground form a passage, and the sampling value of the A/D port 1 is smaller than the internal power supply VDD/2. The internal power supply VDD, the third resistor R3, the fourth resistor R4, the third switch D3, the first switch D1, the second resistor R2 and the ground are connected, at this time, the sampling value of the a/D port 2 is equal to the divided voltage values of the fourth resistor R4, the third switch D3, the first switch D1 and the second resistor R2, and is inevitably greater than the divided voltage values of the second resistor R2 and the second switch D2, and it can be known that when the level signal input end is suspended, the sampling value of the a/D port 2 is greater than the sampling value of the a/D port 1.
It is understood that the first switch D1, the second switch D2 and the third switch D3 may be turned on or off manually, or may be an electrical component that is turned on or off automatically according to the level state of the level signal input terminal 100. In this embodiment, the first switch D1 is a diode whose anode is connected to the level signal input terminal 100, the second switch D2 is a diode whose anode is connected to the a/D port 1, and the third switch D3 is a diode whose cathode is connected to the level signal input terminal 100.
Further, the level state determination condition is: when the level signal input end inputs high level VCC, the sampling value of the A/D port 1 is equal to the sampling value of the A/D port 2 and is equal to the internal power supply VDD.
When the signal input end inputs low level, the sampling value of the A/D port 1 is equal to the sampling value of the A/D port 2 and is smaller than the internal power supply VDD/2, and the voltage drop of the A/D port 1 is larger than the voltage drop of the diode D3 by 0.7V.
When the level signal input end is suspended, the sampling value of the A/D port 2 is smaller than the internal power supply VDD and is at least 0.7V (voltage drop of the first switch D1) larger than the sampling value of the A/D port 1.
Referring to fig. 3, the first signal processing unit further includes a first filter capacitor C1 and a first transient diode TVS1 connected to the a/D port 1, wherein the other end of the first filter capacitor C1 is grounded, and the anode of the first transient diode TVS1 is grounded. The second signal processing unit further includes a second filter capacitor C2 and a second transient diode TVS2 connected to the a/D port 2, the other end of the second filter capacitor C2 is grounded, and the anode of the second transient diode TVS2 is grounded. The first transient diode TVS1 and the second transient diode TVS2 select the model matched with the internal power supply VDD to absorb the high-frequency pulse signal and play a secondary protection role for the A/D port. The first filter capacitor C1 and the second filter capacitor C2 are used for filtering external interference level input, and the precision of the sampling value of the A/D port is improved.
The utility model discloses a tristate level state detection circuitry only needs to occupy MCU's 2 AD oral siphon resources, adopts the ordinary components and parts of general type, just can realize that high, low level and unsettled three kinds of states effectively detect, has saved system's resource greatly, and the circuit simply makes the cost of manufacture reduce, has compensatied the not enough of prior art greatly.
While the above description shows and describes the preferred embodiments of the present invention, it is to be understood that the invention is not limited to the forms disclosed herein, but is not intended to be exhaustive or to exclude other embodiments and may be used in various other combinations, modifications, and environments and is capable of changes within the scope of the invention as expressed in the above teachings or as determined by the knowledge of the relevant art. But that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A tri-state level state detection circuit for detecting a level state of an external level signal input terminal, comprising:
a microcontroller having at least two A/D ports;
the signal processing module comprises a first signal processing unit with one end connected with the A/D port and a second signal processing unit with one end connected with the other A/D port, the other ends of the first signal processing unit and the second signal processing unit are both connected with the level signal input end, and the first signal processing unit and the second signal processing unit are respectively connected with an internal power supply;
wherein, the high level voltage input by the level signal input end is greater than the power supply voltage; when the level signal input end inputs a high level, a low level and a suspension input respectively, the size of a sampling value between two A/D ports connecting the first signal processing unit and the second signal processing unit is different from the size between the two A/D ports connecting the first signal processing unit and the second signal processing unit and the size between the two A/D ports and the internal power supply are different.
2. A tri-state level state detection circuit according to claim 1, wherein when the level signal input terminal inputs a high level, the sampling values of the two a/D ports are equal and equal to the internal power supply; when the level signal input end inputs low level, the sampling values of the two A/D ports are smaller than one half of the internal power supply, and the sampling values of the two A/D ports are equal; when the level signal input end is input in a suspended mode, the sampling value of one A/D port is smaller than the value of the internal power supply and larger than the sampling value of the other A/D port.
3. The tri-state level state detection circuit of claim 2, wherein the first signal processing unit comprises a first switch connected to the level signal input terminal, a second switch connected to the first switch, a first resistor connected between the second switch and the a/D port, and a second resistor connected to a common terminal of the first switch and the second switch;
the other end of the first resistor is connected with the internal power supply, and the other end of the second resistor is grounded; the resistance value of the first resistor is larger than that of the second resistor, so that when the first switch is closed and the second switch is opened, the voltage division value of the second resistor and the second switch is smaller than that of the first resistor.
4. A tristate level state detection circuit as claimed in claim 3 wherein said second signal processing unit comprises a third switch connected to said level signal input terminal, a fourth resistor connected between said third switch and said a/D port and a third resistor connected to said a/D port;
wherein the other end of the third resistor is connected with the internal power supply; the resistance value of the third resistor is larger than that of the fourth resistor, so that when the third switch is switched on at a low level, the voltage division values of the fourth resistor and the third switch are smaller than that of the third resistor.
5. The tri-state level state detection circuit of claim 4, wherein the first resistor has a resistance equal to that of the third resistor, and the second resistor has a resistance equal to that of the fourth resistor.
6. A tristate level state detection circuit as claimed in claim 3 wherein said first switch is a diode having its anode connected to said level signal input terminal and said second switch is a diode having its anode connected to said a/D port.
7. The tri-state level state detection circuit of claim 5, wherein the first signal processing unit further comprises a first filter capacitor and a first transient diode connected to the A/D port, the other end of the first filter capacitor is grounded, and the anode of the first transient diode is grounded.
8. The tri-state level state detection circuit of claim 4, wherein the third switch is a diode having a cathode connected to the level signal input terminal.
9. The tri-state level state detection circuit of claim 8, wherein the second signal processing unit further comprises a second filter capacitor and a second transient diode connected to the a/D port, the other end of the second filter capacitor is grounded, and the anode of the second transient diode is grounded.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221171140.1U CN217901868U (en) | 2022-05-16 | 2022-05-16 | Three-state level state detection circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221171140.1U CN217901868U (en) | 2022-05-16 | 2022-05-16 | Three-state level state detection circuit |
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| CN217901868U true CN217901868U (en) | 2022-11-25 |
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| CN202221171140.1U Active CN217901868U (en) | 2022-05-16 | 2022-05-16 | Three-state level state detection circuit |
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