CN217883474U

CN217883474U - Mainboard and switch

Info

Publication number: CN217883474U
Application number: CN202222780117.9U
Authority: CN
Inventors: 洪超; 王秀成; 王健; 赵立伟; 阎博
Original assignee: Ziguang Hengyue Technology Co ltd
Current assignee: Ziguang Hengyue Technology Co ltd
Priority date: 2022-10-21
Filing date: 2022-10-21
Publication date: 2022-11-22
Anticipated expiration: 2032-10-21

Abstract

The utility model provides a mainboard and switch, the mainboard includes central processing unit, exchange chip, safe card and programmable logic chip, central processing unit passes through PCIE interface connection of PCIE interface 0 with the exchange chip of telling, central processing unit pass through PCIE interface 1 with the PCIE interface connection of safe card, central processing unit passes through SPI interface 1 and is connected with data selector 2, the safe card passes through the SPI interface and is connected with data selector 2, data selector 2 is connected with the BIOS chip. The utility model provides an in the CPU system of host computer is linked with special safety card to the switch, during the system start, special safety card can discern host system, discerns through back host system could normal operating, otherwise the affirmation is illegal equipment, does not let the start. The identification process can ensure the safe operation of the equipment in occasions with higher requirements on confidentiality and the safety of the intranet.

Description

Mainboard and switch

Technical Field

The utility model belongs to network communication equipment field, concretely relates to mainboard and switch.

Background

The switch is as the core equipment among the network communication equipment, along with the increase by a wide margin of data transmission volume and the diversification of application scene, especially in the intranet that has the requirement of keeping secret, has proposed higher requirement to the fail safe nature of switch, and traditional switch does not have the management and control function of authorizing, can't use in the intranet that has the requirement of keeping secret.

The utility model provides an in the CPU system of host computer is connected to special safety card to the switch, during the system start, special safety card can discern host system, and the discernment just can normal operating through back host system, and otherwise the affirmation is illegal equipment, does not let the start. The identification process can ensure the safe operation of the equipment in the occasions with higher requirement on confidentiality and ensure the safety of the intranet.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a mainboard and switch aims at satisfying the requirement to switch fail safe nature.

In order to realize the above object, the utility model provides a mainboard, the mainboard includes central processing unit, exchange chip, safety card and programmable logic chip, central processing unit pass through PCIE interface 0 with the PCIE interface connection of exchange chip, central processing unit pass through PCIE interface 1 with the PCIE interface connection of safety card, central processing unit passes through SPI interface 1 and is connected with data selector 2, the safety card passes through the SPI interface and is connected with data selector 2, data selector 2 is connected with the BIOS chip.

Further, the central processing unit and the switching chip are respectively connected with a data selector 1 through an I2C interface, the data selector 1 is connected with a temperature sensing chip, a primary power supply, an EEPROM chip, a data selector 0 and a 6 × 10g optical port, and the data selector 0 is connected with the 6 × 10g optical port.

Further, the central processing unit is connected to the buffer chip 0 through the SPI interface 0, and the switch chip and the programmable logic chip are connected to the buffer chip 0 through the SPI interface.

Further, the central processing unit and the exchange chip are respectively connected with the buffer chip 1 through a UART interface, and the programmable logic chip is connected with the buffer chip 1 through a UART interface 0.

Furthermore, the programmable logic chip is connected with the management serial port through a UART interface 1, and the programmable logic chip is connected with the service port indicator lamp through an electric lamp interface.

Further, the safety card is connected with the status indicator lamp through an indicator lamp interface, the safety card is connected with the buzzer through a buzzer interface, the safety card is connected with the transformer 2 through an MDI interface, the transformer 2 is connected with the debugging network port, the safety card is connected with the USB test port through a USB interface, and the safety card is connected with the debugging serial port through a UART interface.

Further, the central processing unit and the switch chip are connected with a buffer chip 2 through an SGMII interface, the buffer chip 2 is connected with a PHY chip 2, the PHY chip 2 is connected with a transformer 1, and the transformer 1 is connected with a management network port.

Further, the central processing unit and the exchange chip are connected with a buffer chip 3 through a USB interface, and the buffer chip 3 is connected with a USB2.0 interface.

Further, the exchange chip is connected to PHY chip 0[ 2], [0 ] and PHY chip 1 via high-speed interface 1 and SMI interface, the PHY chip 0[0 ], [0 ] and the PHY chip 1 are connected to transformer 0[0 ], [0 ]:13 ], the transformer 0[ 13] is connected to RJ45 [ 8 ] GE interface, RJ45 [ 4 ] GE interface and RJ45 [ 4 ] electrical port, and the PHY chip 1 is connected to SFP [ 4 ] GE optical port.

Further, the switch at least comprises the main board described in any one of the above.

Compared with the prior art, the utility model has the advantages of it is following: the utility model provides an in the CPU system of host computer is connected to special safety card to the switch, during the system start, special safety card can discern host system, and the discernment just can normal operating through back host system, and otherwise the affirmation is illegal equipment, does not let the start. The identification process can ensure the safe operation of the equipment in occasions with higher requirements on confidentiality and the safety of the intranet.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of the present invention.

Detailed Description

The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Referring to fig. 1, it should be noted that the drawings provided in the present embodiment are only schematic illustrations of the basic concept of the present invention, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

As shown in fig. 1, the structure provided by this embodiment is schematically illustrated.

The utility model provides a giga switch provides the business interface to the external interface and includes: 24 × 10/100/1000 BASE-T RJ45 electrical port, 4 × GE Combo port, 8 × 10G SFP + optical port. The Console port is used for equipment management, the USB3.0 is used for external storage expansion, and the USB interface supports 2 pluggable power supplies and supports 2 pluggable PWM speed regulation fans. The system supports the SOC security card of the PCIe M.2E-Key interface and is used for the security management of the equipment.

The single board exchange core adopts a Shengke exchange chip CTC 7132. The 24 × rj45 electrical port output is implemented by CTCs 21108 × 3, each CTC21108 supporting 2 QSGMII ports (occupying HS _ S0[ 5] of CTC 7132); 4GE Combo output is achieved by Sci _ CTC21104 (occupying HS _ S0[6] of CTC 7132); 8 × sfp + optical port is straight out from CTC7132 (HS _ HS1[0 ] occupying CTC 7132).

The main control CPU adopts FT2000 CPU buckle design, the CPU system comprises peripheral circuits such as DDR4 SDRAM, EMMC and SFLASH, and the like, and provides functions such as control, message/protocol processing and the like for the whole single board. The CPU integrates 4 Feiteng independently developed processor cores FTC663, is compatible with a 64-bit ARMv8 instruction set and a 16nm manufacturing process, and has the highest main frequency of 3.0GHz; the system memory is a 4Gb DDR4 SDRAM, patch type particles with the capacity of 1GB are adopted, and ECC design is supported; the 32Mbit QSPI FLASH is used as Bootrom storage space and is backed up in a master-slave mode.

The single-board logic control adopts purple light to create Compact series CPLD device PGC1KG-6CFBG256, realizing the functions of single-board reset, expansion board and power state collection, interruption convergence, version report, display control, dog feeding and the like.

The safety card part realizes measurement and verification of the BIOS of the system by the safety card before the CPU system is started through switching back and forth between the CPU of the bottom plate and the safety card through the SPI flash, and finally realizes safety management of the equipment.

The utility model provides a mainboard, the mainboard includes central processing unit, exchange chip, safe card and programmable logic chip, central processing unit pass through PCIE interface 0 with the PCIE interface connection of exchange chip, central processing unit pass through PCIE interface 1 with the PCIE interface connection of safe card, central processing unit passes through SPI interface 1 and is connected with data selector 2, safe card passes through the SPI interface and is connected with data selector 2, data selector 2 is connected with the BIOS chip.

Further, the central processing unit is connected with the buffer chip 0 through the SPI interface 0, and the switch chip and the programmable logic chip are connected with the buffer chip 0 through the SPI interface.

Furthermore, the programmable logic chip is connected with a management serial port through a UART interface 1, and the programmable logic chip is connected with the service port indicator light through an electric light interface.

Further, the safety card is connected with the status indicator lamp through the indicator lamp interface, the safety card is connected with the buzzer through the buzzer interface, the safety card is connected with the transformer 2 through the MDI interface, the transformer 2 is connected with the debugging net gape, the safety card is connected with the USB test gape through the USB interface, the safety card is connected with the debugging serial port through the UART interface.

Further, the exchange chip is connected to PHY chip 0[ 2], [0 ], [ 2] and PHY chip 1 via a high-speed interface 1 and an SMI interface, respectively, the PHY chip 0[0 ], [0 ] and the PHY chip 1 are connected to transformer 0[0 ], [0 ]:13 ], the transformer 0[0 ], [ 13] is connected to RJ45 2 GE interface, RJ45 GE 2 GE 4 interface and RJ45 GE 4 electrical port, and the PHY chip 1 is connected to SFP 4GE optical port.

The switch at least comprises the main board. The circuit board inside the switch is used as a carrier. The other hardware configuration of the switch is not particularly limited. The utility model provides a relevant necessary hardware structures such as shell, antenna that the switch has general switch and possesses.

The embodiments described above are only a part of the embodiments of the present invention, and not all of them. The components of embodiments of the present invention, as generally described and illustrated herein and in the figures, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other changes or substitutions obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.

Claims

1. The utility model provides a mainboard, its characterized in that, the mainboard includes central processing unit, exchange chip, safety card and programmable logic chip, central processing unit pass through PCIE interface 0 with the PCIE interface connection of exchange chip, central processing unit pass through PCIE interface 1 with the PCIE interface connection of safety card, central processing unit passes through SPI interface 1 and is connected with data selector 2, the safety card passes through the SPI interface and is connected with data selector 2, data selector 2 is connected with the BIOS chip.

2. The motherboard of claim 1, wherein the cpu and the switch chip are connected to a data selector 1 via an I2C interface, the data selector 1 is connected to a temperature sensing chip, a primary power supply, an EEPROM chip, a data selector 0 and a 6 a 10g optical port, and the data selector 0 is connected to the 6 a 10g optical port.

3. The motherboard of claim 1 or 2, wherein the central processing unit is connected with the buffer chip 0 through an SPI interface 0, and the switch chip and the programmable logic chip are connected with the buffer chip 0 through an SPI interface.

4. The motherboard of claim 3, wherein the central processing unit and the switch chip are respectively connected to the buffer chip 1 through a UART interface, and the programmable logic chip is connected to the buffer chip 1 through a UART interface 0.

5. The motherboard of claim 4, wherein the programmable logic chip is connected to the management serial port via a UART interface 1, and the programmable logic chip is connected to the service port indicator light via an electric light interface.

6. The motherboard of claim 5, wherein the security card is connected to the status indicator lamp through an indicator lamp interface, the security card is connected to the buzzer through a buzzer interface, the security card is connected to the transformer 2 through an MDI interface, the transformer 2 is connected to the debugging network port, the security card is connected to the USB test port through a USB interface, and the security card is connected to the debugging serial port through a UART interface.

7. The motherboard of claim 6, wherein the central processing unit and the switch chip are connected to a buffer chip 2 via an SGMII interface, the buffer chip 2 is connected to a PHY chip 2, the PHY chip 2 is connected to a transformer 1, and the transformer 1 is connected to a management network interface.

8. The motherboard of claim 7, wherein the cpu and the switch chip are connected to a buffer chip 3 via a USB interface, and the buffer chip 3 is connected to a USB2.0 interface.

9. The motherboard of claim 8, wherein the switch chip is connected to PHY chip 0[ 2] and PHY chip 1 via high speed interface 1 and SMI interface, respectively, the PHY chip 0[0 ] and PHY chip 1 are connected to transformer 0[0 ], [0 ] and 13], the transformer 0[0 ], [ 13] is connected to RJ45 [ 8 ] GE interface, RJ45 [ 4 ] GE interface, and RJ45 [ 4 ] electrical port, and the PHY chip 1 is connected to SFP [ 4 ] GE optical port.

10. A switch, characterized in that it comprises at least a motherboard according to any of claims 1 to 9.