CN217882823U - PWM enables control circuit with STO and alarm turn-off function - Google Patents
PWM enables control circuit with STO and alarm turn-off function Download PDFInfo
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- CN217882823U CN217882823U CN202221309691.XU CN202221309691U CN217882823U CN 217882823 U CN217882823 U CN 217882823U CN 202221309691 U CN202221309691 U CN 202221309691U CN 217882823 U CN217882823 U CN 217882823U
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Abstract
The utility model belongs to the technical field of servo, concretely relates to PWM enables control circuit with STO and alarm turn-off function, latch the unit including singlechip, STO acquisition circuit, logic judgement unit, PWM output unit, IGBT drive and power unit and alarm, STO acquisition circuit's output the alarm latch the output of unit all with logic judgement unit connects, logic judgement unit's output with PWM output unit's input is connected, IGBT drive and power unit's output is connected with the alarm and produces the circuit, the alarm produce the output of circuit with the input of alarm latch unit is connected. The utility model relates to an ingenious accords with the control logic of fault and STO that overflows, can turn off IGBT drive signal's output enable by the quick response, can quick response after breaking down and triggering the STO state, protection servo driver and whole motion control system.
Description
Technical Field
The utility model belongs to the technical field of servo, concretely relates to PWM enables control circuit with STO and alarm turn-off function.
Background
In the safety and protection design of the alternating current servo driver, when serious faults such as overcurrent and the like occur in the servo driver, the IGBT needs to be immediately turned off so as to avoid overcurrent damage of the IGBT. Meanwhile, with the improvement of safety requirements in industrial application sites, the STO function is more and more widely applied. The STO function requires that the servo driver be shut down in a safe torque condition when an external STO signal is abnormally input, and the servo driver resumes output when the external STO signal is restored. However, in the prior art, the control logic of the overcurrent fault and the STO is complex, the output enable of the IGBT driving signal cannot be quickly turned off, and the protection effect is limited.
SUMMERY OF THE UTILITY MODEL
The utility model discloses problem to prior art provides a PWM enables control circuit with STO and alarm turn-off function, accords with the control logic of overflowing trouble and STO, and the output that can quick response turn-off IGBT drive signal enables, can quick response after breaking down and triggering the STO state, protection servo driver and whole motion control system.
In order to solve the technical problem, the utility model discloses a model is following technical scheme:
the utility model provides a PWM enables control circuit with STO and alarm turn-off function, includes singlechip, STO acquisition circuit, logic judgement unit, PWM output unit, IGBT drive and power unit and alarm latch unit, the output of singlechip, the output of STO acquisition circuit, alarm latch unit's output all with logic judgement unit connects, the output of singlechip and logic judgement unit's output with PWM output unit's input is connected, IGBT drive and power unit's output is connected with the alarm and produces the circuit, the output that the alarm produced the circuit with alarm latch unit's input is connected.
The input end of the alarm latch unit is connected with a reset circuit.
The alarm latch unit comprises an NAND gate U1, an NAND gate U2, an NAND gate U3, an NAND gate U4 and an AND gate U5, wherein the output end of an alarm generating circuit is connected with a pin 1 of the input pin of the NAND gate U1, a pin 4 of the output pin of the NAND gate U1 is connected with a pin 1 of the input pin of the NAND gate U2, a pin 2 of the input pin of the NAND gate U2 is connected with the output end of the reset circuit, a pin 4 of the output pin of the NAND gate U2 is connected with a pin 2 of the input pin of the NAND gate U1, the output end of the alarm generating circuit is connected with a pin 1 of the input pin of the NAND gate U3, a pin 4 of the output pin of the NAND gate U3 is connected with a pin 1 of the input pin of the NAND gate U4, a pin 2 of the input pin of the NAND gate U4 is connected with the output end of the reset circuit, a pin 4 of the NAND gate U4 is connected with a pin 2 of the input pin of the NAND gate U3, an output pin of the NAND gate U2 is connected with a pin 1 of the AND gate U5, and an output pin of the NAND gate U4 is connected with a pin 4 of the AND gate U5.
The models of the NAND gates U1, U2, U3 and U4 are SN74LVC1G00DBVR respectively, and the model of the AND gate U5 is SN74LVC1G08DBVR respectively.
The logic judgment unit comprises an AND gate U6, an AND gate U7, an NAND gate U8 and an NAND gate U9, wherein a pin 1 of an input pin of the AND gate U6 is connected with the output end of the single chip microcomputer, a pin 2 of an input pin of the AND gate U6 is connected with the input end of the alarm latch unit, a pin 1 of an input pin of the NAND gate U8 is connected with the input end of the STO acquisition circuit, a pin 4 of an output pin of the AND gate U6 is connected with a pin 2 of an input pin of the NAND gate U8, a pin 1 of an input pin of the AND gate U7 is connected with the output end of the single chip microcomputer, a pin 2 of an input pin of the AND gate U7 is connected with the input end of the alarm latch unit, a pin 1 of an input pin of the NAND gate U9 is connected with the input end of the STO acquisition circuit, a pin 4 of an output pin of the AND gate U7 is connected with a pin 2 of an input pin of the NAND gate U9, and pins 4 of the output pins of the NAND gate U8 and 4 of the NAND gate U9 are connected with the input end of the PWM output unit.
The models of the nand gate U6 and the nand gate U7 are both SN74LVC1G00DBVR, and the models of the and gate U8 and the and gate U9 are both SN74LVC1G08DBVR.
Wherein, PWM output unit includes syntropy buffer U10A and syntropy buffer U10B, buffer U10A's input and syntropy buffer U10B's input all with the output of singlechip is connected, the output of logic judgement unit with buffer U10A's input and syntropy buffer U10B's input is connected, syntropy buffer U10A's output and syntropy buffer U10B's output has connect pull-down resistance R1 and pull-down resistance R2 respectively.
The model numbers of the cocurrent buffer U10A and the cocurrent buffer U10B are SN74ABT244APWR.
The utility model has the advantages that: the utility model discloses novel structure, design benefit, IGBT drive and power unit's operating condition produces the circuit through the alarm and exports alarm latch unit to, the logic judges the unit and receives STO signal and alarm latch unit's signal simultaneously, judge the back again with signal transmission to PWM output unit, PWM output unit controls IGBT drive and power unit again whether work, accord with the control logic of overflowing trouble and STO, can turn off IGBT drive signal's output enable by the quick response, can the quick response after breaking down and triggering the STO state, protection servo driver and whole motion control system.
Drawings
Fig. 1 is a schematic block diagram of the circuit of the present invention.
Fig. 2 is a schematic diagram of the present invention.
Fig. 3 is a circuit simulation diagram of the present invention.
The reference numbers are respectively: 1. the device comprises a singlechip, 2, an STO acquisition circuit, 3, a logic judgment unit, 4, a PWM output unit, 5, an IGBT driving and power unit, 6, an alarm latch unit, 7, an alarm generation circuit, 8 and a reset circuit.
Detailed Description
In order to facilitate understanding of those skilled in the art, the present invention will be further described with reference to the following examples and drawings, which are not intended to limit the present invention. The present invention will be described in detail with reference to the accompanying drawings.
A PWM (pulse-width modulation) enabling control circuit with STO and alarm turn-off functions is disclosed, and comprises a single chip microcomputer 1, an STO acquisition circuit 2, a logic judgment unit 3, a PWM output unit 4, an IGBT (insulated gate bipolar transistor) driving and power unit 5 and an alarm latch unit 6, wherein the output end of the single chip microcomputer 1, the output end of the STO acquisition circuit 2 and the output end of the alarm latch unit 6 are all connected with the logic judgment unit 3, the output end of the single chip microcomputer 1 and the output end of the logic judgment unit 3 are connected with the input end of the PWM output unit 4, the output end of the IGBT driving and power unit 5 is connected with an alarm generation circuit 7, and the output end of the alarm generation circuit 7 is connected with the input end of the alarm latch unit 6, as shown in figures 1-3. Specifically, the working state of the IGBT driving and power unit 5 is output to the alarm latch unit 6 through the alarm generating circuit 7, the logic judgment unit 3 receives an STO signal and a signal of the alarm latch unit 6 at the same time, the signal is transmitted to the PWM output unit 4 after judgment, the PWM output unit 4 controls the IGBT driving and power unit 5 to work or not, the control logic of overcurrent fault and STO is met, the output enable of the IGBT driving signal can be quickly responded and shut off, the quick response can be realized after the fault occurs and the STO state is triggered, and a servo driver and the whole motion control system are protected.
In the PWM enable control circuit having STO and alarm turn-off function described in this example, the input terminal of the alarm latch unit 6 is connected to the reset line 8.
In the PWM enable control circuit with STO and alarm shutdown functions in this embodiment, the alarm latch unit 6 includes a nand gate U1, a nand gate U2, a nand gate U3, a nand gate U4, and a nand gate U5, an output terminal of the alarm generation circuit 7 is connected to a pin 1 of an input pin of the nand gate U1, a pin 4 of an output pin of the nand gate U1 is connected to a pin 1 of an input pin of the nand gate U2, a pin 2 of an input pin of the nand gate U2 is connected to an output terminal of the reset circuit 8, a pin 4 of an output pin of the nand gate U2 is connected to a pin 2 of an input pin of the nand gate U1, an output pin 4 of the alarm generation circuit 7 is connected to a pin 1 of the nand gate U3, a pin 4 of the nand gate U3 is connected to a pin 1 of the nand gate U4, a pin 2 of the input pin of the nand gate U4 is connected to an output pin 2 of the nand gate U3, an output pin of the nand gate U2 is connected to a pin 1 of the nand gate U5, and a pin 4 of the and a pin 5 of the nand gate U4 is connected to a pin 5, and a pin of the output unit U5.
Specifically, the alarm generating circuit 7 can send/OCL and/SCL to the alarm latch unit 6, where/OCL and/SCL are fault alarm signals output by the over-current detection and IGBT supersaturation detection circuits inside the servo driver, respectively, and specifically, the/OCL is sent to the nand gate U1, the/SCL is sent to the nand gate U3, the/OCL _ N is sent by the output pin 4 of the nand gate U2, the/SCL _ N is sent by the output pin 4 of the nand gate U4, the RESET circuit 8 can send/RESET signals, the/RESET signals are alarm RESET signals, the/OCL and/SCL are single pulse signals, when an output short circuit occurs, the over-current is triggered instantaneously, the/OCL and/SCL represent alarm output in a low level state, and when the/RESET signals are high level and the/SCL signals are high level, the output/SCL _ N signals are high level. When the/OCL alarm low level pulse is triggered, the output/OCL _ N signal transitions to a low level with the change in/OCL. When the/OCL alarm low pulse ends to return to the high level, the/OCL _ N signal does not transition following the change in/OCL. When the/RESET signal transitions low, the/OCL _ N signal returns to the state of the current/OCL signal, in this way achieving the latching and resetting effect of the alarm signal. Similarly, when the/SCL alarm low level pulse is triggered, the output/SCL _ N signal transitions to a low level with a change in/SCL. When the/SCL alarm low level pulse ends to return to the high level, the/SCL _ N signal does not transition following the change of the/SCL. When the/RESET signal transitions to a low level, the/SCL _ N signal returns to the state of the current/SCL signal, in this way achieving the latching and resetting effect of the alarm signal. When both input pins of the and gate U5 are input with high level signals, the and gate output pin 4 outputs a driver fault signal/ERR as a high level signal to the logic determination unit 3. When any input end of the AND gate U5 receives a low level signal or simultaneously receives a plurality of low level signals, the AND gate output pin 4 outputs a driver fault signal/ERR as a low level signal to the logic judgment unit 3.
In the PWM-enabled control circuit with STO and alarm shutdown functions described in this example, the nand gate U1, the nand gate U2, the nand gate U3, and the nand gate U4 are all model numbers SN74LVC1G00DBVR, and the and gate U5 is all model numbers SN74LVC1G08DBVR.
In the PWM enable control circuit with STO and alarm shutdown functions, the logic determination unit 3 includes an and gate U6, an and gate U7, an nand gate U8, and an nand gate U9, a pin 1 of an input pin of the and gate U6 is connected to an output terminal of the single chip microcomputer 1, a pin 2 of an input pin of the and gate U6 is connected to an input terminal of the alarm latch unit 6, a pin 1 of an input pin of the nand gate U8 is connected to an input terminal of the alarm latch unit 2, a pin 4 of an output pin of the and gate U6 is connected to a pin 2 of an input pin of the nand gate U8, a pin 1 of an input pin of the and gate U7 is connected to an output terminal of the single chip microcomputer 1, a pin 2 of an input pin of the and gate U7 is connected to an input terminal of the alarm latch unit 6, a pin 1 of an input pin of the nand gate U9 is connected to an input terminal of the STO latch unit 2, a pin 4 of an output pin of the and a pin 4 of the nand gate U7 are connected to an input terminal of the PWM output unit 4.
Specifically, the single chip microcomputer 1 sends an EN-PWM signal to the logic judgment unit 3, the EN-PWM signal comprises an ENPWM _ UP signal and an ENPWM _ DN signal, the ENPWM _ UP signal is an IGBT upper arm PWM output enable signal output by the single chip microcomputer 1, the ENPWM _ DN signal is an IGBT lower arm PWM output enable signal output by the single chip microcomputer 1, the STO acquisition circuit 2 sends an STO signal to the logic judgment unit 3, the STO signal comprises an STO1 signal and an STO2 signal, the STO1 signal and the STO2 signal are external STO state signals output by an STO acquisition circuit, and the switching states of the IGBT upper arm and the IGBT lower arm are respectively controlled; the logic decision unit 3 can output/ENBUF signals including/ENBUF _ UP and/ENBUF _ DN to the PWM output unit 4. If the singlechip 1 sets the PWM enabling signals ENPWM _ UP and ENPWM _ DN low, no matter what level states other signals are, the control signal/ENBUF _ UP output by the NAND gate U8 and the control signal/ENBUF _ DN output by the NAND gate U9 are both high level. If the driver fail signal/ERR is a low level signal, the nand gate U8 outputs the control signal/ENBUF _ UP and the nand gate U9 outputs the control signal/ENBUF _ DN in a high level regardless of the level state of the other signals. When the single chip microcomputer 1 controls the IGBT to work, the single chip microcomputer 1 sets ENPWM _ UP and ENPWM _ DN to be high level, if the single chip microcomputer 1 sets the PWM enabling signals ENPWM _ UP and ENPWM _ DN to be high, and/ERR is high level, output pins of AND gates U6 and U7 set input pins 2 of NAND gates U8 and U9 to be high level. When the STO1 and STO2 signals are at a high level, the NAND gate U8 outputs a control signal/ENBUF _ UP and the NAND gate U9 outputs a control signal/ENBUF _ DN at a low level; if STO1 is low, NAND gate U8 outputs control signal/ENBUF _ UP as high; if STO2 is low, NAND gate U9 outputs control signal/ENBUF _ DN high.
In the PWM enable control circuit with STO and alarm shutdown functions described in this example, the models of the nand gate U6 and the nand gate U7 are both SN74LVC1G00DBVR, and the models of the and gate U8 and the and gate U9 are both SN74LVC1G08DBVR.
This example PWM enables control circuit with STO and alarm turn-off function, PWM output unit 4 includes syntropy buffer U10A and syntropy buffer U10B, buffer U10A's input and syntropy buffer U10B's input all with singlechip 1's output is connected, logic judge unit 3's output with buffer U10A's input and syntropy buffer U10B's input is connected, syntropy buffer U10A's output and syntropy buffer U10B's output has connect pull-down resistance R1 and pull-down resistance R2 respectively.
Specifically, PWM output unit 4 is capable of sending GATE _ U/V/W signals to IGBT drive and power unit 5, the GATE _U/V/W signals including UPGATE _ U/V/W signals and DNGATE _ U/V/W signals. The single chip microcomputer 1 respectively sends a PWM _ U/V/W _ UP signal and a PWM _ U/V/W _ DN signal to the syntropy buffer U10A and the syntropy buffer U10B, and the PWM _ U/V/W _ UP signal and the PWM _ U/V/W _ DN signal are output PWM signals. when/ENBUF _ UP is low, the syntropy buffer U10A outputs a PWM drive signal UPGATE _ U/V/W of an upper arm of the IGBT; otherwise, the output end Y of the equidirectional buffer U10A is closed, the three PWM driving signals on the upper arm of the IGBT are pulled down to a low level by the pull-down resistor R1, and the upper arm of the IGBT is turned off. when/ENBUF _ DN is at low level, the syntropy buffer U10B outputs a PWM driving signal DNGATE _ U/V/W of the IGBT lower arm; otherwise, the output end Y of the buffer U10B is turned off, the three PWM driving signals of the IGBT lower arm are pulled down to a low level by the pull-down resistor R2, and the IGBT lower arm is turned off.
In the PWM enable control circuit with STO and alarm shutdown function in this example, the models of the in-phase buffer U10A and the in-phase buffer U10B are SN74ABT244APWR.
The above description is only for the preferred embodiment of the present invention, and the present invention is not limited to the above description, and although the present invention is disclosed in the preferred embodiment, it is not limited to the above description, and any person skilled in the art can make some changes or modifications to equivalent embodiments without departing from the scope of the present invention, but all the technical solutions of the present invention are within the scope of the present invention.
Claims (8)
1. A PWM enable control circuit having STO and alarm shutdown, characterized by: the alarm device comprises a single chip microcomputer, an STO acquisition circuit, a logic judgment unit, a PWM output unit, an IGBT driving and power unit and an alarm latch unit, wherein the output end of the single chip microcomputer, the output end of the STO acquisition circuit and the output end of the alarm latch unit are connected with the logic judgment unit, the output end of the single chip microcomputer and the output end of the logic judgment unit are connected with the input end of the PWM output unit, the output end of the IGBT driving and power unit is connected with an alarm generation circuit, and the output end of the alarm generation circuit is connected with the input end of the alarm latch unit.
2. A PWM enable control circuit with STO and alarm shutdown functionality according to claim 1, wherein: the input end of the alarm latch unit is connected with a reset circuit.
3. A PWM enable control circuit having STO and alarm shutdown functionality according to claim 2, wherein: the alarm latch unit comprises an NAND gate U1, an NAND gate U2, an NAND gate U3, an NAND gate U4 and an AND gate U5, wherein the output end of an alarm generating circuit is connected with a pin 1 of the input pin of the NAND gate U1, a pin 4 of the output pin of the NAND gate U1 is connected with a pin 1 of the input pin of the NAND gate U2, a pin 2 of the input pin of the NAND gate U2 is connected with the output end of the reset circuit, a pin 4 of the output pin of the NAND gate U2 is connected with a pin 2 of the input pin of the NAND gate U1, the output end of the alarm generating circuit is connected with a pin 1 of the input pin of the NAND gate U3, a pin 4 of the output pin of the NAND gate U3 is connected with a pin 1 of the input pin of the NAND gate U4, a pin 2 of the input pin of the NAND gate U4 is connected with the output end of the reset circuit, a pin 4 of the NAND gate U4 is connected with a pin 2 of the input pin of the NAND gate U3, an output pin of the NAND gate U2 is connected with a pin 1 of the AND gate U5, and a pin 4 of the AND gate U5 is connected with a pin 4 of the output pin 4 of the AND gate U5.
4. A PWM enable control circuit with STO and alarm shutdown functionality according to claim 3, wherein: the models of the NAND gate U1, the NAND gate U2, the NAND gate U3 and the NAND gate U4 are SN74LVC1G00DBVR respectively, and the model of the AND gate U5 is SN74LVC1G08DBVR respectively.
5. A PWM enable control circuit with STO and alarm shutdown function according to claim 1, characterized in that: the logic judgment unit comprises an AND gate U6, an AND gate U7, an NAND gate U8 and an NAND gate U9, wherein a pin 1 of an input pin of the AND gate U6 is connected with the output end of the single chip microcomputer, a pin 2 of an input pin of the AND gate U6 is connected with the input end of the alarm latch unit, a pin 1 of an input pin of the NAND gate U8 is connected with the input end of the STO acquisition circuit, a pin 4 of an output pin of the AND gate U6 is connected with a pin 2 of an input pin of the NAND gate U8, a pin 1 of an input pin of the AND gate U7 is connected with the output end of the single chip microcomputer, a pin 2 of an input pin of the AND gate U7 is connected with the input end of the alarm latch unit, a pin 1 of an input pin of the NAND gate U9 is connected with the input end of the STO acquisition circuit, a pin 4 of an output pin of the AND gate U7 is connected with a pin 2 of an input pin of the NAND gate U9, and a pin 4 of an output pin 4 of the NAND gate U8 and a pin 4 of the NAND gate U9 are connected with the input end of the PWM output unit.
6. The PWM enable control circuit having STO and alarm shutdown functionality of claim 5, wherein: the models of the AND gate U6 and the AND gate U7 are both SN74LVC1G00DBVR, and the models of the NAND gate U8 and the NAND gate U9 are both SN74LVC1G08DBVR.
7. A PWM enable control circuit with STO and alarm shutdown function according to claim 1, characterized in that: PWM output unit includes syntropy buffer U10A and syntropy buffer U10B, buffer U10A's input and syntropy buffer U10B's input all with the output of singlechip is connected, the output of logic judgement unit with buffer U10A's input and syntropy buffer U10B's input is connected, syntropy buffer U10A's output and syntropy buffer U10B's output has connect pull-down resistance R1 and pull-down resistance R2 respectively.
8. The PWM enable control circuit with STO and alarm shutdown function according to claim 7, wherein: the model of each of the cocurrent buffer U10A and the cocurrent buffer U10B is SN74ABT244APWR.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221309691.XU CN217882823U (en) | 2022-05-27 | 2022-05-27 | PWM enables control circuit with STO and alarm turn-off function |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221309691.XU CN217882823U (en) | 2022-05-27 | 2022-05-27 | PWM enables control circuit with STO and alarm turn-off function |
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| CN217882823U true CN217882823U (en) | 2022-11-22 |
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