CN217879497U - High signal-to-noise ratio processing circuit for partial discharge signal processing - Google Patents
High signal-to-noise ratio processing circuit for partial discharge signal processing Download PDFInfo
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- CN217879497U CN217879497U CN202220959639.2U CN202220959639U CN217879497U CN 217879497 U CN217879497 U CN 217879497U CN 202220959639 U CN202220959639 U CN 202220959639U CN 217879497 U CN217879497 U CN 217879497U
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Abstract
The utility model relates to the technical field of power measurement, and discloses a high signal-to-noise ratio processing circuit for partial discharge signal processing, which adopts the technical scheme that the processing circuit comprises an acquisition circuit, a signal conditioning circuit and a power frequency trap circuit which are electrically connected correspondingly, wherein the acquisition circuit comprises a transient voltage-to-ground voltage sensor, and is used for acquiring the waveform and amplitude of pulse voltage and outputting a pulsating differential voltage signal; the signal conditioning circuit is used for reading the differential voltage signal, suppressing electromagnetic noise in the differential voltage signal and outputting a discharge waveform; and the power frequency trap circuit is used for trapping the power frequency signal of the power system in the discharge waveform and outputting the signal to the MCU control circuit.
Description
Technical Field
The utility model relates to an electric power measurement technical field, more specifically say that it relates to a high SNR processing circuit for signal processing is put in office.
Background
Along with the rapid development of electric power industry in China, the power utilization capacity is continuously enlarged, and the stable operation of electric power equipment is particularly important. In the operation of an electric power system, partial discharge is a relatively common fault which is not easy to find in time. Therefore, a partial discharge detection technology has been developed to find partial discharge as early as possible and reduce the damage to the power system. The conventional detection methods at present are divided into two categories of electrical measurement and non-electrical measurement, the electrical measurement method is to detect through the charge effect caused by partial discharge, and the typical method comprises the following steps: a pulse current method, a radio interference method, a transient earth wave method, and the like. The non-electrical measurement method is a measurement method using ultrasonic, optical, chemical analysis and the like, and typical methods include: ultrasonic method, optical detection method, thermal detection method, etc.
The most common methods among the partial discharge detection methods are:
pulse current method: the charge migration can be generated in the process of partial discharge, the charge migration can generate pulse current in a measuring loop, and the measurement of the partial discharge is realized through the measurement of the pulse current. The technology is the earliest studied and the application is the most extensive one.
Transient geoelectrical wave method: when a partial discharge event occurs in the insulation of the high-voltage switchgear cabinet, it generates electromagnetic waves in the radio frequency range, which can leak from the interior of the switchgear cabinet to the exterior surface through the opening in the metal housing. These openings may be gaps around the housing or sealing gaskets or other insulating components. When the electromagnetic wave propagates to the outside of the switchgear, it generates a transient ground voltage, also called a transient ground voltage (TEV), on the grounded metal enclosure. The transient radio wave amplitude is in the range of several millivolts to several volts, and has a short rise time in the order of nanoseconds. When the switch cabinet operates, the probe is attached to the surface of the cabinet body to carry out measurement.
Ultrasonic detection: the discharge failure is judged by detecting an ultrasonic signal generated at the time of discharge. Utilize ultrasonic sensor laminating to monitor at equipment housing, also can detect through supporting earphone.
However, the above detection methods have advantages and disadvantages: the pulse current method has the conditions that the current is small and discontinuous, the field interference is easy to occur, the current cannot be detected even if the equipment such as a transformer discharges internally, and the sensitivity has adverse effects on the accuracy of measurement.
The transient electric wave method has the advantages that the insulation defect of the switch cabinet can be found as soon as possible, and good detection sensitivity can be realized; according to the attenuation and the time difference of the electromagnetic pulse signals, the partial discharge can be positioned. The disadvantage is that the detection signal is easily interfered by electromagnetic interference of measuring environment.
The ultrasonic detection method is easy to realize on-line detection and space positioning, but various media have different influences on the attenuation of ultrasonic waves, so that the discharge capacity cannot be quantitatively analyzed by the ultrasonic detection method. The current ultrasonic sensor has low sensitivity, and reduces the detection accuracy.
The partial discharge detection is mainly applied to the power equipment, and the power equipment can generate electromagnetic noise with various components during operation, so the application environment determines that the partial discharge detection equipment can work in a complex electromagnetic environment and is inevitably interfered by the electromagnetic noise. In the initial stage of the device discharging, the discharging signal may be weak, but the noise is large, so that a detection method with better accuracy is required to be designed based on the operating environment characteristics of the partial discharge detection device.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a high SNR treatment circuit for signal processing is put in office, whole circuit has realized the low noise influence, and high common mode rejection ratio carries out the limit wave alone to the power frequency interference among the electric power system and handles, has improved the reliability that the discharge signal detected.
The above technical purpose of the present invention can be achieved by the following technical solutions: a high signal-to-noise ratio processing circuit for partial discharge signal processing comprises an acquisition circuit, a signal conditioning circuit and a power frequency trap circuit which are electrically connected correspondingly, wherein the acquisition circuit comprises a transient voltage-to-ground voltage sensor and is used for acquiring the waveform and amplitude of pulse voltage and outputting a pulsating differential voltage signal;
the signal conditioning circuit is used for reading the differential voltage signal, suppressing electromagnetic noise in the differential voltage signal and outputting a discharge waveform;
and the power frequency trap circuit is used for trapping the power frequency signal of the power system in the discharge waveform and outputting the signal to the MCU control circuit.
As a preferred technical solution of the present invention, the differential voltage signal includes a discharge waveform and electromagnetic noise.
As a preferred technical scheme of the utility model, the acquisition circuit includes transient state earth voltage sensor, first inductance, the second inductance, the third inductance, first electric capacity, the second electric capacity, the third electric capacity, the fourth electric capacity, two GND terminals of transient state earth voltage sensor are connected with the equipment under test face respectively, the IPEX terminal of transient state earth voltage sensor, the first end of first inductance, the first end of first electric capacity is connected, the second end of first electric capacity, the first end of second electric capacity is connected, the second end of second inductance, the first end of third electric capacity is connected, the second end of third inductance, the first end of fourth electric capacity, signal conditioning circuit's input is connected, the second end of first electric capacity, the second end of second electric capacity, the second end of third electric capacity and the second end of fourth electric capacity are connected.
As an optimized technical solution of the present invention, the signal conditioning circuit includes a logarithmic amplifier, a first operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, and a tenth capacitor; the output end of the acquisition circuit, the first end of the first resistor and the first end of the fifth capacitor are connected, the second end of the fifth capacitor is connected with an INHI terminal pin of the demodulation logarithmic amplifier, the second end of the sixth capacitor is connected with an INLO terminal pin of the demodulation logarithmic amplifier, the first end of the seventh capacitor is connected with a BFIN terminal pin of the demodulation logarithmic amplifier, a COMM terminal pin of the demodulation logarithmic amplifier is grounded, an OFLT terminal pin of the demodulation logarithmic amplifier is connected with the first end of the ninth capacitor, an ENBL terminal pin of the demodulation logarithmic amplifier, a VPOS terminal pin of the demodulation logarithmic amplifier, the first end of the second resistor and the first end of the eighth capacitor are connected, the second end of the second resistor is connected with the power supply, a VOUT end of the demodulation logarithmic amplifier is connected with the first end of the third resistor, the second end of the third resistor is connected with a positive input pin of the first operational amplifier, the negative input pin of the first operational amplifier, the first end of the fourth resistor and the first end of the fifth resistor are connected, the negative power supply pin of the first operational amplifier, the first end of the sixth resistor and the first end of the tenth capacitor are connected, the second end of the sixth resistor is connected with the power supply, the second end of the fifth resistor, the output end of the first operational amplifier and the first end of the seventh resistor are connected, the second end of the seventh resistor is connected with the power frequency trap circuit, and the second end of the first resistor, the first end of the sixth capacitor, the second end of the seventh capacitor, the second end of the ninth capacitor, the second end of the eighth capacitor, the second end of the fourth resistor, the positive power supply pin of the first operational amplifier and the second end of the tenth capacitor are connected with the tested device surface.
As a preferred technical solution of the present invention, the power frequency trap circuit includes a second operational amplifier, a potentiometer, an eleventh capacitor, a twelfth capacitor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, an output end of the signal conditioning circuit, a first end of the eighth resistor, a first end of the ninth resistor, a first end of the thirteenth resistor, a second end of the eighth resistor, a first end of the eleventh capacitor, a first end of the twelfth capacitor, a second end of the ninth resistor, and a first end of the tenth resistor are connected, a second end of the eleventh capacitor, a first end of the eleventh resistor, a first end of the twelfth resistor, and an output end of the second operational amplifier are connected, a negative input pin of the second operational amplifier, a second end of the eleventh resistor, and a second end of the twelfth capacitor are connected, a positive input pin of the second operational amplifier, a tested device surface, and a first end of the potentiometer are connected, a second end of the tenth resistor is connected to a second end of the potentiometer, a second end of the twelfth resistor, and a second end of the thirteenth resistor is connected to the MCU.
As a preferred technical scheme of the utility model, the model of adjusting logarithmic amplifier is AD8310ARMZ.
As a preferred technical solution of the present invention, the model of the first operational amplifier is AD8606ARZ.
As a preferred technical solution of the present invention, the second operational amplifier is an AD8606 series chip.
To sum up, the utility model discloses following beneficial effect has: the whole signal circuit only consists of three functional circuits, namely an acquisition circuit, a signal conditioning circuit and a power frequency trap circuit, and the circuit design is simplified, so that the realization of actual production and copying is facilitated; the signal conditioning circuit is provided with the detection and regulation logarithmic amplifier, so that the technical requirements of low-cost and high-precision acquisition, conversion and output of high-frequency small-amplitude signals are met, and the practical detection and use are facilitated; the whole circuit realizes low noise influence and high common mode rejection ratio, and independently carries out wave-limiting processing on power frequency interference in a power system, thereby improving the reliability of the partial discharge instrument for detecting discharge signals.
Drawings
Fig. 1 is a circuit block diagram of the present invention;
FIG. 2 is a schematic diagram of the acquisition circuit of the present invention;
FIG. 3 is a schematic diagram of the signal conditioning circuit of the present invention;
FIG. 4 is a schematic diagram of a power frequency notch circuit of the present invention;
fig. 5 is a schematic diagram of the MCU control circuit of the present invention.
In the figure: p5, a transient voltage-to-ground voltage sensor; l1, a first inductor; l2 and a second inductor; l3, a third inductor; c36, a first capacitor; c37, a second capacitor; c38, a third capacitor; c39 and a fourth capacitor; u9, a detection and regulation logarithmic amplifier; U10A, a first operational amplifier; r36 and a first resistor; r27 and a second resistor; r39 and a third resistor; r37 and a fourth resistor; r35 and a fifth resistor; r28 and a sixth resistor; r38 and a seventh resistor; c35 and a fifth capacitor; c43, a sixth capacitor; c32 and a seventh capacitor; c33, an eighth capacitor; c45 and a ninth capacitor; c34, a tenth capacitance; U1B, a second operational amplifier; p1, a potentiometer; c2, an eleventh capacitor; c4, a twelfth capacitor; r4 and an eighth resistor; r7 and a ninth resistor; r8, tenth resistance; r2 and an eleventh resistor; r3, a twelfth resistor; r11 and a thirteenth resistor; GND1, device under test plane.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides a high signal-to-noise ratio processing circuit for partial discharge signal processing, which includes an acquisition circuit, a signal conditioning circuit and a power frequency trap circuit that are electrically connected;
the acquisition circuit comprises a transient voltage-to-ground voltage sensor P5 for acquiring the waveform and amplitude of pulse voltage and outputting a pulsating differential voltage signal, wherein the differential voltage signal comprises a discharge waveform and electromagnetic noise; when partial discharge occurs in the tested device, a pulsating voltage can be induced on the ferromagnetic surface, the transient voltage-to-ground voltage sensor P5 can detect the waveform and amplitude of the pulsating voltage, and a high-speed pulsating differential voltage signal is output, wherein the signal has a discharge waveform and contains surrounding electromagnetic noise.
Specifically, as shown in fig. 2, the acquisition circuit includes a transient voltage-to-ground sensor P5, a first inductor L1, a second inductor L2, a third inductor L3, a first capacitor C36, a second capacitor C37, a third capacitor C38, and a fourth capacitor C39, two GND terminals of the transient voltage-to-ground sensor P5 are respectively connected to the device under test plane GND1, an IPEX terminal of the transient voltage-to-ground sensor P5, a first terminal of the first inductor L1, and a first terminal of the first capacitor C36 are connected, a second terminal of the first capacitor C36, a first terminal of the second capacitor C37, and a first terminal of the second capacitor C37 are connected, a second terminal of the second inductor L2, a first terminal of the third inductor L3, and a first terminal of the third capacitor C38 are connected, a second terminal of the third inductor L3, a first terminal of the fourth capacitor C39, and an input terminal of the signal conditioning circuit are connected, and a second terminal of the first capacitor C36, a second terminal of the second capacitor C37, a second terminal of the second capacitor C38, a second terminal of the third capacitor C38, and a second terminal of the fourth capacitor C39 are connected.
The signal output by the transient voltage-to-ground voltage sensor P5 is input to a Butterworth filter composed of a first inductor, a second inductor, a third inductor, a fourth inductor and a fourth capacitor, and when the transient voltage-to-ground voltage sensor is specifically implemented, the precision of the device is 1%, and the precision of the cut-off frequency of the filter is guaranteed.
The signal conditioning circuit is used for reading the differential voltage signal, suppressing electromagnetic noise in the differential voltage signal and outputting a discharge waveform;
through the analysis of the type of the output signal of the transient voltage-to-ground voltage sensor P5, it can be known that the discharge signal is mainly a differential signal with high-speed pulsation, and the electromagnetic noise is mainly represented by a common-mode signal. Therefore, the differential signal output by the TEV sensor needs to be completely read in the function of the preprocessing circuit, the common-mode signal mainly interfered by electromagnetic noise can be strongly inhibited, and the influence on the differential signal is reduced.
Specifically, the signal conditioning circuit includes a demodulation logarithmic amplifier U9, a first operational amplifier U10A, a first resistor R36, a second resistor R27, a third resistor R39, a fourth resistor R37, a fifth resistor R35, a sixth resistor R28, a seventh resistor R38, a fifth capacitor C35, a sixth capacitor C43, a seventh capacitor C32, an eighth capacitor C33, a ninth capacitor C45, and a tenth capacitor C34;
the specific circuit composition is as follows: the output end of the acquisition circuit, the first end of the first resistor R36 and the first end of the fifth capacitor C35 are connected, the second end of the fifth capacitor C35 is connected with the INHI terminal pin of the demodulation logarithmic amplifier U9, the second end of the sixth capacitor C43 is connected with the INLO terminal pin of the demodulation logarithmic amplifier U9, the first end of the seventh capacitor C32 is connected with the BFIN terminal pin of the demodulation logarithmic amplifier U9, the COMM terminal pin of the demodulation logarithmic amplifier U9 is grounded, the OFLT terminal pin of the demodulation logarithmic amplifier U9 is connected with the first end of the ninth capacitor C45, the ENBL terminal pin of the demodulation logarithmic amplifier U9, the VPOS terminal pin of the demodulation logarithmic amplifier U9, the first end of the second resistor R27 and the first end of the eighth capacitor C33 are connected, the second end of the second resistor R27 is connected with the power supply, the VOUT terminal of the demodulation logarithmic amplifier U9 is connected with the first end of the third resistor R39, the second end of the third resistor R39 is connected with the positive input pin of the operational amplifier U10A, a negative input pin of the first operational amplifier U10A, a first end of the fourth resistor R37, and a first end of the fifth resistor R35 are connected, a negative power supply pin of the first operational amplifier U10A, a first end of the sixth resistor R28, and a first end of the tenth capacitor C34 are connected, a second end of the sixth resistor R28 is connected to the power supply, a second end of the fifth resistor R35, an output end of the first operational amplifier U10A, and a first end of the seventh resistor R38 are connected, a second end of the seventh resistor R38 is connected to the power frequency trap circuit, a second end of the first resistor R36, a first end of the sixth capacitor C43, a second end of the seventh capacitor C32, a second end of the ninth capacitor C45, a second end of the eighth capacitor C33, a second end of the fourth resistor R37, a positive power supply pin of the first operational amplifier U10A, and a second end of the tenth capacitor C34 are connected to the GND plane 1 of the device under test.
During actual circuit operation, the signal output by the transient voltage-to-ground voltage sensor P5 is filtered and then input to the logarithmic detection amplifier U9, as shown in fig. 3, the logarithmic detection amplifier U9 is an AD8310ARMZ device of ADI corporation, which performs down-conversion processing on the signal of the high-frequency transient voltage-to-ground voltage sensor P5 to output, so as to facilitate the processing of the subsequent circuit. And the detection and regulation logarithmic amplifier U9 has the characteristics of high input impedance (1 k omega | | |1.4 pF), ultralow noise (1.28 nV/HZ) and high-speed voltage output (the maximum working frequency is 400 MHz), and is convenient for practical use.
When actual circuit elements are selected, the first operational amplifier U10A is an AD8606ARZ series chip adopting an ADI formula, and a high-precision operational amplifier circuit can be realized. The chip has low offset (MAX 65 uV), low noise (less than 8 nV/HZ) and high common mode rejection ratio (more than 100 dB); the signal conditioning circuit formed by the circuit can reduce noise and improve effective signals, so that the output voltage reaches the range which can be identified by the MCU control circuit ADC.
The demodulation logarithmic amplifier U9 and the auxiliary resistor capacitor form a demodulation logarithmic amplifier U9 circuit, and in order to work in cooperation with the demodulation logarithmic amplifier U9, the first resistor R36 takes a value of 52.3 omega with the precision of 1%. The values of the fifth capacitor C35 and the sixth capacitor C43 are 1uF, and the precision is 10%. The first resistor R36, the fifth capacitor C35 and the sixth capacitor C43 form a high-pass input and are matched to the input stage of the demodulation logarithmic amplifier U9. The second resistor R27 and the seventh capacitor C32 are used for decoupling and filtering to improve the stability of chip power supply. The seventh capacitor C32 is also used to set the signal bandwidth. The ninth capacitor C45 is used for offset compensation of the signal. The fifth resistor R35 is a thick film resistor with the precision of 10K omega 1%, and the fourth resistor R37 is a thick film resistor with the precision of 100K omega-400K omega 1% and is used for amplifying signals to a proper range.
And the power frequency trap circuit is used for trapping power frequency signals of the power system in the discharge waveform and outputting the signals to the MCU control circuit. Generally, a power frequency signal of a power system generates an interference signal, and a frequency range of a partial discharge signal in the power system is much higher than that of the power frequency signal, so that a separate notch processing needs to be performed on the power frequency signal.
Specifically, as shown in fig. 4, the power frequency notch circuit includes a second operational amplifier U1B, a potentiometer P1, an eleventh capacitor C2, a twelfth capacitor C4, an eighth resistor R4, a ninth resistor R7, a tenth resistor R8, an eleventh resistor R2, a twelfth resistor R3, and a thirteenth resistor R11, wherein the output terminal of the signal conditioning circuit, the first terminal of the eighth resistor R4, the first terminal of the ninth resistor R7, and the first terminal of the thirteenth resistor R11 are connected, the second terminal of the eighth resistor R4, the first terminal of the eleventh capacitor C2, the first terminal of the twelfth capacitor C4, the second terminal of the ninth resistor R7, and the first terminal of the tenth resistor R8 are connected, the second end of the eleventh capacitor C2, the first end of the eleventh resistor R2, the first end of the twelfth resistor R3 and the output end of the second operational amplifier U1B are connected, the negative input pin of the second operational amplifier U1B, the second end of the eleventh resistor R2 and the second end of the twelfth capacitor C4 are connected, the positive input pin of the second operational amplifier U1B, the tested device surface GND1 and the first end of the potentiometer P1 are connected, the second end of the tenth resistor R8 is connected with the second end of the potentiometer P1, and the second end of the twelfth resistor R3 and the second end of the thirteenth resistor R11 are connected and connected to the MCU control circuit.
When circuit element selection is specifically carried out, the second operational amplifier U1B is an AD8606 series chip, and the second operational amplifier U1B, the eighth resistor R4, the ninth resistor R7, the tenth resistor R8, the eleventh resistor R2, the potentiometer P1, the eleventh capacitor C2 and the twelfth capacitor C4 form a multi-feedback active band-pass filter, so that only power frequency signals can pass through the multi-feedback active band-pass filter, and the phases of the multi-feedback active band-pass filter are opposite. The reversed signal and the original signal are added, so that the power frequency in the original signal is offset, and the function of power frequency wave limiting is realized. In practical application, the formula shows that C = C2= C4, R4 and R7 ≧ R8, and the center point of the wave-limiting frequency is only related to the potentiometer P1. Therefore, the eighth resistor R4, the ninth resistor R7, the tenth resistor R8 and the eleventh resistor R2 are thick-film resistors with the precision of 1%, the potentiometer P1 is a precision adjustable potentiometer P1, and the eleventh capacitor C2 and the twelfth capacitor C4 are low-temperature drift capacitors, so that the stability of the wave-limiting central frequency point is ensured.
As shown in FIG. 5, the MCU control circuit selects an STM32L476RET6 low-power consumption single chip microcomputer of ST company. The signal output after passing through the power frequency trap circuit enters the 11 pins of the U1 of the single chip microcomputer, the 11 pins are ADC conversion pins in the single chip microcomputer, and the signal can be quantitatively identified after being converted into digital quantity, so that the partial discharge signal detection of the tested equipment is realized.
The utility model discloses a high SNR processing circuit for signal processing is put in office's advantage lies in: the whole signal circuit only consists of three functional circuits, namely an acquisition circuit, a signal conditioning circuit and a power frequency trap circuit, and the circuit design is simplified, so that the realization of actual production and copying is facilitated; the signal conditioning circuit is provided with the detection and regulation logarithmic amplifier U9, so that the technical requirements of low-cost and high-precision acquisition, conversion and output of high-frequency small-amplitude signals are met, and the practical detection and use are facilitated; the whole circuit realizes low noise influence and high common mode rejection ratio, and independently carries out wave-limiting processing on power frequency interference in a power system, thereby improving the reliability of the partial discharge instrument for detecting discharge signals.
It is above only the utility model discloses a preferred embodiment, the utility model discloses a scope of protection does not only confine above-mentioned embodiment, the all belongs to the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. It should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A high signal-to-noise ratio processing circuit for partial discharge signal processing is characterized in that: the power frequency trap circuit comprises an acquisition circuit, a signal conditioning circuit and a power frequency trap circuit which are electrically connected correspondingly, wherein the acquisition circuit comprises a transient voltage-to-ground voltage sensor and is used for acquiring the waveform and amplitude of pulse voltage and outputting a pulsating differential voltage signal;
the signal conditioning circuit is used for reading the differential voltage signal, suppressing electromagnetic noise in the differential voltage signal and outputting a discharge waveform;
and the power frequency trap circuit is used for trapping the power frequency signal of the power system in the discharge waveform and outputting the signal to the MCU control circuit.
2. A high snr processing circuit for partial discharge signal processing according to claim 1, wherein: the differential voltage signal includes a discharge waveform and electromagnetic noise.
3. A high snr processing circuit for partial discharge signal processing according to claim 2, wherein: the acquisition circuit comprises a transient earth voltage sensor, a first inductor, a second inductor, a third inductor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, wherein two GND ends of the transient earth voltage sensor are respectively connected with the tested device surface, the IPEX terminal of the transient earth voltage sensor, the first end of the first inductor, the first end of the first capacitor is connected, the second end of the first capacitor, the first end of the second capacitor is connected, the second end of the second inductor, the first end of the third capacitor is connected, the second end of the third inductor, the first end of the fourth capacitor, the input end of the signal conditioning circuit is connected, the second end of the first capacitor, the second end of the second capacitor, the second end of the third capacitor and the second end of the fourth capacitor are connected.
4. A high snr processing circuit for partial discharge signal processing according to claim 3, wherein: the signal conditioning circuit comprises a detection and regulation logarithmic amplifier, a first operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a tenth capacitor; the output end of the acquisition circuit, the first end of the first resistor and the first end of the fifth capacitor are connected, the second end of the fifth capacitor is connected with an INHI terminal pin of the detection and regulation logarithmic amplifier, the second end of the sixth capacitor is connected with an INLO terminal pin of the detection and regulation logarithmic amplifier, the first end of the seventh capacitor is connected with a BFIN terminal pin of the detection and regulation logarithmic amplifier, a COMM terminal pin of the detection and regulation logarithmic amplifier is grounded, an OFLT terminal pin of the detection and regulation logarithmic amplifier is connected with the first end of the ninth capacitor, an ENBL terminal pin of the detection and regulation logarithmic amplifier, a VPOS terminal pin of the detection and regulation logarithmic amplifier, the first end of the second resistor and the first end of the eighth capacitor are connected, the second end of the second resistor is connected with a power supply, the VOUT end of the detection and regulation logarithmic amplifier is connected with the first end of the third resistor, the second end of the third resistor is connected with the positive input pin of the first operational amplifier, the negative input pin of the first operational amplifier, the first end of the fourth resistor and the first end of the fifth resistor are connected, the negative power supply pin of the first operational amplifier, the first end of the sixth resistor and the first end of the tenth capacitor are connected, the second end of the sixth resistor is connected with the power supply, the second end of the fifth resistor, the output end of the first operational amplifier and the first end of the seventh resistor are connected, the second end of the seventh resistor is connected with the power frequency trap circuit, and the second end of the first resistor, the first end of the sixth capacitor, the second end of the seventh capacitor, the second end of the ninth capacitor, the second end of the eighth capacitor, the second end of the fourth resistor, the positive power supply pin of the first operational amplifier and the second end of the tenth capacitor are connected with the tested device surface.
5. A high snr processing circuit for partial discharge signal processing according to claim 4, wherein: the power frequency trap circuit comprises a second operational amplifier, a potentiometer, an eleventh capacitor, a twelfth capacitor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor and a thirteenth resistor, an output end of the signal conditioning circuit, a first end of the eighth resistor, a first end of the ninth resistor and a first end of the thirteenth resistor are connected, a second end of the eighth resistor, a first end of the eleventh capacitor, a first end of the twelfth capacitor, a second end of the ninth resistor and a first end of the tenth resistor are connected, a second end of the eleventh capacitor, a first end of the eleventh resistor, a first end of the twelfth resistor and an output end of the second operational amplifier are connected, a negative input pin of the second operational amplifier, a second end of the eleventh resistor and a second end of the twelfth capacitor are connected, a positive input pin of the second operational amplifier, a tested device surface and a first end of the potentiometer are connected, a second end of the tenth resistor is connected with a second end of the potentiometer, and a second end of the twelfth resistor and a second end of the thirteenth resistor are connected and connected into the MCU control circuit.
6. A high snr processing circuit for partial discharge signal processing according to claim 5, wherein: the model of the detection and regulation logarithmic amplifier is AD8310ARMZ.
7. A high snr processing circuit for partial discharge signal processing according to claim 6, wherein: the model of the first operational amplifier is AD8606ARZ.
8. A high snr processing circuit for partial discharge signal processing according to claim 7, wherein: the second operational amplifier is an AD8606 series chip.
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| CN202220959639.2U CN217879497U (en) | 2022-04-25 | 2022-04-25 | High signal-to-noise ratio processing circuit for partial discharge signal processing |
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