CN217847956U - Display substrate, display panel and display device - Google Patents

Abstract

Provided are a display substrate, a display panel and a display device. The display substrate comprises a display pixel area and a first virtual pixel area, a plurality of virtual sub-pixel structures are arranged on the substrate and located in the first virtual pixel area, and at least one virtual sub-pixel structure comprises a first compensation capacitor and a second compensation capacitor. The first scanning signal line is electrically connected to the gate of the fourth transistor of the pixel driving circuit of each sub-pixel in a row of sub-pixels, and is also electrically connected to the first compensation capacitor of the at least one dummy sub-pixel structure. The second scan signal line is electrically connected to a gate of the second transistor of the pixel driving circuit of each of the sub-pixels in a row of the sub-pixels, and is also electrically connected to the second compensation capacitor of the at least one dummy sub-pixel structure.

Description

Display substrate, display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a display panel, and a display device.

Background

With the increasing demand of users for diversified use of display devices and the emergence of design requirements for high screen occupation ratio of display devices, display devices with comprehensive screen design are becoming more and more popular among consumers. In a full screen design, can form the trompil in the display screen, place hardware module such as camera in this trompil to realize the design of full screen. In such a design, the normal light-emitting pixels in the row where the opening is located are more missing, which causes a larger difference between the load of the row where the opening is located and the load of other rows, and affects the charging time of the pixel circuit, thereby adversely affecting the display effect.

The above information disclosed in this section is only for understanding of the background of the technical idea of the present disclosure, and therefore, the above information may contain information that does not constitute prior art.

SUMMERY OF THE UTILITY MODEL

In one aspect, there is provided a display substrate including a display pixel region and a first dummy pixel region, the display substrate including:

a base substrate;

a plurality of sub-pixels disposed on the substrate and in the display pixel region, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, each sub-pixel including a pixel driving circuit, the pixel driving circuit including a driving transistor, a second transistor, and a fourth transistor, each of the driving transistor, the second transistor, and the fourth transistor including a gate electrode, a first pole, and a second pole, the first pole of the second transistor being electrically connected to one of the first pole and the second pole of the driving transistor, the second pole of the second transistor being electrically connected to the gate electrode of the driving transistor, the fourth transistor being for controlling writing of a data signal;

a plurality of dummy sub-pixel structures disposed on the substrate and located in the first dummy pixel region, at least one of the dummy sub-pixel structures including a first compensation capacitor and a second compensation capacitor; and

a first scanning signal line and a second scanning signal line provided on the substrate, the first scanning signal line being configured to supply a first scanning signal to a gate electrode of the fourth transistor, the second scanning signal line being configured to supply a second scanning signal to a gate electrode of the second transistor, the first scanning signal line and the second scanning signal line both extending through the display pixel region and the first dummy pixel region,

wherein the first scanning signal line is electrically connected to a gate of the fourth transistor of the pixel driving circuit of each sub-pixel in a row of sub-pixels, and the first scanning signal line is further electrically connected to the first compensation capacitor of the at least one dummy sub-pixel structure; and

the second scan signal line is electrically connected to a gate of the second transistor of the pixel driving circuit of each sub-pixel in a row of sub-pixels, and the second scan signal line is also electrically connected to the second compensation capacitor of the at least one dummy sub-pixel structure.

According to some exemplary embodiments, the display substrate includes a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a third conductive layer disposed on the substrate base, the first semiconductor layer, the first conductive layer, the second semiconductor layer, and the third conductive layer being sequentially disposed away from the substrate base; an active layer of the fourth transistor is located in the first semiconductor layer, and a gate of the fourth transistor is located in the first conductive layer; the active layer of the second transistor is located in the second semiconductor layer, the grid electrode of the second transistor comprises a bottom grid and a top grid, the bottom grid of the second transistor is located in the second conductive layer, and the top grid of the second transistor is located in the third conductive layer; in the first dummy pixel region, the display substrate includes: a first compensation structure in the first conductive layer; a second compensation structure in the second conductive layer; and a third compensation structure in the third conductive layer.

According to some exemplary embodiments, the first compensation capacitor comprises at least a portion of the first compensation structure and at least a portion of the second compensation structure; the second compensation capacitor includes at least a portion of the second compensation structure and at least a portion of the third compensation structure.

According to some exemplary embodiments, the first compensation capacitor comprises a first compensation sub-capacitor and a second compensation sub-capacitor, the first compensation sub-capacitor and the second compensation sub-capacitor being connected in parallel, the first compensation sub-capacitor comprising at least a portion of the first compensation structure and at least a portion of the second compensation structure; and/or the second compensation capacitor comprises a third compensation sub-capacitor and a fourth compensation sub-capacitor, the third compensation sub-capacitor and the fourth compensation sub-capacitor are connected in parallel, and the third compensation sub-capacitor comprises at least one part of the second compensation structure and at least one part of the third compensation structure.

According to some exemplary embodiments, the first scan signal line is in the first conductive layer, and the first compensation structure is electrically connected to the first scan signal line.

According to some exemplary embodiments, the display substrate further includes a first voltage line disposed on the substrate, for transmitting a first voltage; the second compensation structure is electrically connected to the first voltage line.

According to some exemplary embodiments, an orthographic projection of the first compensation structure on the substrate base plate at least partially overlaps with an orthographic projection of the second compensation structure on the substrate base plate.

According to some exemplary embodiments, the second scan signal line includes a first sub scan signal line in the second conductive layer and a second sub scan signal line in the third conductive layer; the third compensation structure is electrically connected with the second scanning signal line.

According to some exemplary embodiments, an orthographic projection of the third compensation structure on the substrate base plate at least partially overlaps with an orthographic projection of the second compensation structure on the substrate base plate.

According to some exemplary embodiments, the first compensation structure comprises a first body portion, the second compensation structure comprises a second body portion, and an orthographic projection of the second body portion on the substrate base plate covers an orthographic projection of the first body portion on the substrate base plate.

According to some exemplary embodiments, the third compensation structure comprises a third body portion, an orthographic projection of the second body portion on the substrate base plate covers an orthographic projection of the third body portion on the substrate base plate.

According to some exemplary embodiments, an area of an overlapping region of the first and second body portions is 70% or more of an area of an orthogonal projection of the second body portion on the substrate base plate; and/or the area of the overlapping region of the third main body part and the second main body part is more than 70% of the area of the orthographic projection of the second main body part on the substrate.

According to some exemplary embodiments, the first scanning signal line extends in a first direction, and a ratio of a size of an orthogonal projection of the first main body portion on the substrate base plate in a second direction to a size of an orthogonal projection of the first scanning signal line on the substrate base plate in the second direction is equal to or greater than 5; and/or the second scanning signal line extends along a first direction, and the ratio of the size of the orthographic projection of the third main body part on the substrate along a second direction to the size of the orthographic projection of the second scanning signal line on the substrate along the second direction is greater than or equal to 5.

According to some exemplary embodiments, the display substrate includes: the fourth conducting layer is positioned on one side, far away from the substrate, of the third conducting layer, and the fifth conducting layer is positioned on one side, far away from the substrate, of the fourth conducting layer; the first voltage line is located in the fifth conductive layer, the display substrate includes a compensation connection portion located in the fourth conductive layer, and the second compensation structure is electrically connected to the first voltage line through the compensation connection portion.

According to some exemplary embodiments, the display substrate further includes a fifth compensation structure in the fifth conductive layer, the fifth compensation structure being electrically connected to the first voltage line; and the fourth compensation sub-capacitor comprises at least a portion of the third compensation structure and at least a portion of the fifth compensation structure.

According to some exemplary embodiments, an orthographic projection of the third compensation structure on the base substrate at least partially overlaps with an orthographic projection of the fifth compensation structure on the base substrate.

According to some exemplary embodiments, the fifth compensation structure comprises a fifth main body portion, an orthographic projection of the third main body portion on the substrate base plate covers an orthographic projection of the fifth main body portion on the substrate base plate.

According to some exemplary embodiments, the display substrate further includes a sixth conductive layer on a side of the first semiconductor layer adjacent to the substrate; the display substrate further comprises a fourth compensation structure located in the sixth conductive layer, and an orthographic projection of the first compensation structure on the substrate is at least partially overlapped with an orthographic projection of the fourth compensation structure on the substrate.

According to some exemplary embodiments, the second compensation sub-capacitor comprises at least a portion of the first compensation structure and at least a portion of the fourth compensation structure.

According to some exemplary embodiments, the fourth compensation structure comprises a fourth body portion, an orthographic projection of the first body portion on the substrate base plate covers an orthographic projection of the fourth body portion on the substrate base plate.

According to some exemplary embodiments, a size of the fifth body part of the fifth compensation structure in the first direction is greater than a size of the first voltage line in the first direction.

According to some exemplary embodiments, a ratio of a size of the fifth main body portion of the fifth compensation structure in the first direction to a size of the first voltage line in the first direction is greater than or equal to 3.

According to some exemplary embodiments, in the 2 adjacent virtual sub-pixel structures, 2 of the fifth body portions are connected to each other, and an orthogonal projection of the 2 connected fifth body portions on the substrate has a rectangular shape.

According to some exemplary embodiments, for 2 sub-pixels adjacent in the first direction, orthographic projections of the pixel driving circuits thereof on the substrate are in axisymmetric relationship with respect to a first axis of symmetry extending along the second direction.

According to some exemplary embodiments, for 2 virtual sub-pixel structures adjacent in the first direction, orthographic projections of the 2 virtual sub-pixel structures on the substrate are in an axisymmetric relationship with respect to a second axis of symmetry, the second axis of symmetry extending along the second direction.

According to some exemplary embodiments, at least one of the first and second scanning signal lines includes a first compensation signal line and a second compensation signal line, the first compensation signal line electrically connecting the plurality of sub-pixels in one row of sub-pixels and the at least one first dummy sub-pixel structure, the second compensation signal line electrically connecting the plurality of sub-pixels in another row of sub-pixels and the at least one first dummy sub-pixel structure; and the number of sub-pixels to which the first compensation signal line is electrically connected is less than the number of sub-pixels to which the second compensation signal line is electrically connected, and the number of first dummy sub-pixel structures to which the first compensation signal line is electrically connected is greater than the number of first dummy sub-pixel structures to which the second compensation signal line is electrically connected.

According to some exemplary embodiments, the first scan signal line and the second scan signal line each extend in the first direction; and in the first virtual pixel area, the plurality of virtual sub-pixel structures are arranged along the first direction and the second direction, and the number of virtual sub-pixel structures in the same row is increased and then decreased along the second direction.

In another aspect, a display panel is provided, which includes the display substrate as described above.

In a further aspect, there is provided a display device comprising a display substrate as described above or a display panel as described above.

Drawings

The features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a schematic plan view of a display device according to some embodiments of the present disclosure;

fig. 2 is a schematic cross-sectional view of a display device according to some exemplary embodiments of the present disclosure, taken along line AA' in fig. 1;

FIG. 3 is a partial enlarged view of a display substrate at the aperture portion of FIG. 1, according to some exemplary embodiments of the present disclosure;

fig. 4 is a partial enlarged view of a display substrate at part I in fig. 3, according to some exemplary embodiments of the present disclosure;

fig. 5 is a partial enlarged view of a display substrate at part II in fig. 3 according to some exemplary embodiments of the present disclosure;

fig. 6 is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure;

fig. 7 is a plan view illustrating an exemplary implementation of a sub-pixel in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure;

fig. 8A and 8B are respectively equivalent circuit diagrams of a load compensation unit (i.e., a first dummy pixel structure) of a display substrate according to some exemplary embodiments of the present disclosure;

fig. 9 is a plan view illustrating an exemplary implementation of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure;

FIGS. 10-17 are plan views illustrating some of the film layers of an exemplary embodiment of the virtual sub-pixel structure of FIG. 9;

fig. 18 is a schematic view illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure, taken along a line BB' in fig. 7;

fig. 19 is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure;

fig. 20 is a plan view illustrating an exemplary implementation of a sub-pixel in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure;

fig. 21A and 21B are equivalent circuit diagrams of a load compensation unit (i.e., a first dummy pixel structure) of a display substrate according to some exemplary embodiments of the present disclosure, respectively;

fig. 22 is a plan view illustrating an exemplary implementation of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure;

fig. 23 to 32 are plan views illustrating some film layers of an exemplary embodiment of the virtual sub-pixel structure in fig. 22;

fig. 33 is a plan view illustrating an exemplary implementation of a sub-pixel in a display pixel area of a display substrate according to some exemplary embodiments of the present disclosure, in which plan views of two adjacent sub-pixels in the display pixel area are schematically illustrated;

fig. 34 is a plan view illustrating an exemplary implementation of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure, in which plan views of two adjacent virtual sub-pixel structures in a first virtual pixel region are schematically illustrated;

FIGS. 35-42 are plan views illustrating some film layers of an exemplary embodiment of two adjacent virtual sub-pixel structures of FIG. 34;

fig. 43 is a plan view illustrating an exemplary implementation of a sub-pixel in a display pixel area of a display substrate according to some exemplary embodiments of the present disclosure, wherein plan views of two adjacent sub-pixels in the display pixel area are schematically illustrated;

fig. 44 is a plan view illustrating an exemplary embodiment of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure, in which plan views of two adjacent virtual sub-pixel structures in a first virtual pixel region are schematically illustrated; and

fig. 45 to 54 are plan views illustrating some film layers of an exemplary embodiment of two adjacent dummy sub-pixel structures in fig. 44.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of the disclosure.

It should be noted that in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. As such, the sizes and relative sizes of the respective elements are not necessarily limited to those shown in the drawings. In the description and drawings, the same or similar reference numerals denote the same or similar parts.

When an element is referred to as being "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Other terms and/or expressions used to describe the relationship between elements should be interpreted in a similar manner, e.g., "between" and "directly between", "adjacent" and "directly adjacent" or "on. Further, the term "connected" may refer to physical, electrical, communication, and/or fluid connections. Further, the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one element, component, element, region, layer or section from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer, and/or a first portion discussed below could be termed a second component, a second member, a second element, a second region, a second layer, and/or a second portion without departing from the teachings of the present disclosure.

For convenience in description, spatial relationship terms, such as "upper," "lower," "left," "right," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

In this document, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. As used herein, "about" or "approximately" includes the stated values and indicates that the particular values determined by one of ordinary skill in the art are within acceptable deviation ranges, taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of the particular quantities (i.e., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated values.

In this specification, the expression "the same layer" refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film formation process and then patterning the film layer by a single patterning process using the same mask. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, a plurality of elements, components, structures and/or portions located in the same layer are made of the same material and formed by the same patterning process, and generally, the plurality of elements, components, structures and/or portions located in the same layer have substantially the same thickness.

It will be understood by those skilled in the art that, in the present context, unless otherwise specified, the expression "continuously extending", "integral structure" or similar expression means: a plurality of elements, features, structures and/or portions are located in the same layer and are typically formed during the fabrication process by the same patterning process, with no spaces or breaks between the elements, features, structures and/or portions, but rather continuously extending structures.

Embodiments of the present disclosure provide at least a display substrate, a display panel and a display device. The display substrate includes a display substrate including a display pixel region and a first dummy pixel region, the display substrate including: a base substrate; a plurality of sub-pixels disposed on the substrate and in the display pixel region, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, each sub-pixel including a pixel driving circuit including a driving transistor, a second transistor, and a fourth transistor, each of the driving transistor, the second transistor, and the fourth transistor including a gate electrode, a first electrode, and a second electrode, the second transistor being electrically connected between the gate electrode and one of the first electrode and the second electrode of the driving transistor, the fourth transistor being for controlling writing of a data signal; a plurality of dummy sub-pixel structures disposed on the substrate and in the first dummy pixel region, at least one of the dummy sub-pixel structures including a first compensation capacitor and a second compensation capacitor; and a first scanning signal line and a second scanning signal line provided on the substrate, the first scanning signal line for supplying a first scanning signal to a gate electrode of the fourth transistor, the second scanning signal line for supplying a second scanning signal to a gate electrode of the second transistor, the first scanning signal line and the second scanning signal line each extending through the display pixel region and the first dummy pixel region, wherein the first scanning signal line is electrically connected to a gate electrode of a fourth transistor of a pixel driving circuit of each sub-pixel in a row of sub-pixels, and the first scanning signal line is further electrically connected to the first compensation capacitor of the at least one dummy sub-pixel structure; and the second scan signal line is electrically connected to a gate of the second transistor of the pixel driving circuit of each of the sub-pixels in a row of the sub-pixels, and is also electrically connected to the second compensation capacitor of the at least one dummy sub-pixel structure. By arranging the compensation capacitor in the virtual pixel region, loads on different scanning signal lines can be uniform, display difference is avoided, and display quality is guaranteed.

Fig. 1 illustrates a plan view of a display device according to an exemplary embodiment of the present disclosure. For example, the display device includes a display substrate. The display substrate may be an electroluminescent display substrate, such as an OLED display substrate.

As shown in fig. 1, the display substrate includes a display area AA and at least one opening located in the display area AA. It should be noted that the "opening" described herein is a region on the display substrate for mounting a hardware structure, and for convenience of description, it is referred to as an opening herein, but the opening includes, but is not limited to, the following forms: through holes, grooves, openings, etc. Optionally, the hardware structure may include one or more of the following structures: a front camera, HOME keys, a receiver or a speaker. The specific installation manner of the hardware structure is not particularly limited in the embodiment of the present disclosure.

For example, the at least one aperture may comprise two apertures. For convenience of description, the two holes may be referred to as a first hole TH1 and a second hole TH2, respectively. The first holes TH1 may have a substantially circular shape, and the second holes TH2 may have a combination of rounded rectangles and semicircles. The first and second holes TH1 and TH2 are spaced apart from each other, and a solid portion is disposed in a spaced region SR between the first and second holes TH1 and TH2. For example, the display substrate may include a base substrate 1 and various film layers disposed on the base substrate 1. In the regions where the first and second holes TH1 and TH2 are located, at least the respective film layers on the base substrate 1 are not provided. In the spacing region SR, at least some of the respective film layers on the substrate base substrate 1 are disposed. The orthographic projection of the combination of the first opening hole TH1, the spacing region SR and the second opening hole TH2 on the substrate base plate 1 is in a racetrack shape.

It should be noted that fig. 1 illustrates two openings as an example, and it should be understood that the embodiments of the disclosure are not limited thereto, and in other embodiments, fewer (for example, one) or more openings may be provided. Furthermore, the shape of the opening may also be determined according to the shape of the hardware structure to be mounted, for example, the cross section of the opening in a direction parallel to the substrate base of the display substrate may have one or more of the following shapes: circular, oval, rectangular, rounded rectangular, square, diamond, trapezoidal, and the like.

In an embodiment of the present disclosure, a hardware structure such as a camera is mounted in the opening by providing the opening in the display area, i.e. an orthographic projection of the hardware structure such as a camera on the substrate base falls into the at least one opening. Therefore, the functions of shooting under the screen and the like can be realized, so that the screen occupation ratio can be improved, and the effect of a full screen is realized.

With continued reference to fig. 1, the display area AA may include a first display area AA1 and a second display area AA2. For example, the first display area AA1 and the second display area AA2 do not overlap each other. For example, the second display area AA2 at least partially surrounds (e.g., completely surrounds) the first display area AA1.

For example, the first display area AA1 may correspond to an area where the first and second holes TH1 and TH2 are located. For a display substrate with an under-screen camera, some sub-pixels may be disposed in the first display area AA1 to improve the display performance of the display substrate. In order to improve light transmittance of the display region of the display substrate corresponding to the under-screen camera, a distribution density per unit area (PPI) of the light emitting devices corresponding to the display region of the under-screen camera may be less than that of the light emitting devices of the other display regions of the display substrate. That is, the first display area AA1 is formed as a low pixel density region, and the second display area AA2 is formed as a high pixel density region. Of course, for a display substrate having an off-screen camera, no display pixel may be provided in the first display area AA1. The embodiments of the present disclosure do not specifically limit this.

Fig. 2 is a schematic cross-sectional view of a display device according to some exemplary embodiments of the present disclosure, taken along line AA' in fig. 1. As shown in fig. 2, the display substrate may include a substrate 1. The camera 2 may be disposed on the back side (shown as the lower side in fig. 2, for example, the side opposite to the light emitting direction in the display) of the first display area AA1 of the substrate base plate 1, and the first display area AA1 may satisfy the imaging requirement of the camera 2 on the light transmittance.

For example, the light transmittance of the first display area AA1 is greater than that of the second display area AA2. The camera 2 is, for example, an image camera or an infrared camera. The camera 2 is configured to receive light from a display side (an upper side in fig. 2, for example, a display light emitting direction, or a direction in which human eyes are located when displaying) of the display substrate, so as to perform operations such as image capturing, distance sensing, light intensity sensing, and the like, and the light is irradiated onto the camera through the first display area AA1, for example, so as to be sensed by the camera.

In addition, the display substrate may further include a driving circuit layer, a light emitting device layer, and an encapsulation layer disposed on the substrate 1. For example, fig. 2 schematically shows a driving circuit layer 3, a light emitting device layer 4, and an encapsulation layer 5. The driving circuit layer 3 includes a driving circuit structure, and the light emitting device layer 4 includes a light emitting device such as an OLED. The driving circuit structure controls the light emitting devices of the sub-pixels to emit light so as to realize a display function. The driving circuit structure includes a thin film transistor, a storage capacitor, and various signal lines. The various signal lines include a scanning signal line, a data signal line, a first voltage line, a second voltage line, and the like to supply various signals such as a scanning signal, a data signal, a power supply voltage, and the like to the pixel driving circuit in each sub-pixel.

Fig. 3 is a partially enlarged view of a display substrate at an aperture portion in fig. 1 according to some exemplary embodiments of the present disclosure. Fig. 4 is a partial enlarged view of a display substrate at part I in fig. 3 according to some exemplary embodiments of the present disclosure. Fig. 5 is a partial enlarged view of a display substrate at part II in fig. 3 according to some exemplary embodiments of the present disclosure.

With combined reference to fig. 1 to 5, the display substrate may include a display pixel region and a dummy pixel region.

Note that, in this document, the expression "display pixel region" means: in the region, a plurality of pixels capable of emitting light to display a screen are provided; the expression "virtual pixel region" means: in this region, there are provided some pixel structures which may be similar to those of a plurality of pixels in the "display pixel region", but which are not used for a light-emitting display screen.

Referring to fig. 3, the display pixel region may include a display pixel region DP1, and the display pixel region DP1 may be located in the second display area AA2. In the display pixel region DP1, a plurality of pixels PX may be disposed. A plurality of pixels PX may be arranged in an array in the first direction X and the second direction Y on the substrate base 1. For example, each of the plurality of pixels PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. For convenience of understanding, the first, second, and third subpixels PX1, PX2, and PX3 may be described as a red subpixel, a green subpixel, and a blue subpixel, respectively, but embodiments of the present disclosure are not limited thereto.

It should be understood that, in the embodiment of the present disclosure, each sub-pixel located in the display pixel region DP1 includes a pixel driving circuit and a light emitting device. For example, the light emitting device may be an OLED light emitting device including an anode, an organic light emitting layer, and a cathode, which are stacked. The pixel driving circuit may include a plurality of thin film transistors and at least one storage capacitor.

The virtual pixel region may include a first virtual pixel region DMP1, and the first virtual pixel region DMP1 may be located in the spacing region SR. In the first virtual pixel area DMP1, a plurality of first virtual pixel structures DMPX1 may be disposed. A plurality of first dummy pixel structures DMPX1 may be arranged in an array along the first direction X and the second direction Y on the substrate base plate 1. The plurality of first virtual pixel structures DMPX1 may include a plurality of virtual sub-pixel structures DMPX11, DMPX12, and DMPX13 corresponding to the plurality of sub-pixels located in the display pixel region DP 1. It should be noted that, in the embodiment of the present disclosure, the virtual sub-pixel structure does not emit light herein, and is respectively labeled as DMPX11, DMPX12, and DMPX13 herein, only for the requirement corresponding to the plurality of sub-pixels PX1, PX2, and DMPX 3, and the embodiment of the present disclosure is not limited thereto.

It should be noted that, although in the illustrated embodiment, the first direction X and the second direction Y are perpendicular to each other, embodiments of the present disclosure are not limited thereto.

While the embodiments of the present disclosure have been described above with respect to the implementation of the display device of the "perforated screen", it should be noted that the embodiments of the present disclosure are not limited to the display device of the "perforated screen", and the present disclosure may also include the implementation of the display device of the "camera under screen". That is, in an embodiment of the present disclosure, the display substrate may include the above-described display pixel region and a dummy pixel region, for example, the display pixel region DP1 and the first dummy pixel region DMP1. The display substrate may not include the above-mentioned opening. The first virtual pixel area DMP1 may correspond to an area where the off-screen camera is disposed.

Hereinafter, the structure of the pixel driving circuit of the sub-pixel located in the display pixel region DP1 will be described in detail by taking a 7T1C pixel driving circuit as an example, but the embodiments of the present disclosure are not limited to the 7T1C pixel driving circuit, and other known pixel driving circuit structures may be applied to the embodiments of the present disclosure without conflict.

Fig. 6 is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 7 is a plan view illustrating an exemplary implementation of a sub-pixel in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure.

Referring to fig. 6 and 7 in combination, the pixel driving circuit may include: a plurality of thin film transistors, and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

The display substrate may further include a plurality of signal lines, for example, the plurality of signal lines include: a first scanning signal line 61 and a second scanning signal line 61N for transmitting scanning signals, a first reset signal line 62 and a second reset signal line 62N for transmitting reset control signals, a light emission control line 63 for transmitting light emission control signals, a data signal line 64 for transmitting data signals, a first voltage line 65 for transmitting a first voltage, an initialization voltage line 66 for transmitting an initialization voltage, and a second voltage line 67 for transmitting a second voltage. For example, the first voltage may be a VDD voltage, the second voltage may be a VSS voltage, and the first voltage may be higher than the second voltage.

In the embodiment of the present disclosure, including the driving circuit (LTPO) composed of the low temperature polysilicon semiconductor transistor and the oxide semiconductor transistor, in which the active layers of the first transistor T1 and the second transistor T2 are formed using, for example, an oxide semiconductor material, it is possible to improve the voltage stability at the node N1 (shown in fig. 6) in the pixel driving circuit, thereby improving the display performance of the display panel. In addition, the first transistor T1 and the second transistor T2 both have a dual gate structure, so that stability of the first transistor T1 and the second transistor T2 and uniformity of a threshold voltage (Vth) are improved, and performance of the display panel can be further improved.

In the embodiment of the present disclosure, in order to distinguish the scan signals transferred to the second transistor T2 and the fourth transistor T4, a signal line for the scan signal transferred to the gate electrode of the second transistor T2 having the double gate structure is referred to as a second scan signal line 61N, and a signal line for the scan signal transferred to the gate electrode of the fourth transistor T4 is referred to as a first scan signal line 61. Similarly, in order to distinguish the scan signals transferred to the first transistor T1 and the seventh transistor T7, a signal line for transferring to the gate electrode of the first transistor T1 having the dual gate structure is referred to as a second reset signal line 62N, and a signal line for transferring to the gate electrode of the seventh transistor T7 is referred to as a first reset signal line 62.

Referring to fig. 6 and 7, the gate G1 of the first transistor T1 is electrically connected to the second reset signal line 62N, and the source S1 of the first transistor T1 is electrically connected to the initialization voltage line 66. And the drain D1 of the first transistor T1 is electrically connected to the end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3, as shown in fig. 6, the drain D1 of the first transistor T1, the end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 are electrically connected to the node N1. The first transistor T1 is turned on according to the reset control signal transmitted through the second reset signal line 62N to transmit the initialization voltage signal Vint to the gate G1 of the third transistor T3, thereby performing an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, the first transistor T1 is also referred to as an initialization transistor.

The gate G2 of the second transistor T2 is electrically connected to the second scan signal line 61N, the source S2 of the second transistor T2 is electrically connected to the node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1. The second transistor T2 is turned on according to the scan signal transmitted through the second scan signal line 61N to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, thereby performing diode connection of the third transistor T3.

A gate G3 of the third transistor T3 is electrically coupled to the node N1, a source S3 of the third transistor T3 is electrically coupled to the node N2, and a drain D3 of the third transistor T3 is electrically coupled to the node N3. The third transistor T3 receives a data signal according to a switching operation of the fourth transistor T4 to supply the driving current Id to the OLED. That is, the third transistor T3 is also referred to as a driving transistor.

The gate G4 of the fourth transistor T4 is electrically connected to the first scan signal line 61, the source S4 of the fourth transistor T4 is electrically connected to the data signal line 64, and the drain D4 of the fourth transistor T4 is electrically connected to the node N2, i.e., to the source S3 of the third transistor T3. The fourth transistor T4 is turned on according to the scan signal transmitted through the first scan signal line 61 to perform a switching operation to transmit the data signal to the source S3 of the third transistor T3.

The gate G5 of the fifth transistor T5 is electrically connected to the light emission control line 63, and the source S5 of the fifth transistor T5 is electrically connected to the first voltage line 65. And a drain D5 of the fifth transistor T5 is electrically connected to the node N2.

The gate G6 of the sixth transistor T6 is electrically connected to the light-emitting control line 63, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, i.e., to the anode of the light-emitting element OLED. The fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on according to the light emission control signal transmitted through the light emission control line 63 to transmit the first voltage to the OLED, thereby allowing the driving current Id to flow into the OLED.

The gate G7 of the seventh transistor T7 is electrically connected to the first reset signal line 62, the source S7 of the seventh transistor T7 is electrically connected to the node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line 66.

One end (hereinafter, referred to as a first capacitive electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1, and the other end (hereinafter, referred to as a second capacitive electrode) Cst2 is electrically connected to a first voltage line 65.

The anode of the OLED is electrically connected to the node N4, and the cathode is electrically connected to a second voltage line 67 to receive a second voltage VSS. Accordingly, the OLED receives the driving current Id from the third transistor T3 to emit light, thereby displaying an image.

Note that, in fig. 6, each of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 is a p-channel field effect transistor, but embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 may be n-channel field effect transistors.

In operation, in the initialization stage, a reset control signal having a low level is supplied through the second reset signal line 62N. Subsequently, the first transistor T1 is turned on based on the low level of the reset control signal, and the initialization voltage signal Vint from the initialization voltage line 66 is transferred to the gate G1 of the third transistor T3 through the first transistor T1. Accordingly, the third transistor T3 is initialized due to the initialization voltage signal Vint.

In the data programming phase, a scan signal having a low level is supplied through the first scan signal line 61 and the second scan signal line 61N. Subsequently, the fourth transistor T4 and the second transistor T2 are turned on based on the low level of the scan signal. Accordingly, the third transistor T3 is placed in a diode-connected state and biased in a positive direction through the turned-on second transistor T2.

Subsequently, a compensation voltage + Vth (e.g., vth is a negative value) obtained by subtracting the threshold voltage Vth of the third transistor T3 from the data signal supplied via the data signal line 64 is applied to the gate G3 of the third transistor T3. Subsequently, the first voltage VDD and the compensation voltage + Vth are applied to both terminals of the storage capacitor Cst, so that charges corresponding to a voltage difference between the respective terminals are stored in the storage capacitor Cst.

In the light-emitting phase, the light-emission control signal from the light-emission control line 63 changes from the high level to the low level. Subsequently, in the light emitting period, the fifth transistor T5 and the sixth transistor T6 are turned on based on the low level of the light emission control signal.

Subsequently, a driving current is generated based on a difference between the voltage of the gate G3 of the third transistor T3 and the first voltage VDD. The driving current Id corresponding to the difference between the driving current and the bypass current is supplied to the OLED through the sixth transistor T6.

In the light emitting stage, the gate-source voltage of the third transistor T3 is maintained at (+ Vth) -VDD due to the storage capacitor Cst based on the current-voltage relationship of the third transistor T3. Drive currents Id and (-VDD) ² And (4) in proportion. Therefore, the driving current Id may not be affected by the variation of the threshold voltage Vth of the third transistor T3.

Fig. 18 is a schematic view illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure, taken along a line BB' in fig. 7.

Referring to fig. 7 and 18 in combination, the display substrate includes a substrate base plate 10 and a plurality of film layers disposed on the substrate base plate 10. In some embodiments, the plurality of film layers includes at least a first semiconductor layer 20, a first conductive layer 30, a second conductive layer 40, a second semiconductor layer 50, a third conductive layer 60, a fourth conductive layer 70, and a fifth conductive layer 80. First semiconductor layer 20, first conductive layer 30, second conductive layer 40, second semiconductor layer 50, third conductive layer 60, fourth conductive layer 70, and fifth conductive layer 80 are disposed away from substrate base plate 10 in this order.

For example, the first semiconductor layer 20 may be formed of a semiconductor material such as low temperature polysilicon, and the film thickness thereof may be in the range of 400 to 800 angstroms, for example, 500 angstroms. The second semiconductor layer 50 may be formed of an oxide semiconductor material, for example, a polysilicon oxide semiconductor material such as IGZO, and the film thickness thereof may be in a range of 300 to 600 angstroms, for example, 400 angstroms. The first conductive layer 30, the second conductive layer 40 and the third conductive layer 60 may be formed of a conductive material forming a gate electrode of the thin film transistor, for example, the conductive material may be Mo, and a film thickness thereof may be in a range of 20000 to 3000 angstroms, for example, 2500 angstroms. The fourth conductive layer 70 and the fifth conductive layer 80 may be formed of a conductive material forming a source and a drain of the thin film transistor, for example, the conductive material may include Ti, al, etc., may have a stacked structure formed of Ti/Al/Ti, and a film thickness thereof may be in a range of 7000 to 9000 angstroms. For example, in the case where the fourth conductive layer 70 or the fifth conductive layer 80 has a stacked-layer structure formed of Ti/Al/Ti, the thickness of each layer of Ti/Al/Ti may be about 500 angstroms, 5500 angstroms, and 500 angstroms, respectively.

The display substrate includes a second scanning signal line 61N, a first scanning signal line 61, a second reset signal line 62N, a first reset signal line 62, a light emission control line 63, and an initialization voltage line 66 arranged in a row direction to apply a scanning signal, a reset control signal, a light emission control signal, and an initialization voltage signal Vint, respectively, to the subpixels. The display substrate may further include a data signal line 64 and a first voltage line 65 crossing the second scan signal line 61N, the first scan signal line 61, the second reset signal line 62N, the first reset signal line 62, the light emission control line 63, and the initialization voltage line 66 to apply the data signal and the driving voltage VDD to the subpixels, respectively.

In conjunction with the description above with respect to fig. 6, the pixel driving circuit of the display substrate may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, sixth and seventh transistors T6 and T7, and a storage capacitor Cst.

Referring to fig. 6 and 7 in combination, the first transistor T1 and the second transistor T2 may be formed along the second semiconductor layer as shown in fig. 7. The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed along the first semiconductor layer 20 as shown in fig. 7.

As shown in fig. 7, the first semiconductor layer 20 may have a bent or bent shape, and may include a third active layer 20c corresponding to the third transistor T3, a fourth active layer 20d corresponding to the fourth transistor T4, a fifth active layer 20e corresponding to the fifth transistor T5, a sixth active layer 20f corresponding to the sixth transistor T6, and a seventh active layer 20g corresponding to the seventh transistor T7.

For example, the first semiconductor layer 20 may include polysilicon, such as a low temperature polysilicon material. The active layer of each transistor may include a channel region, a source region, and a drain region. The channel region may be undoped or doped differently from the source and drain regions and thus have semiconductor characteristics. The source and drain regions are located at both sides of the channel region, respectively, and are doped with impurities and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

The third transistor T3 includes a third active layer 20c and a third gate electrode G3. The third active layer 20c may include a third source region, a third drain region, and a third channel region connecting the third source region and the third drain region. The third source region and the third drain region extend in opposite directions relative to the third channel region.

The fourth transistor T4 includes a fourth active layer 20d and a fourth gate electrode G4. The fourth active layer 20d may include a fourth source region, a fourth drain region, and a fourth channel region connecting the fourth source region and the fourth drain region. The fourth source region and the fourth drain region extend in opposite directions with respect to the fourth channel region.

The fifth transistor T5 includes a fifth active layer 20e and a fifth gate electrode G5. The fifth active layer 20e may include a fifth source region, a fifth drain region, and a fifth channel region connecting the fifth source region and the fifth drain region. The fifth source region and the fifth drain region extend in opposite directions with respect to the fifth channel region.

The sixth transistor T6 includes a sixth active layer 20f and a sixth gate electrode G6. The sixth active layer 20f may include a sixth source region, a sixth drain region, and a sixth channel region connecting the sixth source region and the sixth drain region. The sixth source region and the sixth drain region extend in opposite directions with respect to the sixth channel region.

The seventh transistor T7 includes a seventh active layer 20G and a seventh gate electrode G7. The seventh active layer 20g may include a seventh source region, a seventh drain region, and a seventh channel region connecting the seventh source region and the seventh drain region. The seventh source region and the seventh drain region extend in opposite two directions with respect to the seventh channel region.

As shown in fig. 7, the second semiconductor layer 50 includes a first active layer 20a corresponding to the first transistor T1 and a second active layer 20b corresponding to the second transistor T2. For example, the first active layer 20a of the first transistor T1 and the second active layer 20b of the second transistor T2 extend in the same direction as the data line, i.e., both extend in the up-down direction in the drawing.

For example, the second semiconductor layer 50 may include an oxide semiconductor material. The active layer of each transistor may include a channel region, a source region, and a drain region. The channel region may be undoped or doped to a different type than the source and drain regions and thus have semiconductor characteristics. The source and drain regions are located at both sides of the channel region, respectively, and are doped with impurities and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

The first active layer 20a of the first transistor T1 includes a first source region, a first drain region, and a first channel region connecting the first source region and the first drain region. The first source region and the first drain region extend in opposite directions relative to the first channel region.

The second active layer 20b of the second transistor T2 includes a second source region, a second drain region, and a second channel region connecting the second source region and the second drain region. The second source region and the second drain region extend in opposite directions relative to the second channel region.

With continued reference to fig. 7, the second scanning signal line 61N includes a first sub-scanning signal line 61N1 in the second conductive layer 40 and a second sub-scanning signal line 61N2 in the third conductive layer 60, respectively. A portion of the first sub-scanning signal line 61N1 overlapping the second active layer 20b forms a bottom gate of the second transistor T2, and a portion of the second sub-scanning signal line 61N2 overlapping the second active layer 20b forms a top gate of the second transistor T2. In this way, the second transistor T2 having a double gate structure can be formed. It should be understood that, in the embodiment of the present disclosure, the first sub-scanning signal line 61N1 located in the second conductive layer 40 and the second sub-scanning signal line 61N2 located in the third conductive layer 60 may be electrically connected, i.e., they are each supplied with the first scanning signal, thereby forming the second scanning signal line 61N. By such a parallel wiring manner, the stability of the transmission signal on the second scanning signal line 61N can be improved.

Similarly, the second reset signal line 62N includes a first sub-reset signal line 62N1 and a second sub-reset signal line 62N2 in the second conductive layer 40 and the third conductive layer 60, respectively. A portion of the first sub-reset signal line 62N1 overlapping the first active layer 20a forms a bottom gate of the first transistor T1, and a portion of the second sub-reset signal line 62N2 overlapping the first active layer 20a forms a top gate of the first transistor T1. In this way, the first transistor T1 having a dual gate structure may be formed. It should be understood that, in the embodiment of the present disclosure, the first sub-reset signal line 62N1 located in the second conductive layer 40 and the second sub-reset signal line 62N2 located in the third conductive layer 60 may be electrically connected, i.e., they are each supplied with the first reset signal, thereby forming the second reset signal line 62N. By such a parallel wiring manner, the stability of the transmission signal on the second reset signal line 62N can be improved.

In an embodiment of the present disclosure, the plurality of film layers may further include an insulating film layer between two adjacent film layers of the first semiconductor layer 20, the first conductive layer 30, the second conductive layer 40, the second semiconductor layer 50, the third conductive layer 60, the fourth conductive layer 70, and the fifth conductive layer 80. Next, other film layers (e.g., insulating film layers) of the display substrate according to an embodiment of the present disclosure will be described with reference to fig. 18.

In an exemplary embodiment, the display substrate may include a barrier layer BL1 disposed on a base substrate 10; and a first buffer layer BL2 disposed on the barrier layer BL1 on the side away from the base substrate 10.

For example, the barrier layer BL1 may be formed of silicon oxide, having a thickness of about 5500 angstroms. The first buffer layer BL2 may be formed of silicon nitride, having a thickness of about 1000 angstroms; alternatively, the first buffer layer BL2 may be formed of a stack of silicon nitride and silicon oxide. For example, the first buffer layer BL2 may include a first buffer sub-layer disposed on the barrier layer BL1 and a second buffer sub-layer disposed on a side of the first buffer sub-layer away from the substrate 10, where the first buffer sub-layer includes a silicon nitride material and the second buffer sub-layer includes a silicon oxide material.

The display substrate may include a first gate insulating layer GI1 disposed between the first semiconductor layer 20 and the first conductive layer 30. For example, the first gate insulating layer GI1 may be formed of silicon oxide.

The display substrate may include a first interlayer insulating layer ILD1 disposed between the first conductive layer 30 and the second conductive layer 40.

The display substrate may include a second gate insulating layer GI2 disposed between the second conductive layer 40 and the second semiconductor layer 50. For example, the second gate insulating layer GI2 may be formed of silicon oxide. In this way, the second gate insulating layer GI2 formed of silicon oxide may block hydrogen (H) from permeating into the oxide semiconductor transistors (i.e., T1, T2) to improve the performance of the oxide semiconductor transistors (i.e., T1, T2).

The display substrate may include a third gate insulating layer GI3 disposed between the second semiconductor layer 50 and the third conductive layer 60. For example, the third gate insulating layer GI3 may be formed of silicon oxide. In this way, the third gate insulating layer GI3 formed of silicon oxide may block hydrogen (H) from penetrating into the oxide semiconductor transistors (i.e., T1, T2) to improve performance of the oxide semiconductor transistors (i.e., T1, T2).

The display substrate may include an interlayer insulating layer ILD2 disposed between the third conductive layer 60 and the fourth conductive layer 70. For example, the interlayer insulating layer ILD2 may be formed of a single layer of silicon oxide, or may be formed of a stacked structure of silicon oxide and silicon nitride.

The display substrate may further include an insulating layer, such as a passivation layer PVX and a planarization layer PLN, disposed between the fourth conductive layer 70 and the fifth conductive layer 80.

Referring back to fig. 1 and 3, a plurality of sub-pixels are arranged in an array on a substrate base 1, that is, a plurality of rows of sub-pixels and a plurality of columns of sub-pixels are formed on the substrate base 1. In fig. 1, 2 rows of sub-pixels electrically connected to the scanning signal lines 61A, 61B, respectively, are schematically shown.

For a plurality of rows of sub-pixels, since at least one opening is formed on the substrate 1, the number of sub-pixels included in each row of sub-pixels is not uniform.

In the embodiment of the present disclosure, the sub-pixel row having the most sub-pixels in the display substrate, for example, the sub-pixel row electrically connected to the scan signal line 61A in fig. 1, may be referred to, the number of sub-pixels in the reference sub-pixel row may be used as a reference value, and the sub-pixel row having the sub-pixel row whose number is less than the reference value may be compensated, for example, the sub-pixel row connected to the scan signal line 61B in fig. 1.

It should be noted that the scanning signal lines 61A and 61B may be any one of the first scanning signal line 61 and the second scanning signal line 61N described above, for example, the scanning signal lines 61A and 61B may be both the first scanning signal line 61, or the scanning signal lines 61A and 61B may be both the second scanning signal line 61N.

For convenience of description, the scan signal line electrically connected to the compensation sub-pixel row may be referred to as a compensation scan signal line, and the scan signal line electrically connected to the reference sub-pixel row may be referred to as a reference scan signal line. It should be understood that the display substrate may include a plurality of rows of compensation sub-pixel rows and a plurality of rows of reference sub-pixel rows, and accordingly, the display substrate may include a plurality of reference scan signal lines and a plurality of compensation scan signal lines.

The number of sub-pixels electrically connected to the compensation scanning signal line is smaller than the number of sub-pixels electrically connected to the reference scanning signal line, so that the load on the compensation scanning signal line is smaller than the load on the reference scanning signal line. Therefore, it is necessary to perform load compensation on the compensation scanning signal line so that the load on the compensation scanning signal line is consistent with that on the reference scanning signal line, thereby avoiding display variation and ensuring display quality.

Note that the number of sub-pixels to which at least two of the compensation scanning signal lines are electrically connected may be different from each other, and thus, the loads on at least two of the compensation scanning signal lines may be different from each other. Therefore, different load compensation needs to be performed on each compensation scanning signal line, so that the loads on each compensation scanning signal line are consistent, thereby avoiding display differences and ensuring display quality.

It should be noted that the number of sub-pixels electrically connected to each compensation scanning signal line is related to the number of openings, the shape of the openings, the arrangement of the sub-pixels, and other factors.

In an embodiment of the present disclosure, a load compensation unit may be disposed in the first dummy pixel region DMP1, and the load compensation unit may be electrically connected to the compensation scanning signal line to compensate for a load on the compensation scanning signal line.

In the embodiment of the present disclosure, the smaller the number of subpixels in the compensation subpixel row, the smaller the load on the scan signal line to which the scan signal is supplied, the larger the load that needs to be compensated. Therefore, optionally, in the display substrate provided in the embodiment of the present disclosure, the larger the number of sub-pixels connected to the scanning signal line corresponding to the load compensation unit is, the smaller the compensation load value of the load compensation unit is. The scanning signal lines with different sub-pixel numbers are compensated by the load compensation units with different compensation load values, so that the loads on different scanning signal lines are uniform, the display difference is avoided, and the display quality is ensured.

For example, the number of subpixels included in the reference subpixel row is N, and the number of subpixels included in the compensation subpixel row is M. In compensating for the load on the scan signal line, a value of the load requiring compensation may be determined according to a difference (i.e., N-M) between the number of subpixels included in the compensation subpixel row to be compensated and the number of subpixels included in the reference subpixel row.

In the embodiment of the present disclosure, the smaller the number of sub-pixels to which the compensation scan signal line is electrically connected, the larger the load it needs to compensate, and accordingly, the larger the number of first virtual sub-pixel structures to which it is electrically connected. For example, the at least one scanning signal line (e.g., the compensation scanning signal line described above) may include a first scanning signal line electrically connecting the plurality of sub-pixels in one row of sub-pixels and the at least one first virtual sub-pixel structure and a second scanning signal line electrically connecting the plurality of sub-pixels in another row of sub-pixels and the at least one first virtual sub-pixel structure. The number of sub-pixels electrically connected by the first scanning signal line is less than the number of sub-pixels electrically connected by the second scanning signal line, and accordingly, the number of first virtual sub-pixel structures electrically connected by the first scanning signal line is greater than the number of first virtual sub-pixel structures electrically connected by the second scanning signal line.

Referring to fig. 1 and 3 in combination, the openings TH1, TH2 have a maximum size at the centers thereof, and accordingly, the number of sub-pixels missing from a row of sub-pixels extending along the centers of the openings TH1, TH2 is the largest, and the number of sub-pixels missing from a row of sub-pixels extending along the edges of the openings TH1, TH2 is relatively small. In this way, in the first dummy pixel area DMP1, the plurality of dummy sub-pixel structures DMPX1 are arranged in the first direction X and the second direction Y, and the number of dummy sub-pixel structures DMPX1 located in the same row increases and then decreases in the second direction Y, that is, the number of dummy sub-pixel structures in one row extending along the centers of the openings TH1 and TH2 is the largest, and the number of dummy sub-pixel structures located in the same row gradually decreases in a direction from the center of the opening toward the edge of the opening.

It should be noted that, in the present document, the expression "center" denotes the geometric center or centroid of the pattern.

In an embodiment of the present disclosure, the load compensation unit may be formed by designing the first virtual pixel structure DMPX1.

Fig. 8A and 8B are equivalent circuit diagrams of a load compensation unit (i.e., a first dummy pixel structure) of a display substrate according to some exemplary embodiments of the present disclosure, respectively. Fig. 9 is a plan view illustrating an exemplary implementation of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 10 to 17 are plan views illustrating some film layers of an exemplary embodiment of the virtual sub-pixel structure in fig. 9. For example, fig. 10 to 17 schematically show a first conductive layer, a second conductive layer, a combination of the first conductive layer and the second conductive layer, a third conductive layer, a combination of the first conductive layer, the second conductive layer, and the third conductive layer, a fourth conductive layer, a combination of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, and a fifth conductive layer located in the first dummy pixel region, respectively.

As described above, the plurality of first dummy pixel structures DMPX1 may include a plurality of dummy sub-pixel structures DMPX11, DMPX12, and DMPX13 corresponding to the plurality of sub-pixels located in the display pixel region DP 1. At least one of the plurality of virtual sub-pixel structures DMPX11, DMPX12, and DMPX13 may include a first compensation capacitor C1 and a second compensation capacitor C2.

In the embodiment of the present disclosure, at least one first scan signal line 61 is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels, and the at least one first scan signal line 61 is also electrically connected to the first compensation capacitor C1 of the at least one dummy sub-pixel structure. In this way, the first compensation capacitor C1 can compensate for the load on the first scanning signal line 61. At least one second scan signal line 61N is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels, and the at least one second scan signal line 61N is also electrically connected to the second compensation capacitor C2 of the at least one dummy sub-pixel structure. Thus, the second compensation capacitor C2 can compensate for the load on the second scan signal line 61N.

For example, the first scanning signal line 61 is located in the first conductive layer 30, and the second scanning signal line 61N is located at least in the second conductive layer 40, or the second scanning signal line 61N includes portions respectively located in the second conductive layer 40 and the third conductive layer 60.

In the embodiment of the disclosure, by designing the compensation capacitor in the dummy pixel region, the compensation capacitor is electrically connected to the scan signal line, in this way, the load on the first scan signal line and the second scan signal line can be compensated, so that the load on different scan signal lines is uniform, the display difference is avoided, and the display quality is ensured.

In the embodiment of the present disclosure, the capacitance values of the compensation capacitors C1 and C2 of the dummy sub-pixel structure are designed to be larger. Through the design, the load on the first scanning signal line and the second scanning signal line which belong to the compensation scanning signal line can be compensated, so that the load on different scanning signal lines is uniform, the display difference is avoided, and the display quality is ensured.

Referring to fig. 9 to 17 in combination, in the first dummy pixel region DMP1, the display substrate may include a first reset signal line 62, an emission control line 63, and a first compensation structure 100a in the first conductive layer 30. That is, the first compensation structure 100a is located in the first conductive layer 30.

The first compensation structure 100a includes a first body portion 110a, a first compensation structure protrusion 111a, and a second compensation structure protrusion 112a. The orthographic projection of the first body portion 110a on the substrate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The first and second compensation structure protrusions 111a and 112a are located at opposite sides of the first body portion 110a, respectively. The first and second compensation structure protrusions 111a and 112a protrude in opposite directions with respect to the first body portion 110a, for example, the first compensation structure protrusion 111a extends leftward with respect to the first body portion 110a in the first direction X, and the second compensation structure protrusion 112a extends rightward with respect to the first body portion 110a in the first direction X.

A first dimension H1a of an orthographic projection of the first main body portion 110a on the substrate base along the second direction Y is greater than a second dimension H2a of an orthographic projection of the first compensation structure protrusion 111a on the substrate base along the second direction Y, and the first dimension H1a of the orthographic projection of the first main body portion 110a on the substrate base along the second direction Y is greater than a third dimension H3a of an orthographic projection of the second compensation structure protrusion 112a on the substrate base along the second direction Y. For example, a second dimension H2a of the orthographic projection of the first compensation structure protrusion 111a on the substrate along the second direction Y is substantially equal to a third dimension H3a of the orthographic projection of the second compensation structure protrusion 112a on the substrate along the second direction Y, or a ratio of the second dimension H2a to the third dimension H3a is between 0.8 and 1.2. A first dimension H1a of the orthographic projection of the first main body portion 110a on the substrate base along the second direction Y is much larger than a second dimension H2a of the orthographic projection of the first compensation structure protrusion 111a on the substrate base along the second direction Y, for example, a ratio of the first dimension H1a to the second dimension H2a or the third dimension H3a is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

In the first dummy pixel region DMP1, the display substrate may include a first reset signal line 62 and an emission control line 63 in the first conductive layer 30. Herein, the first reset signal line 62 and the light emission control line 63 are described using the same expressions and reference numerals, indicating that the first reset signal line 62 and the light emission control line 63 respectively extend from the display pixel region DP1 to the first dummy pixel region DMP1.

In the embodiment of the present disclosure, the first compensation structure 100a located in the first dummy pixel region DMP1 is electrically connected to the first scan signal line 61 located in the display pixel region DP 1. For example, the first scan signal line 61 positioned in the display pixel region DP1 extends from the display pixel region DP1 to the first dummy pixel region DMP1. A portion of the first scan signal line 61 in the first dummy pixel region DMP1 has a width wider than a width of a portion of the first scan signal line 61 in the display pixel region DP1, that is, the first body portion 110a is formed. The width of the other portion of the first scanning signal line 61 (i.e., the first compensation structure protrusion 111a and the second compensation structure protrusion 112 a) in the first virtual pixel region DMP1 is substantially equal to the width of the portion of the first scanning signal line 61 in the display pixel region DP1, or the ratio of the two is between 0.8 and 1.2.

Referring to fig. 11, in the first dummy pixel region DMP1, the display substrate may include a second compensation structure 200a in the second conductive layer 40. That is, the second compensation structure 200a is located in the second conductive layer 40. The second compensation structure 200a includes a second body portion 210a and a second compensation structure connection portion 211a. The orthogonal projection of the second body portion 210a on the substrate base plate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The second compensation structure connection part 211a protrudes in one direction with respect to the second body part 210a, for example, the second compensation structure connection part 211a protrudes upward with respect to the second body part 210a.

With combined reference to fig. 10 to 12, orthographic projections of the first and second compensation structures 100a and 200a on the substrate base plate at least partially overlap. For example, an orthographic projection of the first body portion 110a on the substrate may at least partially overlap an orthographic projection of the second body portion 210a on the substrate. In the embodiment of the present disclosure, the overlapping area of the first body portion 110a and the second body portion 210a is designed to be relatively large. For example, the orthographic projection of the second body portion 210a on the substrate substantially covers the orthographic projection of the first body portion 110a on the substrate. In fig. 12, a dotted line frame 130a schematically shows an overlapping region of the first and second body portions 110a and 210a. For example, the area of the overlapping region 130a of the first main body portion 110a and the second main body portion 210a is substantially equal to the area of the orthographic projection of the first main body portion 110a on the substrate. Alternatively, the ratio of the area of the overlapping region 130a to the area of the orthographic projection of the first body portion 110a on the substrate is between 0.8 and 1.2. The ratio of the area of the overlap region 130a to the area of the orthogonal projection of the second body portion 210a on the substrate board is between 0.7 and 1, that is, most (for example, 70% or more) of the second body portion 210a overlaps the first body portion 110a.

For example, the orthographic projection of the first body portion 110a on the substrate base has a dimension W1a along the first direction X and a dimension H1a along the second direction Y, and the orthographic projection of the second body portion 210a on the substrate base has a dimension W7a along the first direction X and a dimension H7a along the second direction Y. Dimension W1a may be less than dimension W7a and dimension H1a may be less than dimension H7a. For example, the ratio of dimension W1a to dimension W7a may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of dimension H1a to dimension H7a may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

Referring to fig. 13 and 14, in the first dummy pixel region DMP1, the display substrate may include a third compensation structure 300a in the third conductive layer 60. That is, the third compensation structure 300a is located in the third conductive layer 60.

The third compensation structure 300a includes a third body portion 310a, a third compensation structure protrusion 311a, and a fourth compensation structure protrusion 312a. An orthogonal projection of the third body portion 310a on the substrate board has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The third and fourth compensating structural protrusions 311a and 312a are located on opposite sides of the third body portion 310a, respectively. The third and fourth compensation structure protrusions 311a and 312a protrude in opposite directions with respect to the third body portion 310a, for example, the third compensation structure protrusion 311a extends leftward with respect to the third body portion 310a in the first direction X, and the fourth compensation structure protrusion 312a extends rightward with respect to the third body portion 310a in the first direction X.

A first dimension H4a of an orthographic projection of the third main body portion 310a on the substrate base along the second direction Y is greater than a second dimension H5a of an orthographic projection of the third compensation structure protrusion 311a on the substrate base along the second direction Y, and a first dimension H4a of an orthographic projection of the third main body portion 310a on the substrate base along the second direction Y is greater than a third dimension H6a of an orthographic projection of the fourth compensation structure protrusion 312a on the substrate base along the second direction Y. For example, the second dimension H5a of the orthographic projection of the third compensation structure protrusion 311a on the substrate along the second direction Y is substantially equal to the third dimension H6a of the orthographic projection of the fourth compensation structure protrusion 312a on the substrate along the second direction Y, or the ratio of the second dimension H5a to the third dimension H6a is between 0.8 and 1.2. A first dimension H4a of the orthographic projection of the third main body portion 310a on the substrate along the second direction Y is greater than a second dimension H5a of the orthographic projection of the third compensation structure protrusion 311a on the substrate along the second direction Y, for example, a ratio of the first dimension H4a to the second dimension H5a or the third dimension H6a is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

In the embodiment of the present disclosure, the third compensation structure 300a located in the first dummy pixel region DMP1 is electrically connected to the second scan signal line 61N located in the display pixel region DP 1. For example, the second scan signal line 61N located in the display pixel region DP1 extends from the display pixel region DP1 to the first dummy pixel region DMP1. A portion of the second scanning signal line 61N in the first dummy pixel region DMP1 has a width wider than that of a portion of the second scanning signal line 61N in the display pixel region DP1, i.e., the third body portion 310a is formed. The width of the other portion of the second scanning signal line 61N in the first virtual pixel region DMP1 (i.e., the third compensation structure protrusion 311a and the fourth compensation structure protrusion 312 a) is substantially equal to the width of the portion of the second scanning signal line 61N in the display pixel region DP1, or the ratio of the two is between 0.8 and 1.2.

With combined reference to fig. 13 to 14, orthographic projections of the second compensation structure 200a and the third compensation structure 300a on the substrate base plate at least partially overlap. For example, the orthographic projection of the second body portion 210a on the substrate at least partially overlaps with the orthographic projection of the third body portion 310a on the substrate. In the embodiment of the present disclosure, the overlapping area of the second body portion 210a and the third body portion 310a is designed to be relatively large. For example, the orthographic projection of the second body portion 210a on the substrate substantially covers the orthographic projection of the third body portion 310a on the substrate. In fig. 14, a dotted line frame 150a schematically shows an overlapping region of the third body portion 310a and the second body portion 210a. For example, the area of the overlapping region 150a of the third main body portion 310a and the second main body portion 210a is substantially equal to the area of the orthographic projection of the third main body portion 310a on the substrate. Alternatively, the ratio of the area of the overlapping region 150a to the area of the orthographic projection of the third body portion 310a on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 150a to the area of the orthogonal projection of the second body portion 210a on the substrate board is between 0.7 and 1, that is, most (for example, 70% or more) of the second body portion 210a overlaps the third body portion 310a.

For example, the orthographic projection of the third body portion 310a on the substrate base has a dimension W4a along the first direction X and a dimension H4a along the second direction Y. Dimension W4a may be less than dimension W7a and dimension H1a may be less than dimension H4a. For example, the ratio of dimension W4a to dimension W7a may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of dimension H4a to dimension H7a may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

Referring to fig. 15 to 17, in the first dummy pixel region DMP1, the display substrate may further include an initialization voltage line 66 and a compensation connection part 160a in the fourth conductive layer 70. Herein, the initialization voltage line 66 is described using the same expression and reference numeral, indicating that the initialization voltage line 66 extends from the display pixel region DP1 to the first dummy pixel region DMP1. In the first dummy pixel region DMP1, the display substrate may further include a data signal line 64 and a first voltage line 65 in the fifth conductive layer 80. Herein, the data signal line 64 and the first voltage line 65 are described using the same expressions and reference numerals, which indicate that the data signal line 64 and the first voltage line 65 extend from the display pixel region DP1 to the first dummy pixel region DMP1, respectively.

With combined reference to fig. 9, 15 to 17, one end of the compensation connection part 160a is electrically connected to the second compensation structure 200a through the via 1601a, and the other end is electrically connected to the first voltage line 65 through the via 1602 a. For example, the via hole 1601a exposes a portion of the second compensation structure connection portion 211a, and the compensation connection portion 160a located in the fourth conductive layer 70 is electrically connected to the second compensation structure connection portion 211a located in the second conductive layer 40 through the via hole 1601 a. The via 1602a exposes a portion of the compensation connection part 160a, and the first voltage line 65 in the fifth conductive layer 80 is electrically connected to the compensation connection part 160a in the fourth conductive layer 70 through the via 1602 a. The second compensation structure 200a may be electrically connected to the first voltage line 65 through the compensation connection part 160a. In this way, the first voltage (e.g., the VDD voltage) may be transferred to the second compensation structure 200a.

In the embodiment of the present disclosure, the first compensation structure 100a located in the first conductive layer 30 is electrically connected to the first scan signal line 61, i.e., the first compensation structure 100a is supplied with the second scan signal. The second compensation structure 200a located in the second conductive layer 40 is electrically connected to the first voltage line 65, i.e., the second compensation structure 200a is supplied with the first voltage. Moreover, the first compensation structure 100a and the second compensation structure 200a have a larger overlapping area. In this way, a first compensation capacitor C1 may be formed between the first compensation structure 100a and the second compensation structure 200a, as shown in fig. 8A, which schematically illustrates the first compensation capacitor C1. That is, one plate of the first compensation capacitor C1 is the first compensation structure 100a, in particular, the first main body portion 110a of the first compensation structure 100 a; the other plate is the second compensation structure 200a, in particular the second body portion 210a of the second compensation structure 200a.

The capacitance value of the first compensation capacitor C1 is related to the overlapping area between the first compensation structure 100a and the second compensation structure 200a. As described above, the overlapping area between the first compensation structure 100a and the second compensation structure 200a is designed to be large, and accordingly, the capacitance value of the first compensation capacitor C1 is also large. The first compensation capacitor C1 is a load applied to the first scanning signal line 61. Since the capacitance value of the first compensation capacitor C1 is large, the load applied to the first scanning signal line 61 is also large, thereby achieving the purpose of compensating the load on the second scanning signal line.

In the embodiment of the present disclosure, the third compensation structure 300a located in the third conductive layer 60 is electrically connected to the second scan signal line 61N, i.e., the third compensation structure 300a is supplied with the second scan signal. The second compensation structure 200a located in the second conductive layer 40 is electrically connected to the first voltage line 65, i.e., the second compensation structure 200a is supplied with the first voltage. Moreover, the third compensation structure 300a and the second compensation structure 200a have a larger overlapping area. In this way, a second compensation capacitor C2 may be formed between the third compensation structure 300a and the second compensation structure 200a, as shown in fig. 8B, which schematically illustrates the second compensation capacitor C2. That is, one plate of the second compensation capacitor C2 is the third compensation structure 300a, in particular, the third body portion 310a of the third compensation structure 300 a; the other plate is the second compensation structure 200a, in particular the second body portion 210a of the second compensation structure 200a.

The capacitance value of the second compensation capacitor C2 is related to the overlapping area between the third compensation structure 300a and the second compensation structure 200a. As described above, the overlapping area between the third compensation structure 300a and the second compensation structure 200a is designed to be large, and accordingly, the capacitance value of the second compensation capacitor C2 is also large. The second compensation capacitor C2 is a load applied to the second scanning signal line 61N. Since the capacitance value of the second compensation capacitor C2 is large, the load applied to the second scanning signal line 61N is also large, thereby achieving the purpose of compensating for the load on the first scanning signal line.

In the embodiment of the present disclosure, for the first scanning signal line 61 extending through the region (including the first dummy pixel region DMP 1) where the display pixel region DP1 and the openings TH1 and TH2 are located, the number of electrically connected display sub-pixels thereof is smaller than the number of electrically connected display sub-pixels of the reference scanning signal line, resulting in a smaller load on such first scanning signal line 61 (i.e., the above-described compensation scanning signal line) than on the reference scanning signal line. For such a first scanning signal line 61, in the first display pixel region DP1, the first scanning signal line 61 located in the first conductive layer 30 and the components located in the second conductive layer 40 and the third conductive layer 60 are arranged at intervals (i.e., do not overlap); in the first dummy pixel region DMP1, as described above, the first compensation capacitor C1 is formed, and the capacitance value of the first compensation capacitor C1 is large. Thus, the first compensation capacitor C1 can compensate for the load on such first scanning signal lines 61 (i.e., the compensation scanning signal lines described above), so that the load on each first scanning signal line 61 is uniform, which is advantageous for improving the display performance.

In the embodiment of the present disclosure, for the second scanning signal line 61N extending through the display pixel region DP1 and the region (including the first dummy pixel region DMP 1) where the openings TH1 and TH2 are located, the number of electrically connected display sub-pixels thereof is smaller than the number of electrically connected display sub-pixels of the reference scanning signal line, resulting in a smaller load on such second scanning signal line 61N (i.e., the compensation scanning signal line described above) than on the reference scanning signal line. With such a second scanning signal line 61N, in the first display pixel region DP1, although the first sub-scanning signal line 61N1 and the second sub-scanning signal line 61N2 are partially overlapped, both the first sub-scanning signal line 61N1 and the second sub-scanning signal line 61N2 are supplied with the first scanning signal, that is, parasitic capacitance is hardly formed between the first sub-scanning signal line 61N1 and the second sub-scanning signal line 61N 2; in the first dummy pixel region DMP1, as described above, the second compensation capacitor C2 is formed, and the capacitance value of the second compensation capacitor C2 is large. Thus, the second compensation capacitor C2 can compensate the load on such second scanning signal lines 61N (i.e., the compensation scanning signal lines described above), so that the load on each second scanning signal line 61N is uniform, which is beneficial to improving the display performance.

Fig. 19 is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 20 is a plan view illustrating an exemplary implementation of a sub-pixel in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure. It should be noted that the following description focuses on differences between the embodiments shown in fig. 19 and 20 with respect to the above-mentioned embodiments, and the same points between them can be referred to the above description, and are not repeated herein. That is, in this document, the various embodiments or implementations may be combined with each other without conflict.

Referring to fig. 19 and 20 in combination, the pixel driving circuit may include: a plurality of thin film transistors, and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

The display substrate may further include a plurality of signal lines, for example, the plurality of signal lines including: a first scanning signal line 61 and a second scanning signal line 61N for transmitting scanning signals, a second reset signal line 62N for transmitting a reset control signal, a light emission control line 63 for transmitting a light emission control signal, a data signal line 64 for transmitting a data signal, a first voltage line 65 for transmitting a first voltage, a first initializing voltage line 66 and a second initializing voltage line 68 for transmitting an initializing voltage, and a second voltage line 67 for transmitting a second voltage. For example, the first voltage may be a VDD voltage, the second voltage may be a VSS voltage, and the first voltage may be higher than the second voltage.

With continued reference to fig. 19 and 20, the gate G1 of the first transistor T1 is electrically connected to the second reset signal line 62N, and the source S1 of the first transistor T1 is electrically connected to the first initialization voltage line 66. And the drain D1 of the first transistor T1 is electrically connected to the end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3, as shown in fig. 19, the drain D1 of the first transistor T1, the end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 are electrically connected to the node N1. The first transistor T1 is turned on according to the reset control signal transmitted through the second reset signal line 62N to transmit the first initialization voltage signal Vint1 to the gate G1 of the third transistor T3, thereby performing an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, the first transistor T1 is also referred to as an initialization transistor.

The gate G2 of the second transistor T2 is electrically connected to the second scan signal line 61N, the source S2 of the second transistor T2 is electrically connected to the node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1. The second transistor T2 is turned on according to the scan signal transmitted through the second scan signal line 61N to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, thereby performing diode connection of the third transistor T3.

A gate G3 of the third transistor T3 is electrically coupled to the node N1, a source S3 of the third transistor T3 is electrically coupled to the node N2, and a drain D3 of the third transistor T3 is electrically coupled to the node N3. The third transistor T3 receives a data signal according to a switching operation of the fourth transistor T4 to supply the driving current Id to the OLED. That is, the third transistor T3 is also referred to as a driving transistor.

The gate G4 of the fourth transistor T4 is electrically connected to the first scan signal line 61, the source S4 of the fourth transistor T4 is electrically connected to the data signal line 64, and the drain D4 of the fourth transistor T4 is electrically connected to the node N2, i.e., to the source S3 of the third transistor T3. The fourth transistor T4 is turned on according to the scan signal transmitted through the first scan signal line 61 to perform a switching operation to transmit the data signal to the source S3 of the third transistor T3.

The gate G5 of the fifth transistor T5 is electrically connected to the light emitting control line 63, and the source S5 of the fifth transistor T5 is electrically connected to the first voltage line 65. And a drain D5 of the fifth transistor T5 is electrically connected to the node N2.

The gate G6 of the sixth transistor T6 is electrically connected to the light emission control line 63, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, i.e., the anode of the light emitting element OLED. The fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on according to the light emission control signal transmitted through the light emission control line 63 to transmit the first voltage to the OLED, thereby allowing the driving current Id to flow into the OLED.

The gate G7 of the seventh transistor T7 is electrically connected to the first scan signal line 61, the source S7 of the seventh transistor T7 is electrically connected to the node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the second initialization voltage line 68.

One end (hereinafter, referred to as a first capacitive electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1, and the other end (hereinafter, referred to as a second capacitive electrode) Cst2 is electrically connected to a first voltage line 65.

The anode of the OLED is electrically connected to the node N4, and the cathode is electrically connected to a second voltage line 67 to receive a second voltage VSS. Accordingly, the OLED receives the driving current Id from the third transistor T3 to emit light, thereby displaying an image.

That is, in this embodiment, 2 initializing voltage lines 66, 68 are provided, the first initializing voltage line 66 transfers the first initializing voltage signal Vint1 to the first transistor T1, and the second initializing voltage line 68 transfers the second initializing voltage signal Vint2 to the seventh transistor T7. In this way, the initialization voltage signals transmitted to the first transistor T1 and the seventh transistor T7 may be separately adjusted, thereby contributing to an improvement in display performance of the display panel.

Fig. 21A and 21B are equivalent circuit diagrams of a load compensation unit (i.e., a first dummy pixel structure) of a display substrate according to some exemplary embodiments of the present disclosure, respectively. Fig. 22 is a plan view illustrating an exemplary implementation of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 23 to 32 are plan views illustrating some film layers of an exemplary embodiment of the virtual sub-pixel structure in fig. 22. For example, fig. 23 to 32 schematically show a sixth conductive layer, a first conductive layer, a combination of the sixth conductive layer and the first conductive layer, a second conductive layer, a combination of the sixth conductive layer, the first conductive layer and the second conductive layer, a third conductive layer, a combination of the sixth conductive layer, the first conductive layer, the second conductive layer and the third conductive layer, a fourth conductive layer, a combination of the sixth conductive layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer, and a fifth conductive layer located in the first dummy pixel region, respectively.

As described above, the plurality of first dummy pixel structures DMPX1 may include a plurality of dummy sub-pixel structures DMPX11, DMPX12, and DMPX13 corresponding to the plurality of sub-pixels located in the display pixel region DP 1. At least one of the plurality of dummy sub-pixel structures DMPX11, DMPX12, and DMPX13 may include a first compensation capacitor C1 and a second compensation capacitor C2.

In the embodiment of the present disclosure, at least one first scan signal line 61 is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels, and the at least one first scan signal line 61 is also electrically connected to the first compensation capacitor C1 of the at least one dummy sub-pixel structure. In this way, the first compensation capacitor C1 can compensate for the load on the first scanning signal line 61. At least one second scan signal line 61N is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels, and the at least one second scan signal line 61N is also electrically connected to the second compensation capacitor C2 of the at least one dummy sub-pixel structure. Thus, the second compensation capacitor C2 can compensate for the load on the second scanning signal line 61N.

For example, the first scanning signal line 61 is located in the first conductive layer 30, and the second scanning signal line 61N is located at least in the second conductive layer 40, or the second scanning signal line 61N includes portions respectively located in the second conductive layer 40 and the third conductive layer 60.

In the embodiment of the disclosure, by designing the compensation capacitor in the dummy pixel region, the compensation capacitor is electrically connected to the scan signal line, in this way, the load on the first scan signal line and the load on the second scan signal line can be compensated, so that the loads on different scan signal lines are uniform, the display difference is avoided, and the display quality is ensured.

In the embodiment of the present disclosure, the capacitance values of the compensation capacitors C1 and C2 of the dummy sub-pixel structure are designed to be larger. Through the design, the load on the first scanning signal line and the second scanning signal line which belong to the compensation scanning signal line can be compensated, so that the load on different scanning signal lines is uniform, the display difference is avoided, and the display quality is ensured.

Referring collectively to fig. 19-32, the display substrate includes a plurality of film layers disposed on the base substrate. In some embodiments, the plurality of film layers includes at least sixth conductive layer 90, first semiconductor layer 20, first conductive layer 30, second conductive layer 40, second semiconductor layer 50, third conductive layer 60, fourth conductive layer 70, and fifth conductive layer 80. Sixth conductive layer 90, first semiconductor layer 20, first conductive layer 30, second conductive layer 40, second semiconductor layer 50, third conductive layer 60, fourth conductive layer 70, and fifth conductive layer 80 are disposed away from base substrate 10 in this order.

In the first dummy pixel region DMP1, the display substrate may include a fourth compensation structure 400b in the sixth conductive layer 90. For example, the sixth conductive layer 90 may be a light-shielding layer, i.e., the fourth compensation structure 400b is located in the light-shielding layer.

The fourth compensation structure 400b may include a fourth body portion 410b, and an orthographic projection of the fourth body portion 410b on the substrate base plate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like.

It should be understood that the sixth conductive layer 90 may also include other structures or portions for shielding the semiconductor layer.

The display substrate may include an emission control line 63 and a first compensation structure 100b in the first conductive layer 30. That is, the first compensation structure 100b is located in the first conductive layer 30.

The first compensation structure 100b includes a first body portion 110b, a first compensation structure protrusion 111b, and a second compensation structure protrusion 112b. The orthographic projection of the first body portion 110b on the substrate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The first and second compensating structure protrusions 111b and 112b are located at opposite sides of the first body portion 110b, respectively. The first and second compensation structure protrusions 111b and 112b protrude in opposite directions with respect to the first body portion 110b, for example, the first compensation structure protrusion 111b extends leftward with respect to the first body portion 110b in the first direction X, and the second compensation structure protrusion 112b extends rightward with respect to the first body portion 110b in the first direction X.

A first dimension H1b of an orthographic projection of the first main body portion 110b on the substrate base along the second direction Y is greater than a second dimension H2b of an orthographic projection of the first compensation structure protrusion 111b on the substrate base along the second direction Y, and the first dimension H1b of the orthographic projection of the first main body portion 110b on the substrate base along the second direction Y is greater than a third dimension H3b of an orthographic projection of the second compensation structure protrusion 112b on the substrate base along the second direction Y. For example, a second dimension H2b of the orthographic projection of the first compensation structure protrusion 111b on the substrate base along the second direction Y is substantially equal to a third dimension H3b of the orthographic projection of the second compensation structure protrusion 112b on the substrate base along the second direction Y, or a ratio of the second dimension H2b to the third dimension H3b is between 0.8 and 1.2. A first dimension H1b of an orthographic projection of the first main body portion 110b on the substrate base along the second direction Y is much larger than a second dimension H2b of an orthographic projection of the first compensation structure protrusion 111b on the substrate base along the second direction Y, for example, a ratio of the first dimension H1b to the second dimension H2b or the third dimension H3b is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

In the embodiment of the present disclosure, the first compensation structure 100b located in the first dummy pixel region DMP1 is electrically connected to the first scan signal line 61 located in the display pixel region DP 1. For example, the first scan signal line 61 positioned in the display pixel region DP1 extends from the display pixel region DP1 to the first dummy pixel region DMP1. A portion of the first scan signal line 61 in the first dummy pixel region DMP1 has a width wider than that of a portion of the first scan signal line 61 in the display pixel region DP1, i.e., the first main body portion 110b is formed. The width of the other portion of the first scanning signal line 61 (i.e., the first and second compensating structure protrusions 111b and 112 b) located in the first virtual pixel region DMP1 is substantially equal to the width of the portion of the first scanning signal line 61 located in the display pixel region DP1, or the ratio of the two is between 0.8 and 1.2.

The orthographic projections of the first compensation structure 100b and the fourth compensation structure 400b on the substrate base plate at least partially overlap. For example, an orthographic projection of the first body portion 110b on the substrate is at least partially overlapped with an orthographic projection of the fourth body portion 410b on the substrate. In the embodiment of the present disclosure, the overlapping area of the first body portion 110b and the fourth body portion 410b is designed to be relatively large. For example, the orthographic projection of the first body portion 110b on the substrate substantially covers the orthographic projection of the fourth body portion 410b on the substrate. In fig. 25, a dotted line frame 120b schematically shows an overlapping area of the first and fourth body portions 110b and 410 b. For example, the area of the overlapping region 120b of the first and fourth body portions 110b and 410b is substantially equal to the area of the orthographic projection of the fourth body portion 410b on the substrate base. Alternatively, the ratio of the area of the overlapping region 120b to the area of the orthogonal projection of the fourth body portion 410b on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 120b to the area of the orthographic projection of the first body portion 110b on the substrate is between 0.3 and 1, or between 0.35 and 0.8, or between 0.4 and 0.6.

In the first dummy pixel region DMP1, the display substrate may include a second compensation structure 200b in the second conductive layer 40, a first initialization voltage line 66, and a first sub-reset signal line 62N1. That is, the second compensation structure 200b is located in the second conductive layer 40. The second compensation structure 200b includes a second body portion 210b. The orthographic projection of the second body portion 210b on the substrate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like.

The orthographic projections of the first compensation structure 100b and the second compensation structure 200b on the substrate base plate at least partially overlap. For example, an orthographic projection of the first body portion 110b on the substrate may at least partially overlap an orthographic projection of the second body portion 210b on the substrate. In the embodiment of the present disclosure, the overlapping area of the first body portion 110b and the second body portion 210b is designed to be relatively large. For example, the orthographic projection of the second body portion 210b on the substrate substantially covers the orthographic projection of the first body portion 110b on the substrate. In fig. 27, a dotted line box 130b schematically shows an overlapping region of the first and second body portions 110b and 210b. For example, the area of the overlapping region 130b of the first main body portion 110b and the second main body portion 210b is substantially equal to the area of the orthographic projection of the first main body portion 110b on the substrate. Alternatively, the ratio of the area of the overlapping region 130b to the area of the orthographic projection of the first body portion 110b on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 130b to the area of the orthogonal projection of the second body portion 210b on the substrate board is between 0.7 and 1, that is, most (for example, 70% or more) of the second body portion 210b overlaps the first body portion 110b.

For example, an orthographic projection of the first body portion 110b on the substrate base has a dimension W1b along the first direction X and a dimension H1b along the second direction Y, and an orthographic projection of the second body portion 210b on the substrate base has a dimension W7b along the first direction X and a dimension H7b along the second direction Y. Dimension W1b may be smaller than dimension W7b, and dimension H1b may be smaller than dimension H7b. For example, the ratio of dimension W1b to dimension W7b may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of dimension H1b to dimension H7b may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

In the first dummy pixel region DMP1, the display substrate may include a third compensation structure 300b and a second sub-reset signal line 62N2 in the third conductive layer 60. That is, the third compensation structure 300b is located in the third conductive layer 60.

The third compensation structure 300b includes a third body portion 310b, a third compensation structure protrusion 311b, and a fourth compensation structure protrusion 312b. The orthographic projection of the third body portion 310b on the substrate has a substantially rectangular shape or a truncated rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The third and fourth compensating structure protrusions 311b and 312b are located on opposite sides of the third body portion 310b, respectively. The third and fourth compensating structural protrusions 311b, 312b protrude in opposite directions relative to the third body portion 310b, e.g., the third compensating structural protrusion 311b extends leftward relative to the third body portion 310b in the first direction X, and the fourth compensating structural protrusion 312b extends rightward relative to the third body portion 310b in the first direction X.

A first dimension H4b of an orthographic projection of the third main body portion 310b on the substrate base along the second direction Y is greater than a second dimension H5b of an orthographic projection of the third compensation structure protrusion 311b on the substrate base along the second direction Y, and a first dimension H4b of an orthographic projection of the third main body portion 310b on the substrate base along the second direction Y is greater than a third dimension H6b of an orthographic projection of the fourth compensation structure protrusion 312b on the substrate base along the second direction Y. For example, the second dimension H5b of the orthographic projection of the third compensation structure protrusion 311b on the substrate along the second direction Y is substantially equal to the third dimension H6b of the orthographic projection of the fourth compensation structure protrusion 312b on the substrate along the second direction Y, or the ratio of the second dimension H5b to the third dimension H6b is between 0.8 and 1.2. A first dimension H4b of the orthographic projection of the third main body portion 310b on the substrate base along the second direction Y is much larger than a second dimension H5b of the orthographic projection of the third compensation structure protrusion 311b on the substrate base along the second direction Y, for example, a ratio of the first dimension H4b to the second dimension H5b or the third dimension H6b is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

In the embodiment of the present disclosure, the third compensation structure 300b located in the first dummy pixel region DMP1 is electrically connected to the second scan signal line 61N located in the display pixel region DP 1. For example, the second scan signal line 61N located in the display pixel region DP1 extends from the display pixel region DP1 to the first dummy pixel region DMP1. A portion of the second scanning signal line 61N in the first dummy pixel region DMP1 has a width wider than that of a portion of the second scanning signal line 61N in the display pixel region DP1, i.e., the third body portion 310b is formed. The width of the other portion of the second scanning signal line 61N (i.e., the third compensation structure protrusion 311b and the fourth compensation structure protrusion 312 b) located in the first virtual pixel region DMP1 is substantially equal to the width of the portion of the second scanning signal line 61N located in the display pixel region DP1, or the ratio of the two is between 0.8 and 1.2.

The orthographic projections of the second compensation structure 200b and the third compensation structure 300b on the substrate are at least partially overlapping. For example, an orthographic projection of the second body portion 210b on the substrate may at least partially overlap an orthographic projection of the third body portion 310b on the substrate. In the embodiment of the present disclosure, the overlapping area of the second body portion 210b and the third body portion 310b is designed to be relatively large. For example, the orthographic projection of the second body portion 210b on the substrate substantially covers the orthographic projection of the third body portion 310b on the substrate. In fig. 29, a dotted line frame 150b schematically shows an overlapping region of the third body portion 310b and the second body portion 210b. For example, the area of the overlapping region 150b of the third body portion 310b and the second body portion 210b is substantially equal to the area of the orthographic projection of the third body portion 310b on the substrate. In other words, the ratio of the area of the overlapping region 150b to the area of the orthographic projection of the third main body portion 310b on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 150b to the area of the orthogonal projection of the second main body portion 210b on the substrate is between 0.7 and 1, that is, most (for example, 70% or more) of the second main body portion 210b overlaps with the third main body portion 310b.

For example, an orthographic projection of the third body portion 310b on the substrate base has a dimension W4b along the first direction X and a dimension H4b along the second direction Y. Dimension W4b may be smaller than dimension W7b and dimension H1b may be smaller than dimension H4b. For example, the ratio of dimension W4b to dimension W7b may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of dimension H4b to dimension H7b may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

In the first dummy pixel region DMP1, the display substrate may further include a second initialization voltage line 68, a compensation connection part 160b, and a first transfer part 161b in the fourth conductive layer 70. In the first dummy pixel region DMP1, the display substrate may further include a data signal line 64, a first voltage line 65, a fifth compensation structure 500b, and a second transfer part 420b in the fifth conductive layer 80. Herein, the data signal line 64 and the first voltage line 65 are described using the same expressions and reference numerals, indicating that the data signal line 64 and the first voltage line 65 extend from the display pixel region DP1 to the first dummy pixel region DMP1, respectively.

The fifth compensation structure 500b includes a fifth body portion 510b. An orthogonal projection of the fifth body portion 510b on the substrate base plate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like.

For example, the fifth body portion 510b may be formed as an integral structure with the first voltage line 65, that is, the fifth body portion 510b may be a portion of the first voltage line 65, or the fifth body portion 510b may be a widened portion of the first voltage line 65.

A dimension W8b of an orthogonal projection of the fifth body portion 510b on the substrate base along the first direction X is larger than a dimension W9b of an orthogonal projection of the first voltage line 65 on the substrate base along the first direction X. For example, the ratio of dimension W8b to dimension W9b is greater than or equal to 3, or greater than or equal to 4, or between 3 and 30, or between 3 and 10, or between 3 and 8.

The orthographic projections of the fifth compensation structure 500b and the third compensation structure 300b on the substrate base plate at least partially overlap. For example, an orthographic projection of the fifth body portion 510b on the substrate may at least partially overlap an orthographic projection of the third body portion 310b on the substrate. In the embodiment of the present disclosure, the overlapping area of the fifth body portion 510b and the third body portion 310b is designed to be relatively large. For example, the orthographic projection of the third body portion 310b on the substrate substantially covers the orthographic projection of the fifth body portion 510b on the substrate. In fig. 22, a dotted line frame 180b schematically illustrates an overlapping region of the fifth and third body portions 510b and 310b. For example, the area of the overlapping region 180b of the fifth main body portion 510b and the third main body portion 310b is slightly larger than the area of the orthographic projection of the fifth main body portion 510b on the substrate. Or, the ratio of the area of the overlapping region 180b to the area of the orthogonal projection of the fifth body portion 510b on the substrate board is between 1.1 and 1.9. The ratio of the area of the overlapping region 180b to the area of the orthographic projection of the third body portion 310b on the substrate is between 0.4 and 0.7, or between 0.4 and 0.6.

One end of the compensation connection part 160b is electrically connected to the second compensation structure 200b through the via 1601b, and the other end is electrically connected to the first voltage line 65 through the via 1602 b.

For example, the orthographic projection of the third body portion 310b on the base substrate has a rectangular shape with missing corners. In this way, most of the second body portion 210b is covered by the third body portion 310b, and the unfilled corner portion of the third body portion 310b may expose the second body portion 210b therebelow. The via 1601b further exposes the second body portion 210b, and the compensation connection portion 160b in the fourth conductive layer 70 is electrically connected to the second body portion 210b in the second conductive layer 40 through the via 1601 b. The via 1602b exposes a portion of the compensation connection part 160b, and the first voltage line 65 in the fifth conductive layer 80 is electrically connected to the compensation connection part 160b in the fourth conductive layer 70 through the via 1602 b. The second compensation structure 200b may be electrically connected to the first voltage line 65 through the compensation connection part 160 b. In this way, the first voltage (e.g., the VDD voltage) may be transferred to the second compensation structure 200b.

In an embodiment of the present disclosure, the fourth compensation structure located in the sixth conductive layer 90 may be supplied with the first voltage; the first compensation structure 100b in the first conductive layer 30 is electrically connected to the first scan signal line 61, i.e., the first compensation structure 100b is supplied with the second scan signal; the second compensation structure 200b located in the second conductive layer 40 is electrically connected to the first voltage line 65, i.e., the second compensation structure 200b is supplied with the first voltage. Moreover, the fourth compensation structure 400b and the first compensation structure 100b have an overlapping region with an enlarged area, and the first compensation structure 100b and the second compensation structure 200b have an overlapping region with a larger area. In this way, capacitances may be formed between the fourth compensation structure 400b and the first compensation structure 100b and between the first compensation structure 100b and the second compensation structure 200b, respectively, which are connected in parallel to form a first compensation capacitor C1, as shown in fig. 21A, which schematically illustrates the first compensation capacitor C1. That is, the first compensation capacitor C1 includes 2 capacitors connected in parallel, for example, a first compensation sub-capacitor C11 and a second compensation sub-capacitor C12, and the first compensation sub-capacitor C11 and the second compensation sub-capacitor C12 are connected in parallel. One plate of one of the capacitors (e.g., the second compensation sub-capacitor C12) is the fourth compensation structure 400b, particularly the fourth main body portion 410b of the fourth compensation structure 400b, and the other plate is the first compensation structure 100b, particularly the first main body portion 110b of the first compensation structure 100 b; one plate of the other capacitance (e.g., the first compensation sub-capacitor C11) is the first compensation structure 100b, particularly the first body portion 110b of the first compensation structure 100b, and the other plate is the second compensation structure 200b, particularly the second body portion 210b of the second compensation structure 200b.

The capacitance value of the first compensation capacitor C1 is related to the overlapping area between the fourth compensation structure 400b and the first compensation structure 100b and the overlapping area between the first compensation structure 100b and the second compensation structure 200b. As described above, the overlapping area between the fourth compensation structure 400b and the first compensation structure 100b and the overlapping area between the first compensation structure 100b and the second compensation structure 200b are designed to be larger, and accordingly, the capacitance value of the first compensation capacitor C1 is also larger. The first compensation capacitor C1 is a load applied to the first scanning signal line 61. Since the capacitance value of the first compensation capacitor C1 is large, the load applied to the first scanning signal line 61 is also large, thereby achieving the purpose of compensating for the load on the first scanning signal line.

In this embodiment, the first compensation capacitor C1 includes 2 capacitances connected in parallel, and accordingly, the capacitance value of the first compensation capacitor C1 can be further increased. In addition, the areas of the first and second compensation structures themselves may be appropriately reduced, thereby facilitating the realization of a display panel with a high PPI.

In the embodiment of the present disclosure, the second compensation structure 200b located in the second conductive layer 40 is electrically connected to the first voltage line 65, i.e., the second compensation structure 200b is supplied with the first voltage; the third compensation structure 300b located in the third conductive layer 60 is electrically connected to the second scan signal line 61N, i.e., the third compensation structure 300b is supplied with the second scan signal; the fifth compensation structure 500b located in the fifth conductive layer 80 is electrically connected to the first voltage line 65, i.e., the fifth compensation structure 500b is supplied with the first voltage. Moreover, the second compensation structure 200b and the third compensation structure 300b have an overlapping region with an increased area therebetween, and the fifth compensation structure 500b and the third compensation structure 300b have an overlapping region with a larger area therebetween. In this way, capacitances may be formed between the second compensation structure 200B and the third compensation structure 300B and between the fifth compensation structure 500B and the third compensation structure 300B, respectively, which are connected in parallel to form a second compensation capacitor C2, as shown in fig. 21B, which schematically illustrates the second compensation capacitor C2. That is, the second compensation capacitor C2 includes 2 capacitors connected in parallel, for example, a third compensation sub-capacitor C21 and a fourth compensation sub-capacitor C22, and the third compensation sub-capacitor C21 and the fourth compensation sub-capacitor C22 are connected in parallel. One plate of one of the capacitors (e.g., the third compensation sub-capacitor C21) is the second compensation structure 200b, particularly the second main body portion 210b of the second compensation structure 200b, and the other plate is the third compensation structure 300b, particularly the third main body portion 310b of the third compensation structure 300 b; one plate of the other capacitor (e.g., the fourth compensation sub-capacitor C22) is the third compensation structure 300b, particularly the third body portion 310b of the third compensation structure 300b, and the other plate is the fifth compensation structure 500b, particularly the fifth body portion 510b of the fifth compensation structure 500 b.

The capacitance value of the second compensation capacitor C2 is related to the overlapping area between the second compensation structure 200b and the third compensation structure 300b and the overlapping area between the fifth compensation structure 500b and the third compensation structure 300 b. As described above, the overlapping area between the second compensation structure 200b and the third compensation structure 300b and the overlapping area between the fifth compensation structure 500b and the third compensation structure 300b are designed to be large, and accordingly, the capacitance value of the second compensation capacitor C2 is also large. The second compensation capacitor C2 is a load applied to the second scanning signal line 61N. Since the capacitance value of the second compensation capacitor C2 is large, the load applied to the second scanning signal line 61N is also large, thereby achieving the purpose of compensating for the load on the second scanning signal line.

In this embodiment, the second compensation capacitor C2 includes 2 capacitances connected in parallel, and accordingly, the capacitance value of the second compensation capacitor C2 can be further increased. In addition, the areas of the second and third compensation structures themselves may be appropriately reduced, thereby facilitating the realization of a display panel with a high PPI.

It should be noted that, in this embodiment, the second adaptor 420b is electrically connected to the first adaptor 161 through the via 1604b, and the first adaptor 161 is electrically connected to other components through the via 1603, which is not described herein again.

Fig. 33 is a plan view illustrating an exemplary implementation of a sub-pixel in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure, in which plan views of two adjacent sub-pixels in the display pixel region are schematically illustrated. Fig. 34 is a plan view illustrating an exemplary implementation of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure, in which plan views of two adjacent virtual sub-pixel structures in a first virtual pixel region are schematically illustrated. Fig. 35 to 42 are plan views illustrating some film layers of an exemplary embodiment of two adjacent virtual sub-pixel structures in fig. 34. For example, fig. 35 to 42 schematically show a first conductive layer, a second conductive layer, a combination of the first conductive layer and the second conductive layer, a third conductive layer, a combination of the first conductive layer, the second conductive layer, and the third conductive layer, a fourth conductive layer, a combination of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, and a fifth conductive layer in the first dummy pixel region, respectively.

It should be noted that the following description focuses on differences between the embodiments shown in fig. 33 to fig. 42 with respect to the above-mentioned embodiments, and the same points between them can be referred to the above description, and are not repeated herein. That is, in this document, the various embodiments or implementations may be combined with each other without conflict.

Referring to fig. 33 to 42 in combination, the pixel driving circuit may include: a plurality of thin film transistors, and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

The display substrate may further include a plurality of signal lines, for example, the plurality of signal lines including: a first scanning signal line 61 and a second scanning signal line 61N for transmitting scanning signals, a second reset signal line 62N for transmitting a reset control signal, a light emission control line 63 for transmitting a light emission control signal, a data signal line 64 for transmitting a data signal, a first voltage line 65 for transmitting a first voltage, a first initializing voltage line 66 and a second initializing voltage line 68 for transmitting an initializing voltage, and a second voltage line 67 for transmitting a second voltage. For example, the first voltage may be a VDD voltage, the second voltage may be a VSS voltage, and the first voltage may be higher than the second voltage.

For example, in the display pixel region, between adjacent 2 sub-pixels, there is a first axis symmetry line AX1, and orthogonal projections of the adjacent 2 sub-pixels on the substrate are in an axisymmetric relationship with respect to the first axis symmetry line AX 1. It should be noted that, in this document, an axis symmetry line represents a virtual line, not a physical line.

For example, in the first virtual pixel region, a second axis of symmetry AX2 exists between the adjacent 2 virtual sub-pixel structures, and orthogonal projections of the adjacent 2 virtual sub-pixel structures on the substrate are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

Referring to fig. 33 to 42 in combination, in the first dummy pixel region DMP1, the display substrate may include an emission control line 63 and a first compensation structure 100c in the first conductive layer 30. That is, the first compensation structure 100c is located in the first conductive layer 30.

The first compensation structure 100c includes a first body portion 110c, a first compensation structure protrusion 111c, and a second compensation structure protrusion 112c. The orthographic projection of the first body portion 110c on the substrate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The first and second compensating structure protrusions 111c and 112c are located at opposite sides of the first body portion 110c, respectively. The first and second compensation structure protrusions 111c and 112c protrude in opposite directions with respect to the first body portion 110c.

A first dimension H1c of an orthographic projection of the first main body portion 110c on the substrate base along the second direction Y is greater than a second dimension H2c of an orthographic projection of the first compensation structure protrusion 111c on the substrate base along the second direction Y, and the first dimension H1c of the orthographic projection of the first main body portion 110c on the substrate base along the second direction Y is greater than a third dimension H3c of an orthographic projection of the second compensation structure protrusion 112c on the substrate base along the second direction Y. For example, a second dimension H2c of the orthographic projection of the first compensation structure protrusion 111c on the substrate base along the second direction Y is substantially equal to a third dimension H3c of the orthographic projection of the second compensation structure protrusion 112c on the substrate base along the second direction Y, or a ratio of the second dimension H2c to the third dimension H3c is between 0.8 and 1.2. A first dimension H1c of an orthographic projection of the first main body portion 110c on the substrate base along the second direction Y is much larger than a second dimension H2c of an orthographic projection of the first compensation structure protrusion 111c on the substrate base along the second direction Y, for example, a ratio of the first dimension H1c to the second dimension H2c or the third dimension H3c is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

Among the adjacent 2 virtual sub-pixel structures, 2 first compensation structures 100c are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

The second compensation structure protrusions 112c of the 2 first compensation structures 100c are connected to each other. In the embodiment of the present disclosure, the first compensation structure 100c located in the first dummy pixel region DMP1 is electrically connected to the first scan signal line 61 located in the display pixel region DP 1. For example, the first scan signal line 61 located in the display pixel region DP1 extends from the display pixel region DP1 to the first dummy pixel region DMP1. A portion of the first scan signal line 61 in the first dummy pixel region DMP1 has a width wider than a width of a portion of the first scan signal line 61 in the display pixel region DP1, that is, the first body portion 110c is formed. The width of the other portion of the first scanning signal line 61 (i.e., the first and second compensating structure protrusions 111c and 112 c) located in the first virtual pixel region DMP1 is substantially equal to the width of the portion of the first scanning signal line 61 located in the display pixel region DP1, or the ratio of the two is between 0.8 and 1.2.

In the first dummy pixel region DMP1, the display substrate may include a second compensation structure 200c in the second conductive layer 40. That is, the second compensation structure 200c is located in the second conductive layer 40. The second compensation structure 200c includes a second body portion 210c and a second compensation-structure connection portion 211c. An orthogonal projection of the second body portion 210c on the substrate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The second compensation-structure connection part 211c protrudes toward one direction with respect to the second body part 210c.

For example, in the first virtual pixel region DMP1, the second compensation structures 200c between the adjacent sub-pixel structures are disposed apart from each other.

Among the adjacent 2 virtual sub-pixel structures, 2 second compensation structures 200c are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

The orthographic projections of the first compensation structure 100c and the second compensation structure 200c on the substrate base plate at least partially overlap. For example, an orthographic projection of the first body portion 110c on the base substrate at least partially overlaps with an orthographic projection of the second body portion 210c on the base substrate. In the embodiment of the present disclosure, the overlapping area of the first body portion 110c and the second body portion 210c is designed to be relatively large. For example, the orthographic projection of the second body portion 210c on the substrate substantially covers the orthographic projection of the first body portion 110c on the substrate. The dashed line box 130c schematically shows the overlapping area of the first body portion 110c and the second body portion 210c. For example, the area of the overlapping region 130c of the first main body portion 110c and the second main body portion 210c is substantially equal to the area of the orthographic projection of the first main body portion 110c on the substrate. Alternatively, the ratio of the area of the overlapping region 130c to the area of the orthographic projection of the first body portion 110c on the substrate is between 0.8 and 1.2. The ratio of the area of the overlap region 130c to the area of the orthogonal projection of the second body portion 210c on the substrate board is between 0.7 and 1, that is, most (for example, 70% or more) of the second body portion 210c overlaps the first body portion 110c.

For example, an orthographic projection of the first body portion 110c on the base substrate has a dimension W1c along the first direction X and a dimension H1c along the second direction Y, and an orthographic projection of the second body portion 210c on the base substrate has a dimension W7c along the first direction X and a dimension H7c along the second direction Y. Dimension W1c may be smaller than dimension W7c and dimension H1c may be smaller than dimension H7c. For example, the ratio of dimension W1c to dimension W7c may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of dimension H1c to dimension H7c may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

In the first dummy pixel region DMP1, the display substrate may include a third compensation structure 300c in the third conductive layer 60. That is, the third compensation structure 300c is located in the third conductive layer 60.

The third compensation structure 300c includes a third body portion 310c, a third compensation structure protrusion 311c, and a fourth compensation structure protrusion 312c. An orthogonal projection of the third body portion 310c on the substrate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The third and fourth compensating structural protrusions 311c and 312c are located on opposite sides of the third body portion 310c, respectively. The third and fourth compensating structure protrusions 311c and 312c protrude in opposite directions with respect to the third body portion 310c.

A first dimension H4c of an orthographic projection of the third main body portion 310c on the substrate base along the second direction Y is greater than a second dimension H5c of an orthographic projection of the third compensation structure protrusion 311c on the substrate base along the second direction Y, and a first dimension H4c of an orthographic projection of the third main body portion 310c on the substrate base along the second direction Y is greater than a third dimension H6c of an orthographic projection of the fourth compensation structure protrusion 312c on the substrate base along the second direction Y. For example, a second dimension H5c of an orthographic projection of the third compensation structure protrusion 311c on the substrate along the second direction Y is substantially equal to a third dimension H6c of an orthographic projection of the fourth compensation structure protrusion 312c on the substrate along the second direction Y, or a ratio of the second dimension H5c to the third dimension H6c is between 0.8 and 1.2. A first dimension H4c of the orthographic projection of the third main body portion 310c on the substrate base along the second direction Y is much larger than a second dimension H5c of the orthographic projection of the third compensation structure protrusion 311c on the substrate base along the second direction Y, for example, a ratio of the first dimension H4c to the second dimension H5c or the third dimension H6c is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

Of the adjacent 2 virtual sub-pixel structures, 2 third compensation structures 300c are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

The fourth compensation structure protrusions 312c of the 2 third compensation structures 300c are connected to each other. In the embodiment of the present disclosure, the third compensation structure 300c located in the first dummy pixel region DMP1 is electrically connected to the second scan signal line 61N located in the display pixel region DP 1. For example, the second scan signal line 61N located in the display pixel region DP1 extends from the display pixel region DP1 to the first dummy pixel region DMP1. A portion of the second scanning signal line 61N in the first dummy pixel region DMP1 has a width wider than that of a portion of the second scanning signal line 61N in the display pixel region DP1, i.e., the third body portion 310c is formed. The width of the other portion of the second scanning signal line 61N in the first virtual pixel region DMP1 (i.e., the third compensation structure protrusion 311c and the fourth compensation structure protrusion 312 c) is substantially equal to the width of the portion of the second scanning signal line 61N in the display pixel region DP1, or the ratio of the two is between 0.8 and 1.2.

The orthographic projections of the second compensation structure 200c and the third compensation structure 300c on the substrate base plate at least partially overlap. For example, an orthographic projection of the second body portion 210c on the substrate may at least partially overlap an orthographic projection of the third body portion 310c on the substrate. In the embodiment of the present disclosure, the overlapping area of the second body portion 210c and the third body portion 310c is designed to be relatively large. For example, the orthographic projection of the second body portion 210c on the substrate substantially covers the orthographic projection of the third body portion 310c on the substrate. The dotted line box 150c schematically shows the overlapping region of the third body portion 310c and the second body portion 210c. For example, the area of the overlapping region 150c of the third body portion 310c and the second body portion 210c is substantially equal to the area of the orthographic projection of the third body portion 310c on the substrate base plate. In other words, the ratio of the area of the overlapping region 150c to the area of the orthographic projection of the third body portion 310c on the substrate is between 0.8 and 1.2. The ratio of the area of the overlap region 150c to the area of the orthogonal projection of the second body portion 210c on the substrate board is between 0.7 and 1, that is, most (for example, 70% or more) of the second body portion 210c overlaps the third body portion 310c.

For example, an orthographic projection of the third body portion 310c on the substrate base has a dimension W4c along the first direction X and a dimension H4c along the second direction Y. Dimension W4c may be smaller than dimension W7c and dimension H1c may be smaller than dimension H4c. For example, the ratio of dimension W4c to dimension W7c may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of dimension H4c to dimension H7c may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

In the first dummy pixel region DMP1, the display substrate may further include a second initialization voltage line 68 and a compensation connection part 160c in the fourth conductive layer 70. In the first dummy pixel region DMP1, the display substrate may further include a data signal line 64, a first voltage line 65, and a fifth compensation structure 500c in the fifth conductive layer 80.

In the adjacent 2 virtual sub-pixel structures, 2 compensation connections 160c are disposed at intervals from each other, and the 2 compensation connections 160c are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

The fifth compensation structure 500c includes a fifth body portion 510c. An orthogonal projection of the fifth body portion 510c on the base substrate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like.

For example, the fifth body portion 510c may be formed as an integral structure with the first voltage line 65, that is, the fifth body portion 510c may be a portion of the first voltage line 65, or the fifth body portion 510c may be a widened portion of the first voltage line 65.

A dimension W8c of an orthographic projection of the fifth main body portion 510c on the substrate base in the first direction X is larger than a dimension W9c of an orthographic projection of the first voltage line 65 on the substrate base in the first direction X. For example, the ratio of dimension W8c to dimension W9c is greater than or equal to 3, or greater than or equal to 4, or between 3 and 30, or between 3 and 10, or between 3 and 8.

Among the adjacent 2 virtual sub-pixel structures, 2 fifth compensation structures 500c are in an axisymmetric relationship with respect to the second axis of symmetry AX2, for example, 2 fifth body portions 510 are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

In the adjacent 2 virtual sub-pixel structures, 2 fifth body portions 510c are connected to each other, thereby forming one integral structure. For example, the orthographic projection of the 2 fifth body portions 510c connected to each other on the substrate base plate has a rectangular shape. The area of the fifth main body portion 510c is relatively large, and among the adjacent 2 virtual sub-pixel structures, 2 fifth main body portions 510c form an integral structure, which is beneficial to the planarization of a film layer covering the fifth conductive layer, and thus, is beneficial to the subsequent formation process of an anode layer.

One end of the compensation connection part 160c is electrically connected to the second compensation structure 200c through the via 1601c, and the other end is electrically connected to the first voltage line 65 through the via 1602 c. For example, the via 1601c exposes a portion of the second compensation structure connection portion 211c, and the compensation connection portion 160c located in the fourth conductive layer 70 is electrically connected to the second compensation structure connection portion 211c located in the second conductive layer 40 through the via 1601 c. The via 1602c exposes a portion of the compensation connection part 160c, and the first voltage line 65 in the fifth conductive layer 80 is electrically connected to the compensation connection part 160c in the fourth conductive layer 70 through the via 1602 c. The second compensation structure 200c may be electrically connected to the first voltage line 65 through the compensation connection part 160c. In this way, the first voltage (e.g., the VDD voltage) may be transferred to the second compensation structure 200c.

In the embodiment of the present disclosure, the first compensation structure 100c located in the first conductive layer 30 is electrically connected to the first scan signal line 61, i.e., the first compensation structure 100c is supplied with the first scan signal. The second compensation structure 200c located in the second conductive layer 40 is electrically connected to the first voltage line 65, i.e., the second compensation structure 200c is supplied with the first voltage. Moreover, the first compensation structure 100c and the second compensation structure 200c have a larger overlapping area. In this way, a first compensation capacitor C1 may be formed between the first compensation structure 100C and the second compensation structure 200C, as shown in fig. 8A, which schematically illustrates the first compensation capacitor C1. That is, one plate of the first compensation capacitor C1 is the first compensation structure 100C, in particular, the first main body portion 110C of the first compensation structure 100C; the other plate is the second compensation structure 200c, in particular the second body portion 210c of the second compensation structure 200c.

The capacitance value of the first compensation capacitor C1 is related to the overlapping area between the first compensation structure 100C and the second compensation structure 200C. As described above, the overlapping area between the first compensation structure 100C and the second compensation structure 200C is designed to be large, and accordingly, the capacitance value of the first compensation capacitor C1 is also large. The first compensation capacitor C1 is a load applied to the first scanning signal line 61. Since the capacitance value of the first compensation capacitor C1 is large, the load applied to the first scanning signal line 61 is also large, thereby achieving the purpose of compensating for the load on the first scanning signal line.

In the embodiment of the present disclosure, the second compensation structure 200c located in the second conductive layer 40 is electrically connected to the first voltage line 65, i.e., the second compensation structure 200c is supplied with the first voltage; the third compensation structure 300c located in the third conductive layer 60 is electrically connected to the second scan signal line 61N, i.e., the third compensation structure 300c is supplied with the second scan signal; the fifth compensation structure 500c located in the fifth conductive layer 80 is electrically connected to the first voltage line 65, i.e., the fifth compensation structure 500c is supplied with the first voltage. Moreover, the second compensation structure 200c and the third compensation structure 300c have an overlapping region with an increased area therebetween, and the fifth compensation structure 500c and the third compensation structure 300c have an overlapping region with a larger area therebetween. In this way, capacitances may be formed between the second compensation structure 200C and the third compensation structure 300C and between the fifth compensation structure 500C and the third compensation structure 300C, respectively, which are connected in parallel to form a second compensation capacitor C2, as shown in fig. 21B, which schematically illustrates the second compensation capacitor C2. That is, the second compensation capacitor C2 includes 2 capacitors connected in parallel, wherein one plate of one capacitor is the second compensation structure 200C, particularly the second main body portion 210C of the second compensation structure 200C, and the other plate is the third compensation structure 300C, particularly the third main body portion 310C of the third compensation structure 300C; one plate of the other capacitor is the third compensation structure 300c, in particular the third body portion 310c of the third compensation structure 300c, and the other plate is the fifth compensation structure 500c, in particular the fifth body portion 510c of the fifth compensation structure 500c.

The capacitance value of the second compensation capacitor C2 is related to the overlapping area between the second compensation structure 200C and the third compensation structure 300C and the overlapping area between the fifth compensation structure 500C and the third compensation structure 300C. As described above, the overlapping area between the second compensation structure 200C and the third compensation structure 300C and the overlapping area between the fifth compensation structure 500C and the third compensation structure 300C are designed to be large, and accordingly, the capacitance value of the second compensation capacitor C2 is also large. The second compensation capacitor C2 is a load applied to the second scanning signal line 61N. Since the capacitance value of the second compensation capacitor C2 is large, the load applied to the second scanning signal line 61N is also large, thereby achieving the purpose of compensating the load on the second scanning signal line.

In this embodiment, the second compensation capacitor C2 includes 2 capacitances connected in parallel, and accordingly, the capacitance value of the second compensation capacitor C2 can be further increased. In addition, the areas of the second and third compensation structures themselves may be appropriately reduced, thereby facilitating the implementation of a display panel with a high PPI.

Fig. 43 is a plan view illustrating an exemplary implementation of a sub-pixel in a display pixel area of a display substrate according to some exemplary embodiments of the present disclosure, in which plan views of two adjacent sub-pixels in the display pixel area are schematically illustrated. Fig. 44 is a plan view illustrating an exemplary implementation of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure, in which plan views of two adjacent virtual sub-pixel structures in a first virtual pixel region are schematically illustrated. Fig. 45 to 54 are plan views illustrating some film layers of an exemplary embodiment of two adjacent dummy sub-pixel structures in fig. 44. For example, fig. 45 to 54 schematically show a sixth conductive layer, a first conductive layer, a combination of the sixth conductive layer and the first conductive layer, a second conductive layer, a combination of the sixth conductive layer, the first conductive layer and the second conductive layer, a third conductive layer, a combination of the sixth conductive layer, the first conductive layer, the second conductive layer and the third conductive layer, a fourth conductive layer, a combination of the sixth conductive layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer, and a fifth conductive layer, respectively, which are located in the first dummy pixel region.

It should be noted that the following description focuses on differences between the embodiments shown in fig. 43 to 54 and the above-mentioned embodiments, and the same points between them can be referred to the above description, and are not repeated herein. That is, in this document, the various embodiments or implementations may be combined with each other without conflict.

Referring to fig. 43 to 54 in combination, the pixel driving circuit may include: a plurality of thin film transistors, and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

The display substrate may further include a plurality of signal lines, for example, the plurality of signal lines include: a first scanning signal line 61 and a second scanning signal line 61N for transmitting scanning signals, a second reset signal line 62N for transmitting a reset control signal, a light emission control line 63 for transmitting a light emission control signal, a data signal line 64 for transmitting a data signal, a first voltage line 65 for transmitting a first voltage, a first initializing voltage line 66 and a second initializing voltage line 68 for transmitting an initializing voltage, and a second voltage line 67 for transmitting a second voltage. For example, the first voltage may be a VDD voltage, the second voltage may be a VSS voltage, and the first voltage may be higher than the second voltage.

For example, in the display pixel region, between adjacent 2 sub-pixels, there is a first axis symmetry line AX1, and orthogonal projections of the adjacent 2 sub-pixels on the substrate are in an axisymmetric relationship with respect to the first axis symmetry line AX 1.

For example, in the first virtual pixel region, between the adjacent 2 virtual sub-pixel structures, there is a second axis of symmetry AX2, and orthogonal projections of the adjacent 2 virtual sub-pixel structures on the substrate are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

With combined reference to fig. 43-54, the display substrate includes a plurality of film layers disposed on the base substrate. In some embodiments, the plurality of film layers includes at least sixth conductive layer 90, first semiconductor layer 20, first conductive layer 30, second conductive layer 40, second semiconductor layer 50, third conductive layer 60, fourth conductive layer 70, and fifth conductive layer 80. Sixth conductive layer 90, first semiconductor layer 20, first conductive layer 30, second conductive layer 40, second semiconductor layer 50, third conductive layer 60, fourth conductive layer 70, and fifth conductive layer 80 are disposed away from substrate base plate 10 in this order.

In the first dummy pixel region DMP1, the display substrate may include a fourth compensation structure 400d in the sixth conductive layer 90. For example, the sixth conductive layer 90 may be a light-shielding layer, i.e., the fourth compensation structure 400d is located in the light-shielding layer.

The fourth compensation structure 400d may include a fourth body portion 410d, a fifth compensation structure protrusion 411d, and a sixth compensation structure protrusion 412d. The orthogonal projection of the fourth body portion 410d on the substrate base plate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The fifth and sixth compensation structure protrusions 411d and 412d are located at opposite sides of the fourth body portion 410d, respectively. The fifth and sixth compensation structure protrusions 411d and 412d protrude in opposite directions with respect to the fourth body portion 410 d. The sixth compensation structure protrusions 412d of the 2 fourth compensation structures 400d are connected to each other.

Of the adjacent 2 virtual sub-pixel structures, 2 fourth compensation structures 400d are in an axisymmetric relationship with respect to the second axis of symmetry AX 2. That is, the orthographic projections of the 2 fourth compensation structures 400d on the substrate base plate are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

Referring to fig. 43 to 54 in combination, in the first dummy pixel region DMP1, the display substrate may include an emission control line 63 and a first compensation structure 100d in the first conductive layer 30. That is, the first compensation structure 100d is located in the first conductive layer 30.

The first compensation structure 100d includes a first body portion 110d, a first compensation structure protrusion 111d, and a second compensation structure protrusion 112d. The orthographic projection of the first body portion 110d on the substrate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The second compensating structure protrusion 112d is spaced from the first body portion 110d, e.g., in the first direction Y, and the second compensating structure protrusion 112d extends substantially along the first direction X. The first compensation structure protrusion 111d extends in the second direction Y to connect the first body portion 110d and the second compensation structure protrusion 112d.

Of the adjacent 2 virtual sub-pixel structures, 2 first compensation structures 100d are in an axisymmetric relationship with respect to the second axis of symmetry AX 2. That is, the orthographic projections of the 2 first compensation structures 100d on the substrate base plate are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

The second compensation structure protrusions 112d of the 2 first compensation structures 100d are connected to each other to form a structure extending in the first direction X. In the embodiment of the present disclosure, the first compensation structure 100d located in the first dummy pixel region DMP1 is electrically connected to the first scan signal line 61 located in the display pixel region DP 1. For example, the first scan signal line 61 positioned in the display pixel region DP1 extends from the display pixel region DP1 to the first dummy pixel region DMP1. A portion of the first scan signal line 61 in the first dummy pixel region DMP1 is formed as a second compensation structure protrusion 112d. That is, the width of the portion of the first scanning signal line 61 located in the first dummy pixel region DMP1 (i.e., the second compensation structure protrusion 112 d) is substantially equal to the width of the portion of the first scanning signal line 61 located in the display pixel region DP1, or the ratio of the two is between 0.8 and 1.2.

The orthographic projections of the first compensation structure 100d and the fourth compensation structure 400d on the substrate base plate at least partially overlap. For example, an orthographic projection of the first body portion 110d on the substrate is at least partially overlapped with an orthographic projection of the fourth body portion 410d on the substrate. In the embodiment of the present disclosure, the overlapping area of the first and fourth body portions 110d and 410d is designed to be relatively large. For example, the orthographic projection of the first body portion 110d on the substrate substantially covers the orthographic projection of the fourth body portion 410d on the substrate. The dotted line box 120d schematically shows an overlapping region of the first and fourth body portions 110d and 410 d. For example, the area of the overlapping region 120d of the first and fourth body portions 110d and 410d is substantially equal to the area of the orthographic projection of the fourth body portion 410d on the substrate base plate. Alternatively, the ratio of the area of the overlapping region 120d to the area of the orthogonal projection of the fourth body portion 410d on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 120d to the area of the orthographic projection of the first body portion 110d on the substrate is between 0.3 and 1, or between 0.35 and 0.9, or between 0.6 and 0.8.

In the first dummy pixel region DMP1, the display substrate may include a second compensation structure 200d in the second conductive layer 40. That is, the second compensation structure 200d is located in the second conductive layer 40. The second compensation structure 200d includes a second body portion 210d and a second compensation structure connection portion 211d. The orthographic projection of the second body portion 210d on the substrate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The second compensation-structure connection part 211d protrudes toward one direction with respect to the second body part 210d.

For example, in the first virtual pixel region DMP1, the second compensation structures 200d between the adjacent virtual sub-pixel structures are disposed apart from each other.

Of the adjacent 2 virtual sub-pixel structures, 2 second compensation structures 200d are in an axisymmetric relationship with respect to the second axis of symmetry AX 2. That is, the orthographic projections of the 2 second compensation structures 200d on the substrate base plate are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

The orthographic projections of the first compensation structure 100d and the second compensation structure 200d on the substrate base plate at least partially overlap. For example, an orthographic projection of the first body portion 110d on the substrate at least partially overlaps with an orthographic projection of the second body portion 210d on the substrate. In the embodiment of the present disclosure, the overlapping area of the first body portion 110d and the second body portion 210d is designed to be relatively large. For example, the orthographic projection of the second body portion 210d on the substrate substantially covers the orthographic projection of the first body portion 110d on the substrate. The dashed line box 130d schematically illustrates the overlapping area of the first and second body portions 110d and 210d. For example, the area of the overlapping region 130d of the first and second body portions 110d and 210d is substantially equal to the area of the orthographic projection of the first body portion 110d on the substrate base. Alternatively, the ratio of the area of the overlapping region 130d to the area of the orthographic projection of the first body portion 110d on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 130d to the area of the orthogonal projection of the second body portion 210d on the substrate board is between 0.7 and 1, that is, most (for example, 70% or more) of the second body portion 210d overlaps the first body portion 110 d.

In the first dummy pixel region DMP1, the display substrate may include a third compensation structure 300d in the third conductive layer 60. That is, the third compensation structure 300d is located in the third conductive layer 60.

The third compensation structure 300d includes a third body portion 310d, a third compensation structure protrusion 311d, and a fourth compensation structure protrusion 312d. An orthogonal projection of the third body portion 310d on the substrate board has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like. The third and fourth compensating structure protrusions 311d and 312d are located on opposite sides of the third body portion 310d, respectively. The third and fourth compensating structure protrusions 311d and 312d protrude in opposite directions with respect to the third body portion 310d.

Among the adjacent 2 virtual sub-pixel structures, 2 third compensation structures 300d are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

The fourth compensation structure protrusions 312d of the 2 third compensation structures 300d are connected to each other. In the embodiment of the present disclosure, the third compensation structure 300d located in the first dummy pixel region DMP1 is electrically connected to the second scan signal line 61N located in the display pixel region DP 1. For example, the second scan signal line 61N located in the display pixel region DP1 extends from the display pixel region DP1 to the first dummy pixel region DMP1. A portion of the second scanning signal line 61N in the first dummy pixel region DMP1 has a width wider than that of a portion of the second scanning signal line 61N in the display pixel region DP1, i.e., the third body portion 310d is formed. The width of the other portion of the second scanning signal line 61N in the first virtual pixel region DMP1 (i.e., the third compensation structure protrusion 311d and the fourth compensation structure protrusion 312 d) is substantially equal to the width of the portion of the second scanning signal line 61N in the display pixel region DP1, or the ratio of the two is between 0.8 and 1.2.

The orthographic projections of the second compensation structure 200d and the third compensation structure 300d on the substrate are at least partially overlapped. For example, an orthographic projection of the second body portion 210d on the substrate may at least partially overlap an orthographic projection of the third body portion 310d on the substrate. In the embodiment of the present disclosure, the overlapping area of the second body portion 210d and the third body portion 310d is designed to be relatively large. For example, the orthographic projection of the second body portion 210d on the substrate substantially covers the orthographic projection of the third body portion 310d on the substrate. The dashed box 150d schematically illustrates the overlapping area of the third body portion 310d and the second body portion 210d. For example, the area of the overlapping region 150d of the third body portion 310d and the second body portion 210d is substantially equal to the area of the orthographic projection of the third body portion 310d on the substrate base plate. Alternatively, the ratio of the area of the overlapping region 150d to the area of the orthographic projection of the third body portion 310d on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 150d to the area of the orthogonal projection of the second body portion 210d on the substrate board is between 0.7 and 1, that is, most (for example, 70% or more) of the second body portion 210d overlaps the third body portion 310d.

In the first dummy pixel region DMP1, the display substrate may further include a second initialization voltage line 68 and a compensation connection part 160d in the fourth conductive layer 70. In the first dummy pixel region DMP1, the display substrate may further include a data signal line 64, a first voltage line 65, and a fifth compensation structure 500d in the fifth conductive layer 80.

In the adjacent 2 virtual sub-pixel structures, 2 compensation connections 160d are connected to each other by a connection structure extending in the first direction X, and the 2 compensation connections 160d are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

The fifth compensation structure 500d includes a fifth body portion 510d. An orthogonal projection of the fifth body portion 510d on the substrate base plate has a substantially rectangular shape. "generally rectangular" herein may include rectangular, square, rectangular with at least one corner rounded, rectangular with at least one corner chamfered, and the like.

For example, the fifth body portion 510d may be formed as an integral structure with the first voltage line 65, that is, the fifth body portion 510d may be a portion of the first voltage line 65, or the fifth body portion 510d may be a widened portion of the first voltage line 65.

Among the adjacent 2 virtual sub-pixel structures, 2 fifth compensation structures 500d are in an axisymmetric relationship with respect to the second axis of symmetry AX2, for example, 2 fifth body portions 510 are in an axisymmetric relationship with respect to the second axis of symmetry AX 2. That is, the orthographic projections of the 2 fifth compensation structures 500d on the base substrate are in an axisymmetric relationship with respect to the second axis of symmetry AX2, for example, the orthographic projections of the 2 fifth trunk portions 510 on the base substrate are in an axisymmetric relationship with respect to the second axis of symmetry AX 2.

In the adjacent 2 dummy sub-pixel structures, 2 fifth body portions 510d are connected to each other, thereby forming one integral structure. The area of the fifth main body portion 510d is relatively large, and among the adjacent 2 virtual sub-pixel structures, 2 fifth main body portions 510d form an integral structure, which is beneficial to the planarization of a film layer covering the fifth conductive layer, thereby being beneficial to the subsequent formation process of an anode layer.

One end of the compensation connection part 160d is electrically connected to the second compensation structure 200d through the via 1601d, and the other end is electrically connected to the first voltage line 65 through the via 1602 d. For example, the via 1601d exposes a portion of the second compensation structure connection portion 211d, and the compensation connection portion 160d located in the fourth conductive layer 70 is electrically connected to the second compensation structure connection portion 211d located in the second conductive layer 40 through the via 1601 d. The via 1602d exposes a portion of the compensation connection part 160d, and the first voltage line 65 in the fifth conductive layer 80 is electrically connected to the compensation connection part 160d in the fourth conductive layer 70 through the via 1602 d. The second compensation structure 200d may be electrically connected to the first voltage line 65 through the compensation connection part 160d. In this way, the first voltage (e.g., VDD voltage) may be transferred to the second compensation structure 200d.

In an embodiment of the present disclosure, the fourth compensation structure 400d located in the sixth conductive layer 90 may be supplied with the first voltage; the first compensation structure 100d in the first conductive layer 30 is electrically connected to the first scan signal line 61, i.e., the first compensation structure 100d is supplied with a first scan signal; the second compensation structure 200d located in the second conductive layer 40 is electrically connected to the first voltage line 65, i.e., the second compensation structure 200d is supplied with the first voltage. Moreover, the fourth compensation structure 400d and the first compensation structure 100d have an overlapping region with an increased area, and the first compensation structure 100d and the second compensation structure 200d have an overlapping region with a larger area. In this way, capacitances may be formed between the fourth compensation structure 400d and the first compensation structure 100d and between the first compensation structure 100d and the second compensation structure 200d, respectively, which are connected in parallel to form a first compensation capacitor C1, as shown in fig. 21A, which schematically illustrates the first compensation capacitor C1. That is, the first compensation capacitor C1 includes 2 capacitors connected in parallel, wherein one plate of one capacitor is the fourth compensation structure 400d, particularly the fourth main body portion 410d of the fourth compensation structure 400d, and the other plate is the first compensation structure 100d, particularly the first main body portion 110d of the first compensation structure 100 d; one plate of the other capacitor is the first compensation structure 100d, in particular the first body portion 110d of the first compensation structure 100d, and the other plate is the second compensation structure 200d, in particular the second body portion 210d of the second compensation structure 200d.

The capacitance of the first compensation capacitor C1 is related to the overlapping area between the fourth compensation structure 400d and the first compensation structure 100d and the overlapping area between the first compensation structure 100d and the second compensation structure 200d. As described above, the overlapping area between the fourth compensation structure 400d and the first compensation structure 100d and the overlapping area between the first compensation structure 100d and the second compensation structure 200d are designed to be larger, and accordingly, the capacitance value of the first compensation capacitor C1 is also larger. The first compensation capacitor C1 is a load applied to the first scanning signal line 61. Since the capacitance value of the first compensation capacitor C1 is large, the load applied to the first scanning signal line 61 is also large, thereby achieving the purpose of compensating for the load on the first scanning signal line.

In this embodiment, the first compensation capacitor C1 includes 2 capacitances connected in parallel, and accordingly, the capacitance value of the first compensation capacitor C1 can be further increased. In addition, the areas of the first and second compensation structures themselves may be appropriately reduced, thereby facilitating the implementation of a display panel with a high PPI.

In the embodiment of the present disclosure, the second compensation structure 200d located in the second conductive layer 40 is electrically connected to the first voltage line 65, that is, the second compensation structure 200d is supplied with the first voltage; the third compensation structure 300d located in the third conductive layer 60 is electrically connected to the second scanning signal line 61N, i.e., the third compensation structure 300d is supplied with the second scanning signal; the fifth compensation structure 500d located in the fifth conductive layer 80 is electrically connected to the first voltage line 65, i.e., the fifth compensation structure 500d is supplied with the first voltage. Moreover, the second compensation structure 200d and the third compensation structure 300d have an overlapping region with an increased area therebetween, and the fifth compensation structure 500d and the third compensation structure 300d have an overlapping region with a larger area therebetween. In this way, capacitances may be formed between the second compensation structure 200d and the third compensation structure 300d and between the fifth compensation structure 500d and the third compensation structure 300d, respectively, which are connected in parallel to form a second compensation capacitor C2, as shown in fig. 21B, which schematically illustrates the second compensation capacitor C2. That is, the second compensation capacitor C2 includes 2 capacitors connected in parallel, wherein one plate of one capacitor is the second compensation structure 200d, particularly the second main body portion 210d of the second compensation structure 200d, and the other plate is the third compensation structure 300d, particularly the third main body portion 310d of the third compensation structure 300 d; one plate of the other capacitor is the third compensation structure 300d, particularly the third body portion 310d of the third compensation structure 300d, and the other plate is the fifth compensation structure 500d, particularly the fifth body portion 510d of the fifth compensation structure 500d.

The capacitance of the second compensation capacitor C2 is related to the overlapping area between the second compensation structure 200d and the third compensation structure 300d and the overlapping area between the fifth compensation structure 500d and the third compensation structure 300d. As described above, the overlapping area between the second compensation structure 200d and the third compensation structure 300d and the overlapping area between the fifth compensation structure 500d and the third compensation structure 300d are designed to be large, and accordingly, the capacitance value of the second compensation capacitor C2 is also large. The second compensation capacitor C2 is a load applied to the second scanning signal line 61N. Since the capacitance value of the second compensation capacitor C2 is large, the load applied to the second scanning signal line 61N is also large, thereby achieving the purpose of compensating the load on the second scanning signal line.

In this embodiment, the second compensation capacitor C2 includes 2 capacitances connected in parallel, and accordingly, the capacitance value of the second compensation capacitor C2 can be further increased. In addition, the areas of the second and third compensation structures themselves may be appropriately reduced, thereby facilitating the realization of a display panel with a high PPI.

At least some embodiments of the present disclosure also provide a display panel including the display substrate as described above. For example, the display panel may be an OLED display panel.

Referring to fig. 1, at least some embodiments of the present disclosure also provide a display device. The display device may comprise a display substrate as described above.

The display means may comprise any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (e.g., a head-mounted device, an electronic apparel, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, or the like.

It should be understood that the display panel and the display device according to the embodiments of the present disclosure have all the features and advantages of the display substrate, and specific reference may be made to the above description, which is not repeated herein.

Although a few embodiments of the present general inventive concept have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims (31)

1. A display substrate comprising a display pixel region and a first virtual pixel region, the display substrate comprising;

a base substrate;

a plurality of sub-pixels disposed on the substrate and in the display pixel region, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, each sub-pixel including a pixel driving circuit, the pixel driving circuit including a driving transistor, a second transistor, and a fourth transistor, each of the driving transistor, the second transistor, and the fourth transistor including a gate electrode, a first electrode, and a second electrode, the first electrode of the second transistor being electrically connected to one of the first electrode and the second electrode of the driving transistor, the second electrode of the second transistor being electrically connected to the gate electrode of the driving transistor, the fourth transistor being for controlling writing of a data signal;

a plurality of dummy sub-pixel structures disposed on the substrate and located in the first dummy pixel region, at least one of the dummy sub-pixel structures including a first compensation capacitor and a second compensation capacitor; and

a first scanning signal line and a second scanning signal line provided on the substrate, the first scanning signal line being configured to supply a first scanning signal to a gate electrode of the fourth transistor, the second scanning signal line being configured to supply a second scanning signal to a gate electrode of the second transistor, the first scanning signal line and the second scanning signal line both extending through the display pixel region and the first dummy pixel region,

wherein the first scanning signal line is electrically connected to a gate of the fourth transistor of the pixel driving circuit of each sub-pixel in a row of sub-pixels, and the first scanning signal line is further electrically connected to the first compensation capacitor of the at least one dummy sub-pixel structure; and

the second scan signal line is electrically connected to a gate of the second transistor of the pixel driving circuit of each of the sub-pixels in a row of the sub-pixels, and is also electrically connected to the second compensation capacitor of the at least one dummy sub-pixel structure.

2. The display substrate of claim 1, wherein the display substrate comprises a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a third conductive layer disposed on the substrate, the first semiconductor layer, the first conductive layer, the second semiconductor layer, and the third conductive layer being sequentially disposed away from the substrate;

an active layer of the fourth transistor is located in the first semiconductor layer, and a gate of the fourth transistor is located in the first conductive layer;

an active layer of the second transistor is located in the second semiconductor layer, a gate of the second transistor comprises a bottom gate and a top gate, the bottom gate of the second transistor is located in the second conductive layer, and the top gate of the second transistor is located in the third conductive layer;

in the first dummy pixel region, the display substrate includes: a first compensation structure in the first conductive layer; a second compensation structure in the second conductive layer; and a third compensation structure in the third conductive layer.

3. The display substrate of claim 2, wherein the first compensation capacitor comprises at least a portion of the first compensation structure and at least a portion of the second compensation structure;

the second compensation capacitor includes at least a portion of the second compensation structure and at least a portion of the third compensation structure.

4. The display substrate of claim 2, wherein the first compensation capacitor comprises a first compensation sub-capacitor and a second compensation sub-capacitor, the first compensation sub-capacitor and the second compensation sub-capacitor being connected in parallel, the first compensation sub-capacitor comprising at least a portion of the first compensation structure and at least a portion of the second compensation structure; and/or the presence of a gas in the gas,

the second compensation capacitor includes a third compensation sub-capacitor and a fourth compensation sub-capacitor, the third compensation sub-capacitor and the fourth compensation sub-capacitor being connected in parallel, the third compensation sub-capacitor including at least a portion of the second compensation structure and at least a portion of the third compensation structure.

5. The display substrate according to claim 3, wherein the first scan signal line is in the first conductive layer, and the first compensation structure is electrically connected to the first scan signal line.

6. The display substrate according to claim 4, wherein the first scan signal line is in the first conductive layer, and the first compensation structure is electrically connected to the first scan signal line.

7. The display substrate of claim 5, wherein the display substrate further comprises a first voltage line disposed on the substrate for transmitting a first voltage;

the second compensation structure is electrically connected to the first voltage line.

8. The display substrate of claim 6, wherein the display substrate further comprises a first voltage line disposed on the substrate for transmitting a first voltage;

the second compensation structure is electrically connected to the first voltage line.

9. A display substrate according to claim 7 or 8, wherein an orthographic projection of the first compensation structure on the substrate at least partially overlaps with an orthographic projection of the second compensation structure on the substrate.

10. The display substrate according to claim 9, wherein the second scan signal line comprises a first sub-scan signal line in the second conductive layer and a second sub-scan signal line in the third conductive layer;

the third compensation structure is electrically connected with the second scanning signal line.

11. The display substrate of claim 10, wherein an orthographic projection of the third compensation structure on the substrate at least partially overlaps with an orthographic projection of the second compensation structure on the substrate.

12. A display substrate according to claim 9, wherein the first compensation structure comprises a first body portion and the second compensation structure comprises a second body portion, an orthographic projection of the second body portion on the substrate overlaying an orthographic projection of the first body portion on the substrate.

13. A display substrate according to claim 12, wherein the third compensation structure comprises a third body portion, an orthographic projection of the second body portion on the substrate overlaying an orthographic projection of the third body portion on the substrate.

14. The display substrate according to claim 13, wherein an area of an overlapping region of the first and second main body portions is 70% or more of an area of an orthogonal projection of the second main body portion on the substrate; and/or the presence of a gas in the atmosphere,

the area of the overlapping region of the third main body portion and the second main body portion is 70% or more of the area of the orthographic projection of the second main body portion on the substrate.

15. The display substrate according to claim 14, wherein the first scanning signal line extends in a first direction, and a ratio of a dimension in a second direction of an orthogonal projection of the first main body portion on the substrate to a dimension in the second direction of an orthogonal projection of the first scanning signal line on the substrate is 5 or more; and/or the presence of a gas in the atmosphere,

the second scanning signal line extends along a first direction, and the ratio of the size of the orthographic projection of the third main body part on the substrate along the second direction to the size of the orthographic projection of the second scanning signal line on the substrate along the second direction is greater than or equal to 5.

16. The display substrate of claim 8, wherein the display substrate comprises: the fourth conducting layer is positioned on one side, far away from the substrate, of the third conducting layer, and the fifth conducting layer is positioned on one side, far away from the substrate, of the fourth conducting layer;

the first voltage line is located in the fifth conductive layer, the display substrate includes a compensation connection portion located in the fourth conductive layer, and the second compensation structure is electrically connected to the first voltage line through the compensation connection portion.

17. The display substrate of claim 16, wherein the display substrate further comprises a fifth compensation structure in the fifth conductive layer, the fifth compensation structure electrically connected to the first voltage line; and

the fourth compensation sub-capacitor includes at least a portion of the third compensation structure and at least a portion of the fifth compensation structure.

18. The display substrate of claim 17, wherein an orthographic projection of the third compensation structure on the substrate at least partially overlaps an orthographic projection of the fifth compensation structure on the substrate.

19. A display substrate according to claim 18, wherein the third compensation structure comprises a third body portion and the fifth compensation structure comprises a fifth body portion, an orthographic projection of the third body portion on the substrate overlaying an orthographic projection of the fifth body portion on the substrate.

20. The display substrate of any of claims 4, 17-19, wherein the display substrate further comprises a sixth conductive layer on a side of the first semiconductor layer proximate to the substrate;

the display substrate further comprises a fourth compensation structure located in the sixth conductive layer, and an orthographic projection of the first compensation structure on the substrate is at least partially overlapped with an orthographic projection of the fourth compensation structure on the substrate.

21. The display substrate of claim 20, wherein the second compensation sub-capacitor comprises at least a portion of the first compensation structure and at least a portion of the fourth compensation structure.

22. A display substrate according to claim 21, wherein the first compensation structure comprises a first body portion and the fourth compensation structure comprises a fourth body portion, an orthographic projection of the first body portion on the substrate overlaying an orthographic projection of the fourth body portion on the substrate.

23. The display substrate of claim 19, wherein a dimension of the fifth body portion of the fifth compensation structure in the first direction is greater than a dimension of the first voltage line in the first direction.

24. The display substrate of claim 23, wherein a ratio of a dimension of the fifth main body portion of the fifth compensation structure in the first direction to a dimension of the first voltage line in the first direction is greater than or equal to 3.

25. A display substrate according to claim 19, 23 or 24, wherein in a2 adjacent virtual sub-pixel structure, 2 of the fifth body portions are connected to each other, and an orthographic projection of the 2 connected fifth body portions on the substrate is in a rectangular shape.

26. A display substrate according to any one of claims 1 to 4, wherein for 2 sub-pixels adjacent in a first direction, the orthographic projections of their pixel drive circuits on the substrate are in an axisymmetric relationship with respect to a first axis of symmetry extending in a second direction.

27. A display substrate according to any one of claims 1 to 4, wherein for 2 virtual sub-pixel structures adjacent in a first direction, the orthographic projections of the 2 virtual sub-pixel structures on the substrate are in an axisymmetric relationship with respect to a second axis of symmetry, the second axis of symmetry extending along a second direction.

28. The display substrate according to any one of claims 1 to 4, wherein at least one of the first scanning signal line and the second scanning signal line includes a first compensation signal line and a second compensation signal line, the first compensation signal line electrically connecting the plurality of sub-pixels in one row of sub-pixels and the at least one first dummy sub-pixel structure, the second compensation signal line electrically connecting the plurality of sub-pixels in another row of sub-pixels and the at least one first dummy sub-pixel structure; and

the number of sub-pixels to which the first compensation signal lines are electrically connected is less than the number of sub-pixels to which the second compensation signal lines are electrically connected, and the number of first dummy sub-pixel structures to which the first compensation signal lines are electrically connected is greater than the number of first dummy sub-pixel structures to which the second compensation signal lines are electrically connected.

29. The display substrate according to any one of claims 1 to 4, wherein the first scan signal line and the second scan signal line each extend in the first direction; and

in the first virtual pixel region, the plurality of virtual sub-pixel structures are arranged along the first direction and the second direction, and the number of virtual sub-pixel structures located in the same row increases and then decreases along the second direction.

30. A display panel comprising the display substrate of any one of claims 1-29.

31. A display device comprising the display substrate of any one of claims 1-29 or the display panel of claim 30.

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