CN217847954U - Packaging structure - Google Patents

Abstract

An embodiment of the present disclosure provides a package structure, including: a package substrate and first and second dies disposed thereon, the first and second dies each having first and second edges opposing each other in a first direction and extending in a second direction, and third and fourth edges opposing each other in the second direction and extending in the first direction; the first die and the second die respectively comprise a transceiving interface area which is arranged at the first edge and provided with a receiving interface and a transmitting interface which are alternately arranged, the parts of the first edges of the first die and the second die, which are provided with the transceiving interface areas, face each other, in the second direction, the part of the first die, which is not provided with the transceiving interface areas, extends to the side, far away from the fourth edge, of the third edge of the second die, the part of the second die, which is not provided with the transceiving interface areas, extends to the side, far away from the fourth edge, of the third edge of the first die, and the receiving interfaces in the transceiving interface areas of the first die and the second die are electrically connected with the corresponding transmitting interfaces.

Description

Packaging structure

Technical Field

Embodiments of the present disclosure relate to a package structure.

Background

With the development of semiconductor technology, moore's law develops more and more slowly, and the number of transistors that can be integrated on a chip is multiplied more and more difficult. It is widely believed in the industry that there are two directions to the development of semiconductor technology, one to continue moore's law and the other to extend moore's law. Along the technical route of developing along the direction of expanding moore's law, a plurality of functional chips can be integrated in one system by using a semiconductor packaging technology, but how to realize high performance, multiple functions and system miniaturization of a large-scale complex chip system is still a problem to be solved in the industry.

SUMMERY OF THE UTILITY MODEL

There is provided in accordance with at least one embodiment of the present disclosure a package structure including: a package substrate; and a first die and a second die disposed on the package substrate, the first die and the second die each having a first edge and a second edge opposing each other in a first direction and extending in a second direction, and a third edge and a fourth edge opposing each other in the second direction and extending in the first direction, the first direction and the second direction intersecting each other; wherein the first die and the second die each include a transceiver interface region disposed at the first edge and including receiving interfaces and transmitting interfaces alternately disposed along the first edge, a portion of the first edge of the first die where the transceiver interface region is disposed and a portion of the first edge of the second die where the transceiver interface region is disposed face each other in the first direction, in the second direction, a portion of the first edge of the first die where the transceiver interface region is not disposed extends to a side of the third edge of the second die away from the fourth edge of the second die, a portion of the first edge of the second die where the transceiver interface region is not disposed extends to a side of the third edge of the first die away from the fourth edge of the first die, a receiving interface within the transceiver interface region of the first die is electrically connected to a transmitting interface within the transceiver region of the second die, and the transmitting interface within the transceiver interface region of the first die is electrically connected to the receiving interface within the transceiver region of the second die.

In some examples, the distance between the transceiver interface region and the third edge is less than the distance between the transceiver interface region and the fourth edge.

In some examples, the package structure further comprises: a first memory die disposed on a side of the third edge of the first die away from the fourth edge in the second direction, the first memory die at least partially overlapping the second die in the first direction; and a second memory die disposed on a side of the third edge of the second die away from the fourth edge in the second direction, the second memory die at least partially overlapping the first die in the first direction.

In some examples, the transmit interface and the receive interface of the first die and the second die that are connected corresponding to each other overlap in the first direction.

In some examples, the sidewalls of the transmitting interface opposite in the second direction and the sidewalls of the receiving interface correspondingly connected opposite in the second direction are aligned with each other in the first direction, respectively.

In some examples, the sidewalls of the transmitting interface opposite in the second direction and the sidewalls of the receiving interface correspondingly connected opposite in the second direction are offset from each other in the second direction, respectively.

In some examples, the transmit interface and the correspondingly connected receive interface do not overlap in the first direction, but are adjacent to each other in the second direction.

In some examples, the package structure further includes at least one package connection member disposed on the package substrate, and the first die and the second die are disposed on a side of the at least one package connection member away from the package substrate, wherein the at least one package connection member or the package substrate includes a first conductive trace electrically connecting the transmission interface of the first die and the reception interface of the second die, and a second conductive trace electrically connecting the reception interface of the first die and the transmission interface of the second die.

In some examples, portions of the first and second conductive traces that extend parallel to the major surface of the package substrate extend in the first direction parallel to each other.

In some examples, portions of the first and second conductive traces that extend parallel to a major surface of the package substrate extend parallel to each other in a third direction that is parallel to the major surface of the package substrate and that intersects the first and second directions.

In some examples, the at least one package connecting member is one package connecting member, and the first and second conductive traces are disposed in the one package connecting member for electrical connection of the first die and the second die.

In some examples, the first die and the second die are both system chips.

In some examples, the package structure further comprises: the first memory die and the second memory die are arranged on one side of the package connecting component far away from the package substrate, wherein the package connecting component comprises a first interconnection area, a second interconnection area and a third interconnection area, the first interconnection area is used for electrically connecting the first die with the first memory die, the second interconnection area is used for electrically connecting the second die with the second memory die, and the first conductive routing and the second conductive routing are arranged in the third interconnection area of the package connecting component.

In some examples, the at least one package connection member includes a first package connection member and a second package connection member, the first package connection member is located between the first die and the package substrate, and the second package connection member is located between the second die and the package substrate, wherein the first conductive trace and the second conductive trace are disposed in the package substrate, and the corresponding transmission interface and the reception interface in the first die and the second die are connected to each other through the first package connection member, the second package connection member, and the package substrate.

In some examples, the package structure further comprises: the first package connecting member comprises a first interconnection area used for electrically connecting the first die and the first memory die and a first additional routing used for connecting the first conductive routing of the first die and the package substrate, and the second package connecting member comprises a second interconnection area used for electrically connecting the second die and the second memory die and a second additional routing used for connecting the second die and the second conductive routing of the package substrate.

In some examples, the at least one package connection member includes an interposer, a rewiring structure, or a connection structure with a bridged die.

In some examples, no transceiver interface region is disposed at the second edge of the first die and the second edge of the second die.

In some examples, the package structure further includes at least one of a first dummy die disposed on the side of the third edge of the first die away from the fourth edge in the second direction and overlapping the first memory die in the first direction; the second dummy die is disposed on the side of the third edge of the second die away from the fourth edge in the second direction and overlaps the second memory die in the first direction.

In some examples, the second die has the same orientation as the first die after being rotated 180 degrees in a plane in which the first direction and the second direction lie, the same orientation including the first edge to the fourth edge of the second die being oriented the same as the first edge to the fourth edge of the first die after being rotated 180 degrees in the plane.

In some examples, the first die and the second die are dies having substantially the same structure.

The packaging structure according to the embodiment of the disclosure can shorten the interconnection length between the dies and improve the function density.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1A illustrates a schematic top view of a package structure according to some embodiments of the present disclosure.

Fig. 1B illustrates a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure.

Fig. 2A-2D illustrate enlarged schematic views of region P in fig. 1A according to some embodiments of the present disclosure.

Fig. 3A illustrates a schematic top view of a package structure according to some embodiments of the present disclosure.

Fig. 3B illustrates a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure.

Fig. 4A-4D illustrate enlarged schematic views of region P' in fig. 3A according to some embodiments of the present disclosure.

Fig. 5A-5C and 6A-6C illustrate schematic cross-sectional views of package structures according to some embodiments of the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Various embodiments of the present disclosure integrate a first die and a second die within the same package structure using semiconductor packaging techniques, and the first die and the second die may both be system on chips (socs) and may be connected to each other through package connection means (e.g., interposer, redistribution structures, connection structures including bridge dies), or may be connected to each other through package connection means and package substrates. The first die and the second die may be formed using substantially the same semiconductor process and may include substantially the same structures, e.g., each including a transceiver interface region disposed at a first edge thereof. The first die and the second die may be arranged in a rotationally symmetric configuration, and the orientation of the second die may be substantially the same as the orientation of the first die rotated 180 degrees in a horizontal direction parallel to the major surfaces of the dies. The arrangement can enable the transceiving interface areas of the first edges of the first die and the second die to correspond to each other, and minimize connection paths between the transceiving interface areas, namely, shorten interconnection length and improve function density. Further, in some embodiments, the first die and the second die are included in the first die group and the second die group, respectively, and the first memory die and the second memory die connected to the first die and the second die by the package connecting means, respectively, may be further included in the first die group and the second die group, the first die group and the second die group may be arranged in a rotationally symmetric structure, and the orientation of the second die group may be the same as that of the first die group after being rotated 180 degrees in a horizontal direction parallel to the main surfaces of the dies, so that the warpage problem of a package structure (e.g., an oversized chip system) may be solved or reduced, thereby optimizing the package structure in terms of performance, function, and area.

Fig. 1A and 1B illustratebase:Sub>A schematic top view andbase:Sub>A schematic cross-sectional view, respectively, ofbase:Sub>A package structure according to some embodiments of the present disclosure, where fig. 1B isbase:Sub>A cross-sectional view taken along linebase:Sub>A-base:Sub>A' of fig. 1A.

Referring to fig. 1A and 1B, in some embodiments, the encapsulation structure 500 may include first and second die groups C1 and C2, an encapsulation connection member 200, and an encapsulation substrate 300. The set of tubes may also be referred to as a core pellet (chiplet). The packing connecting member 200 is disposed between the first and second tube core groups C1 and C2 and the packing connecting member 200, i.e., the first and second tube core groups C1 and C2 are located at one side of the packing connecting member 200 away from the packing substrate 300. In some embodiments, the package connecting means 200 provides electrical connection between the plurality of dies in the first die group C1, electrical connection between the plurality of dies in the second die group C2, electrical connection between the first and second die groups C1 and C2, and electrical connection between the first and second die groups C1 and C2 and the package substrate 300, and the package substrate 300 also provides electrical connection between the first and second die groups C1 and C2 and an external member (e.g., a printed circuit board).

In some embodiments, the encapsulation structure 500 further includes an encapsulation layer 80, and the encapsulation layer 80 is disposed on the same side of the encapsulation connecting member 200 as the first and second die groups C1 and C2, i.e., on the side of the encapsulation connecting member 200 away from the encapsulation substrate 300. The encapsulating layer 80 surrounds and encapsulates at least the sidewalls of the first and second groups C1 and C2 of the tubes, and in some embodiments, may also extend to cover the surfaces of the first and second groups C1 and C2 of the tubes distal from the encapsulating connecting member 200. The encapsulation layer 80 may include a molding compound (EMC), such as an epoxy molding compound (epoxy molding compound), but the disclosure is not limited thereto.

In some embodiments, the first and second groups S1, S2 of tubes are arranged side-by-side along direction D1, and may each comprise substantially the same components and structures; the first and second groups S1 and S2 may be arranged in a rotationally symmetric structure, and the orientation of the second group S2 may be substantially the same as that of the structure after the first group S1 is rotated 180 degrees in a direction parallel to the major surface of the package substrate 300.

For example, first die group S1 includes die 100a, die 50a, and die 52a. The dies 100a, 50a, 52a may each be any suitable type of die. For example, die 100 may be a system on chip (SoC) and include logic and input-output circuits; die 50a and die 52a are, for example, memory dies, and in some examples, high Bandwidth Memory (HBM) chips. However, the disclosure is not so limited and the dies 50a and 52a may be other types of memory dies as well.

In some embodiments, the dies 100a, 50a, 52b in the first die group S1 are connected to each other by the package connection means 200. For example, the package connecting means 200 includes a first interconnection region therein to provide electrical connection between the die 100a and the dies 50a and 52a in the first die group C1. For example, a plurality of conductive traces 201a are included in the first interconnect region, and the die 100a is electrically connected to the dies 50a and 52a through the conductive traces 201 a. Die 100a may include a connection region 101a and a connection region 102a for making connections to die 50a and 52a. In some embodiments, the connection zones 101a and 102a may be or include physical layers (PHYs) that are communicatively coupled to the dies 50a and 52a, respectively, and may each include functional circuitry for transmitting signals/data.

In some embodiments, die 100a has edges S1 and S2 extending along direction D2 opposite and substantially parallel to each other in direction D1 and edges S3 and S4 extending along direction D1 opposite and substantially parallel to each other in direction D2; the direction D1 and the direction D2 intersect each other, and are, for example, perpendicular to each other. The edges S1-S4 of the die 100a may also be referred to as its first, second, third, and fourth edges, respectively, and the edges of the die may also be referred to as the sides of the die. In some embodiments, edge S3 and edges S1, S2 intersect each other and are, for example, perpendicular, and edge S4 and edges S1, S2 intersect each other and are, for example, perpendicular.

In some embodiments, the connection areas 101a and 102a of the die 100a are disposed at the edge S3 and/or at a position near the edge S3, and the dies 50a and 52a are arranged on the side of the die 100a near the edge S3 thereof in the direction D2, i.e., on the side of the edge S3 of the die 100a away from the edge S4, and may be disposed side by side along the direction D1 at positions corresponding to the connection areas 101a and 102a. The dies 100a, 50a, and 50a are spaced apart from each other, and portions of the encapsulation layer 80 fill in the gaps between the dies 100a, 50a, and 50 a.

Referring to fig. 1A, in some embodiments, a die 100a includes one or more transceiver elements (transceiver elements), such as a die-to-die (D2D) transceiver, disposed in a transceiver interface region. Each transceiver element comprises a transmitting interface for transmitting signals and a receiving interface for receiving signals, and the transmitting interface and the receiving interface may be alternately arranged in the transceiver interface region along the direction D2. For example, the die 100a includes transceiver elements 106a1 and 106a2 disposed in a transceiver interface region 106 a. The transceiving element 106a1 includes a transmission interface Ta1 and a reception interface Ra1; the transceiving element 106a2 includes a transmission interface Ta2 and a reception interface Ra2.

In some embodiments, the transceiving elements 106a1 and 106a2 are disposed at the edge S1 and/or near the edge S1 of the die 100a, and are disposed side-by-side spaced apart from each other in the direction D2. That is, the transceiver interface region 106a and the connection regions 101a, 102a are disposed near and/or at two edges of the die 100a that intersect (e.g., are perpendicular) to each other.

With continued reference to fig. 1A, in some embodiments, the first die group C1 may also optionally include a dummy die (dummy die) 60a, for example, disposed along direction D2 on a side of die 100a proximate to edge S3 thereof (i.e., a side of edge S3 of die 100a distal from edge S4), and disposed alongside dies 50a and 52a and spaced apart from each other in direction D1. In some embodiments, the dummy die 60a may be or include a filler die, although the disclosure is not so limited. For example, the die 50a may be disposed between the dummy die 60a and the die 52a in the direction D1, but the disclosure is not limited thereto. It should be noted that although the dummy die 60a is shown to be disposed on the side of the dies 50a and 52a away from the die 100b, i.e., the dummy die 60a, the die 50a, and the die 52a are arranged in the order from left to right in the figure, the arrangement order of the dummy die 60a and the dies 50a and 52a shown in the figure is merely illustrative, and the disclosure is not limited thereto. In other embodiments, dummy die 60a may also be arranged on the side of dies 50a and 52a that is closer to die 100b, i.e., die 50a, die 52a, and dummy die 60a may be arranged from left to right in the figure; alternatively, dummy die 60a may be arranged between die 50a and die 52a or in any other suitable location. The locations of the dies 50a and 52a and the dummy die 60a may be adjusted based on product requirements and are not limited by this disclosure.

In some embodiments, the overall dimension (e.g., width) of dummy die 60a and dies 50a and 52a in direction D1 is substantially equal to the dimension (e.g., width) of die 100a in direction D1. Herein, the overall width of the plurality of dies in a certain direction refers to the sum of the width of each of the plurality of dies in the direction and the width of the gap between the plurality of dies in the direction; that is, the overall width of the dummy die 60a and the dies 50a and 52a in the direction D1 refers to the sum of the respective widths of the dies 50a, 52a, and the dummy die 60a, and the width of the gap between the die 50a and the die 52a, and the width of the gap between the dummy die 60a and the die 50 a. In some embodiments, the dummy die 60a has a first sidewall and a second sidewall opposite each other in the direction D1, wherein the first sidewall of the dummy die 60a faces the die 50a and the second sidewall is substantially aligned with the edge S2 of the die 100a in the direction D2; die 52a has first and second sidewalls opposite each other in direction D1, where the first sidewall of die 52a faces die 50a and its second sidewall is substantially aligned with edge S1 of die 100a in direction D2. However, the disclosure is not so limited and the respective sidewalls of dummy die 60a and die 52a may also be offset from the edge of die 100a in direction D1. In the case where the overall width of the dies 50a and 52a in the direction D1 is smaller than the width of the die 100a in the direction D1, the warpage of the package structure can be effectively reduced or avoided by providing the dummy die 60 a. The dummy die 60a may comprise any suitable material, such as silicon, for example, although the disclosure is not limited thereto.

It should be noted that the first die group C1 optionally includes dummy die 60a, and in some embodiments dummy die 60a may be omitted. For example, in some examples, the overall width of dies 50a and 52a in direction D1 (i.e., the sum of the respective widths of dies 50a and 52a in direction D1 and the width of the gap between dies 50a and 52 a) is approximately equal to the width of die 100a in direction D1. In this case, the sidewalls of dies 50a and 52a that are distant from each other in direction D1 may be generally aligned with the opposite edges S2 and S1 of die 100a in direction D1, respectively. Specifically, die 50a has a first sidewall facing die 52a and a second sidewall opposite the first sidewall in direction D1 and distal die 52a, which may be substantially aligned with edge S2 of die 100a in direction D2; die 52a has a first sidewall facing die 50a and a second sidewall opposite the first sidewall and distal die 50a in direction D1, which may be substantially aligned with edge S1 of die 100a in direction D2.

With continued reference to fig. 1A, in some embodiments, the second group of die C2 has a similar or substantially identical structure to the first group of die C1. For example, second die group S2 includes die 100b, die 50b, and die 52b, and the types of the dies are similar to the types of dies described above with reference to first die group C1. Die 100b is a system chip, for example, and die 50b and 52b are memory dies, such as HBM dies, for example.

In some embodiments, the dies 100b, 50b, and 52b in the second die group C2 are also connected to each other by the package connecting structure 200, for example, a second interconnection region is included in the package connecting structure 200 to provide electrical connection between the dies 100b, 50b, and 52b in the second die group C2. For example, a plurality of conductive traces 201b are included in the second interconnect region, and the die 100b is electrically connected to the dies 50b and 52b by conductive lines 201 b. The first interconnect region and the second interconnect region are disposed in the interposer 200 and spaced apart from each other.

Die 100b may include a connection region 101b and a connection region 102b for making connections to die 50a and 52a. In some embodiments, the connection zones 101b and 102b may be or include physical layers (PHYs) communicatively connected to the dies 50b and 52b, respectively, and may each include functional circuitry for transmitting signals and/or data.

Similar to die 100a, die 100b also has edges S1 'and S2' extending along direction D2 opposite and substantially parallel to each other in direction D1, and edges S3 'and S4' extending along direction D1 opposite and substantially parallel to each other in direction D2; edges S1 'through S4' of die 100b may also be referred to as first, second, third, and fourth edges thereof, respectively. The relative position relationship of the edges S1 'to S4' is similar to that of the edges S1 to S4, and is not described herein again.

In some embodiments, the connection regions 101b and 102b of the die 100b are disposed at the edge S3' and/or at a position near the edge S3', the dies 50b and 52b are arranged on the side of the die 100b near the edge S3' thereof (i.e., the side of the edge S3' of the die 100b away from the edge S4 ') in the direction D2, and may be disposed side by side at positions corresponding to the connection regions 101b and 102b along the direction D2. The dies 100b, 50b, and 50b are spaced apart from each other, and portions of the encapsulation layer 80 fill in the gaps between the dies 100b, 50b, and 50 b.

In some embodiments, the die 100b also includes one or more transceiver elements (transceiver elements) disposed in a transceiver interface region, such as a die-to-die (D2D) transceiver. Each transceiver element comprises a transmitting interface for transmitting signals and a receiving interface for receiving signals, and the transmitting interface and the receiving interface may be alternately arranged in the transceiver interface region along the direction D2. For example, the die 100b includes transceiver elements 106b1 and 106b2 disposed in a transceiver interface region 106 b. The transceiving element 106b1 comprises a transmitting interface Tb1 and a receiving interface Rb1; the transceiving element 106b2 comprises a transmission interface Tb2 and a reception interface Rb2.

In some embodiments, the transceiver elements 106b1 and 106b2 are disposed at the edge S1 'and/or near the edge S2' of the die 100b and are disposed side-by-side spaced apart from each other in the direction D2. That is, the transceiving elements 106b1 and 106b2 and the connection regions 101b and 102b are disposed near and/or at both edges of the die 100b that intersect (e.g., are perpendicular) to each other.

With continued reference to fig. 1A, similar to first die group C1, second die group C2 may also optionally include dummy die 60b, dummy die 60b being disposed, for example, on a side of die 100b proximate edge S3' thereof along direction D2, and being disposed alongside and spaced apart from dies 50b and 52b in direction D1. For example, die 50b may be disposed between dummy die 60b and die 52b in direction D1. In some embodiments, the overall dimension (e.g., width) of dummy die 60b and dies 50b and 52b in direction D1 is substantially equal to the dimension (e.g., width) of die 100b in direction D1. In some embodiments, dummy die 60b has a first sidewall and a second sidewall opposite each other in direction D1, wherein the first sidewall of dummy die 60b faces die 50b and the second sidewall is substantially aligned with edge S2' of die 100b in direction D2; die 52b has a first sidewall and a second sidewall opposite each other in direction D1, wherein the first sidewall of die 52b faces die 50b and the second sidewall thereof is substantially aligned with edge S1' of die 100b in direction D2.

It should be noted that the second die group C2 is optional including the dummy die 60b, and in some embodiments, the dummy die 60a may be omitted. For example, in some examples, the overall width of dies 50b and 52b in direction D1 (i.e., the sum of the respective widths of dies 50b and 52b in direction D1 and the width of the gap between dies 50b and 52 b) is approximately equal to the width of die 100b in direction D1. In this case, the sidewalls of dies 50b and 52b that are away from each other in direction D1 may be generally aligned with opposing edges S2 and S1 of die 100a in direction D1, respectively. The positional relationship of dies 50b and 52b and die 100b relative to each other is similar to that described above with reference to first die group C1.

In some embodiments, die 100a and die 100b have substantially the same structure and components, and may be, for example, cut from the same wafer (wafer) and subjected to substantially the same semiconductor manufacturing process. Thus, die 100a and die 100b may have substantially the same structure. In some embodiments, the transceiver interface regions of both die 100a and die 100b are disposed at a first edge thereof and do not have a transceiver interface region at a second edge opposite the first edge, although the disclosure is not so limited.

In some embodiments, the first and second groups of dies C1 and C2 may be electrically connected to each other by the encapsulation connection means 200, e.g., the encapsulation connection means 200 includes a third interconnection zone to provide an electrical connection (or may be referred to as a D2D connection) between the dies 100a in the first group of dies C2 and the dies 100b in the second group of dies C2 (e.g., between corresponding launch and receive interfaces in the receive interface zones 106a and 106 b). For example, the third interconnect region includes a plurality of conductive traces 201c therein, and the die 100a is electrically connected to the die 100b by the conductive traces 201 c. In some embodiments, the first to third interconnection regions are disposed in the package connecting member 200 and spaced apart from each other, e.g., electrically isolated from each other.

In some embodiments, the encapsulating layer 80 encapsulates and surrounds the sidewalls of each of the dies of the first and second die groups C1 and C2, and an orthogonal projection of the first and second die groups C1 and C2 on the encapsulation connecting member 200 in the direction D3 perpendicular to the major surface of the encapsulation connecting member 200 is located within an orthogonal projection range of the encapsulating layer 80 on the encapsulation connecting member 200 in the direction D3 perpendicular to the major surface of the encapsulation connecting member 200. In some embodiments, encapsulation layer 80 has edges E1 and E2 extending along direction D2 opposite and substantially parallel to each other in direction D1, and edges E3 and E4 extending along direction D1 opposite and substantially parallel to each other in direction D2, where edge E4 intersects with edges E2 and E1 and is, for example, perpendicular to each other, and edge E3 intersects with edges E2 and E1 and is, for example, perpendicular to each other. In some embodiments, edges E1-E4 may be referred to as first, second, third, and fourth encapsulant layer edges, respectively.

In some embodiments, the first and second die groups C1 and C2 are substantially identical in structure, the number and types of dies included therein, and the relative positional relationship between the respective dies. In some embodiments, the second group of dies C2 is substantially the same orientation as the first group of dies C1 after rotating 180 ° in either a clockwise or counterclockwise direction on a plane in which the directions D1 and D2 lie. That is, the first and second die groups C1 and C2 are disposed in different orientations, for example, in the plane of the direction D1 and the direction D2, the dies 50a and 52a in the first die group C1 are disposed below the die 100a in the direction D2, and the dies 50a and 52a in the second die group C2 are disposed above the die 100b in the plan view.

By so arranging the first die group C1 and the second die group C2, the transceiving interface region 106a of the die 100a and the transceiving interface region 106b of the die 100b can be made to face each other, and the transmitting interface and the receiving interface in the transceiving interface region 106a can be in positions corresponding to the receiving interface and the transmitting interface in the die 100b, respectively, and the interconnection length (e.g., the path of conductive traces) of the transceiving interface region 106a and the transceiving interface region 106b is minimized. Furthermore, by providing a transceiver interface area at one edge of each die, interconnection between different dies can be achieved. In some embodiments, the distance of the transceiver interface region of each of the dies 100a and 100b from the third edge is less than the distance of the transceiver interface region from the fourth edge; the portion of the die 100a provided with the transceiving interface region 106a and the portion of the die 100b provided with the transceiving interface region 106b overlap each other in the direction D1, and the portion of the die 100a not provided with the transceiving interface region and the portion of the die 100b not provided with the transceiving interface region do not overlap in the direction D1; in other words, orthogonal projections of the portion of the die 100a provided with the transceiver interface region 106a and the portion of the die 100b provided with the transceiver interface region 106b in the direction D1 on a reference plane (e.g., the edge E1 or E2 of the encapsulation layer 80) extending in the direction D2 coincide with each other (e.g., completely coincide with or partially coincide with each other); the orthogonal projections of the portion of die 100a not provided with the transceiving interface region and the portion of die 100b not provided with the transceiving interface region on the edge E1 or E2 of encapsulation layer 80 in direction D1 do not coincide with each other. In some embodiments, the portion of the die 100a not provided with the transceiver interface region extends in the direction D2 toward the edge E4 of the encapsulation layer 80 to a side of the third edge S3 'of the die 100b away from the fourth edge S4', and may overlap the dies 50b, 52b and the dummy die 60b in the direction D1; the portion of the die 100b not provided with the transceiver interface region extends in direction D2 toward the edge E3 of the encapsulation layer 80 to a side of the third edge S3 of the die 100a away from the fourth edge S4, and may overlap the dies 50a, 52a and the dummy die 60a in direction D1. In other words, the portion of the die 100a not provided with the transceiver interface region and the orthogonal projections of the dies 50b, 52b and the dummy die 60b in the direction D1 on the edge E1 or E2 of the encapsulation layer 80 coincide with each other (e.g., completely coincide or partially coincide); the portion of the die 100b not provided with the transceiver interface region and the orthogonal projections of the dies 50a, 52a and the dummy die 60a in the direction D1 on the edge E1 or E2 of the encapsulation layer 80 coincide with each other (e.g., completely coincide or partially coincide).

Herein, that a plurality of members overlap each other in a certain direction (e.g., a first direction) means that orthogonal projections of the plurality of members on a same reference plane along the direction coincide with each other (completely coincide or partially coincide), wherein the reference plane is perpendicular to the direction; also, the overlapping of the plurality of members with each other does not limit whether the plurality of members contact or are connected with each other, and may include a case where the plurality of members contact each other, are physically separated from each other without contacting, are connected or are not connected with each other, and the like. For example, the overlapping of the die 100a and the die 100b in the first direction D1 may include a case where the dies 100a and 100b contact each other, and may also include a case where the dies 100a and 100b are physically separated from each other without contacting.

In some embodiments, in die 100a, the transceiver interface region 106a including transceiver elements 106a1 and 106a2 is disposed at edge S1, and in direction D2, transceiver element 106a1 is closer to edge S4 than transceiver element 106a2, and transceiver element 106a2 is closer to edge S3 than transceiver element 106a 1; in some embodiments, in the direction D2, the transceiving element 106a1 has a distance D1 from the edge S4, the transceiving element 106a2 has a distance D2 from the edge S3, and the transceiving element 106a1 has a distance D3 from the transceiving element 106a2. In this embodiment, the distance between the transceiving interface region 106a and the edge S4 in the direction D2 is the distance D1 between the transceiving element 106a1 and the edge S4 in the direction D2, and the distance between the transceiving interface region 106a and the edge S3 in the direction D2 is the distance D2 between the transceiving element 106a2 and the edge S3 in the direction D2. In some embodiments, distance d1 is greater than distance d2.

In die 100b, a transceiver interface region 106b including transceiver elements 106b1 and 106b2 is disposed at edge S1', and in direction D2, transceiver element 106b1 is closer to edge S4' than transceiver element 106b2, and transceiver element 106b2 is closer to edge S3' than transceiver element 106b 1; in some embodiments, in the direction D2, there is a distance D1' between the transceiving element 106b1 and the edge S4', a distance D2' between the transceiving element 106b2 and the edge S3', and a distance D3' between the transceiving element 106b1 and the transceiving element 106b2. In this embodiment, the distance between the transceiving interface region 106b and the edge S4 'in the direction D2 is a distance D1' between the transceiving element 106b1 and the edge S4 'in the direction D2, and the distance between the transceiving interface region 106b and the edge S3' in the direction D2 is a distance D2 'between the transceiving element 106b2 and the edge S3' in the direction D2. In some embodiments, distance d1 'is greater than distance d2'. In some embodiments, the distance d1 is substantially equal to the distance d1'; distance d2 is substantially equal to distance d2'; the distance d3 is substantially equal to the distance d3'. That is, the difference between the distances d1 and d2 is substantially equal to the difference between the distances d1 'and d2'. In some embodiments, the distances d1-d3, d1'-d3' may also be referred to as pitches. Herein, the distance of the transceiving element from the die edge refers to the distance of the sidewall of the transceiving element facing the die edge from the die edge; the distance between the transceiver component and the transceiver component refers to the distance between the sidewalls of the transceiver component that face each other.

In some embodiments where the second die group C2 is substantially identical to the first die group C1 in orientation after being rotated 180 deg., the dies 100a and 100b are also substantially rotationally symmetric structures, i.e., the dies 100a and 100b are in different orientations, and the die 100b may be substantially identical to the structure after the die 100a is rotated 180 deg. in a plane including directions D1 and D2. For example, the edge S3 of the die 100a of the first die group S1, where the connection regions 101a and 102a are disposed, faces the edge E3 of the encapsulation layer 80, and the dies 50a, 52a and the dummy die 60a are disposed between the edge S3 of the die 100a and the edge E3 of the encapsulation layer 80; edge S4 of die 100a faces edge E4 of encapsulation layer 80; in contrast, the edge S3 'of the die 100b of the second group S2, where the connection regions 101b and 102b are provided, faces the edge E4 of the encapsulation layer 80, and the dies 50b, 52b and the dummy die 60b are disposed between the edge S3' of the die 100b and the edge E4 of the encapsulation layer 80; and edge S4' of die 100b faces edge E3 of encapsulation layer 80. Furthermore, the edge S1 of the die 100a provided with the transceiving interface region 106a and the edge S1' of the die 100b provided with the transceiving interface region 106b face each other and are arranged next to each other in the direction D1; and edge S2 of die 100a and edge S2' of die 100b face and are adjacent to edges E1 and E2 of encapsulation layer 80, respectively, that are opposite to each other in direction D1.

As shown in fig. 1A, by the above arrangement, the transceiving element 106a1 and the transceiving element 106a2 of the die 100a and the transceiving element 106b2 and the transceiving element 106b1 of the die 100b may correspond to and be communicatively connected to each other, respectively. Specifically, the receiving interface Ra1 of the transceiving element 106a1 is disposed corresponding to the transmitting interface Tb2 of the transceiving element 106b2, the transmitting interface Tb2 of the die 100b is configured to send signals to the die 100a, and the receiving interface Ra1 of the die 100a is configured to receive signals from the transmitting interface Tb2 of the die 100 b; the transmit interface Ta1 of the transceiving element 106a1 is disposed in correspondence with the receive interface Rb2 of the transceiving element 106b2, the transmit interface Ta1 of the die 100a is configured to transmit signals to the die 100b, and the receive interface Rb2 of the die 100b is configured to receive signals from the transmit interface Ta1 of the die 100 a. Similarly, the receiving interface Ra2 and the transmitting interface Ta2 of the transceiving element 106a2 are respectively connected with the corresponding transmitting interface Tb1 and receiving interface Rb1 of the transceiving element 106b2 to realize the communication of signals/data between the die 100a and the die 100b.

It should be noted that herein, the corresponding arrangement of the transmit and receive interfaces of the transceiver elements in the die described above may include the corresponding transmit and receive interfaces being substantially aligned in the direction D1, e.g., partially overlapping or fully overlapping in the direction D1, and may also include the corresponding transmit and receive interfaces being misaligned (i.e., not overlapping) in the direction D1, but adjacent to each other in the direction D2. For example, the case of being adjacent to each other here may include that the distance between the correspondingly connected transmitting interface and receiving interface in the D2 direction is 0 or smaller than the distance between the adjacent transmitting interface and receiving interface in the same die in the D2 direction. Furthermore, although the figures show two sets of transceiver elements in each of the transceiver zones of the dies 100a and 100b, the number of transceiver elements in the transceiver zones is not limited thereto. In other embodiments, the dies 100a and 100b may each include more or fewer transceiving elements, and the locations of the transmit and receive interfaces in the transceiving elements are also not limited, so long as the dies 100a and 100b have a corresponding number (e.g., the same number) of corresponding interfaces, with their respective transmit and receive interfaces alternating in a predetermined order at the first edge. For example, the dies 100a and 100b may also each include a transceiver element having a transmitting interface and a receiving interface, where the transmitting interface of the die 100a is disposed corresponding to the receiving interface of the die 100b, and the receiving interface of the die 100a is disposed corresponding to the transmitting interface of the die 100b. In other examples, more than two transceiver elements may also be included in the transceiver interface regions of the dies 100a and 100b, and the transmit and receive interfaces in the dies 100a and 100b are arranged to correspond to each other.

On the other hand, in this document, "the first die and the second die each include a transceiver interface region that is disposed at the first edge and includes receiving interfaces and transmitting interfaces alternately disposed along the first edge" means that the receiving interfaces and the transmitting interfaces are arranged in the same predetermined order in a direction from the respective fourth edge toward the third edge of each die, and "alternately disposed" includes a single receiving interface and a single transmitting interface alternately arranged, and also includes a receiving interface group including n receiving interfaces and a transmitting interface group including m transmitting interfaces alternately arranged (n >1, m >1, and m = n). For example, when a single reception interface and a single transmission interface are alternately arranged, the alternately arranged reception interface and transmission interface include, for example, reception interface, transmission interface \8230; (or transmission interface, reception interface, transmission interface, reception interface \8230; \8230;) sequentially arranged along the first edge in a direction from the fourth edge to the third edge, and may also include a case where only 1 reception interface and only 1 transmission interface are disposed side by side at the first edge; when a reception interface group including n reception interfaces and a transmission interface group including m transmission interfaces are alternately arranged and, for example, n = m =2, the alternately arranged reception interfaces and transmission interfaces include, for example, reception interfaces, transmission interfaces \8230 \ 8230;, or transmission interfaces, reception interfaces \8230;, and so on, which are sequentially arranged in the direction from the fourth edge to the third edge, and so on, and also, a case of only 1 reception interface group and 1 transmission interface group may be included.

The receiving interfaces of the same transceiving element in the transceiving interface region of the die shown in the figure are closer to the fourth edge of the die than the transmitting interfaces, such that the respective interfaces are arranged in the same die in the order of the receiving interface, the transmitting interface \8230;, in the direction from the fourth edge to the third edge thereof, and the arrangement order of the receiving interface and the transmitting interface in the direction from the fourth edge to the third edge or in the direction from the third edge to the fourth edge is the same in the dies 100a and 100b. For example, in the die 100a, the interfaces in the transceiving interface region are arranged in the order of the receiving interface Ra1, the transmitting interface Ta1, the receiving interface Ra2, and the transmitting interface Ta2 in the direction from the fourth edge S4 to the third edge S3, and the interfaces in the die 100b also have the same arrangement order. However, it should be understood that the arrangement order of the interfaces shown in the drawings is only an illustration, and the disclosure is not limited thereto. For example, in other embodiments, in each transceiver element of the die, the respective interfaces may be located closer to the fourth edge than the receiving interfaces, for example, in the die 100a and 100b, the arrangement sequence of the respective interfaces in the transceiver interface region in the direction from the fourth edge S4/S4 'to the third edge S3/S3' may also be the transmitting interface, the receiving interface, 8230. For example, in the die 100a, in the direction from the fourth edge S4 to the third edge S3, the interfaces in the transceiving interface region may also be arranged in the order of the transmitting interface Ta1, the receiving interface Ra1, the transmitting interface Ta2, and the receiving interface Ra2; correspondingly, in the die 100b, the interfaces in the transceiving interface region may also be arranged in the order of the transmitting interface Tb1, the receiving interface Rb1, the transmitting interface Tb2, and the receiving interface Rb2 in the direction from the fourth edge S4 'to the third edge S3'.

Fig. 2A to 2D are enlarged schematic views of the region P in fig. 1A, which schematically illustrate the relative position relationship of the respective transceiving elements in the dies 100a and 100b and the conductive traces for data/signal transmission between the respective transceiving elements, according to some embodiments of the present disclosure. It should be understood that for simplicity and clarity, fig. 2A-2D only show a portion of the various transceiver elements and conductive traces connecting the transceiver elements, rather than showing all of the components, and that the conductive traces in the package connecting components are shown as visible.

For example, referring to fig. 2A, in some embodiments, the conductive traces 201c in the package connection member 200 include conductive traces L1, L2, L3, and L4 for connecting different sets of transmitting and receiving interfaces, respectively. It should be understood that the data/signal transmission directions of the conductive traces L1-L4 are schematically shown by arrows in the drawings, and are not intended to indicate the shapes of the conductive traces; also, the conductive traces L1-L4 shown in the figures are portions of the conductive trace 201c that extend in a direction parallel to the main surface of the package substrate 300 or the package connection member 200. In some embodiments, a corresponding set of transmit and receive interfaces in die 100a and die 100b are aligned in direction D1, e.g., opposing sidewalls of the transmit interface in direction D2 are respectively substantially aligned with opposing sidewalls of the corresponding receive interface in direction D2 in direction D1; the conductive tracks between the set of transmit and receive interfaces extend, for example, parallel to each other, generally along direction D1. The arrangement can make the conductive routing path between the corresponding group of the transmitting interface and the receiving interface shortest, thereby improving the speed of data/signal transmission and improving the efficiency of the device.

For example, in some embodiments, the transmission interface Tb2 of the transceiving element 106b2 and the reception interface Ra1 of the transceiving element 106a1 overlap and are substantially aligned with each other in the direction D1, e.g., opposite side walls of the transmission interface Tb2 in the direction D2 and opposite side walls of the reception interface Ra1 in the direction D2 are substantially aligned with each other in the direction D1, respectively; the conductive trace L1 is disposed between the transmitting interface Tb2 of the transceiving element 106b2 and the receiving interface Ra1 of the transceiving element 106a1, and is used for transmitting data/signals from the transmitting interface Tb2 to the receiving interface Ra1; the plurality of conductive traces L1 extend in a direction D1, for example, substantially parallel to each other.

In some embodiments, the transmitting interface Ta1 of the transceiving element 106a1 and the receiving interface Rb2 of the transceiving element 106b2 overlap and are substantially aligned with each other in the direction D1, e.g., opposite sidewalls of the transmitting interface Ta1 in the direction D2 and opposite sidewalls of the receiving interface Rb2 in the direction D2 are respectively substantially aligned with each other in the direction D1; the conductive routing L2 is disposed between the transmitting interface Ta1 and the receiving interface Rb2, and is used for transmitting data/signals from the transmitting interface Ta1 to the receiving interface Rb2; the plurality of conductive tracks L2 extend, for example, parallel to each other substantially along the direction D1.

In some embodiments, the transmission interface Tb1 of the transceiving element 106b1 and the reception interface Ra2 of the transceiving element 106a2 overlap and are substantially aligned with each other in the direction D1, for example, opposite sidewalls of the transmission interface Tb1 in the direction D2 and opposite sidewalls of the reception interface Ra2 in the direction D2 are respectively substantially aligned with each other in the direction D1; the conductive trace L3 is disposed between the transmission interface Tb1 and the reception interface Ra2, and is used for transmitting data/signals from the transmission interface Tb1 to the reception interface Ra2; the plurality of conductive traces L3 extend substantially along the direction D1, for example, parallel to each other.

In some embodiments, the transmitting interface Ta2 of the transceiving element 106a2 and the receiving interface Rb1 of the transceiving element 106b1 overlap and are substantially aligned with each other in the direction D1, e.g., opposite sidewalls of the transmitting interface Ta2 in the direction D2 and opposite sidewalls of the receiving interface Rb1 in the direction D2 are respectively substantially aligned with each other in the direction D1; the conductive routing L4 is disposed between the transmitting interface Ta2 and the receiving interface Rb1, and is used for transmitting data/signals from the transmitting interface Ta2 to the receiving interface Rb1; the plurality of conductive traces L4 extend in the direction D1, for example, substantially parallel to each other.

In the embodiment of the present disclosure, by setting the orientation of the second die group to be rotated by 180 ° counterclockwise with respect to the orientation of the first die group, the transceiving elements of the dies in the first die group and the transceiving elements of the dies in the second die group can be made to correspond to each other, and the plurality of conductive traces L1-L4 between the corresponding transmitting interface and receiving interface do not cross each other but extend in the direction D1 in a substantially parallel manner, thereby reducing the data/signal transmission distance between the transmitting interface and the receiving interface.

Referring to fig. 2B, in some embodiments, a corresponding set of transmit and receive interfaces in dies 100a and 100B may also overlap each other in direction D1 but not fully aligned (i.e., partially overlapping), i.e., opposing sidewalls of the transmit interface in direction D2 and opposing sidewalls of the receive interface in direction D2 may not be aligned with each other in direction D1, but may be offset from each other in direction D2. In this embodiment, the plurality of conductive traces L1-L4 between the respective transmitting and receiving interfaces may also extend substantially parallel to each other along the direction D1, but the disclosure is not limited thereto. For example, as shown in fig. 2C, in some embodiments where a corresponding set of transmit and receive interfaces in the dies 100a and 100b overlap each other in the direction D1 but are not fully aligned, the plurality of conductive traces L1-L4 may extend in a direction that intersects the directions D1 and D2, and may be substantially parallel to each other. In this embodiment, since the orientation of the second group C2 is rotated 180 ° counterclockwise relative to the orientation of the first group C1, the transceiving elements in the second group C2 and the transceiving elements in the first group C1 are correspondingly disposed to each other, even if the corresponding transmitting interface and receiving interface are not completely aligned in the direction D1, they can be located at the corresponding positions, so that the conductive traces between the transmitting interface and receiving interface can be disposed in parallel without being arranged in a crossing manner, so that the data/signal transmission path between the transmitting interface and receiving interface is relatively short, thereby increasing the data/signal transmission speed and further increasing the device performance.

In other embodiments, a corresponding set of transmit and receive interfaces in the dies 100a and 100b may also not overlap each other in the direction D1 but be in positions corresponding to each other such that the plurality of conductive traces L1-L4 located between the respective transmit and receive interfaces may be arranged parallel to each other without crossing each other and, for example, parallel to each other extending in a direction that intersects the directions D1 and D2.

Referring back to fig. 1A and 1B, in this embodiment, the encapsulation structure 500 further includes a plurality of conductive connectors 160 disposed between the first and second groups of dies C1 and C2 and the encapsulation connection member 200 to provide electrical connection between the first and second groups of dies C1 and C2 and the encapsulation connection member 200. For example, the die 100a in the first die group C1 is connected to the die 50a and the die 52a through the conductive connection 160 and the conductive trace 201a in the package connection member 200, respectively; the die 100b in the second die group C2 is connected to the die 50b and the die 52b through the conductive connection 160 and the conductive trace 201b in the package connection member 200, respectively; the die 100a of the first die group C1 is connected to the die 100b by the conductive connection 160 and the conductive trace 201C in the package connection member 200. In some embodiments, the conductive connection 160 may include a plurality of conductive bumps, such as or including a plurality of micro-bumps (micro-bumps).

In some embodiments, a plurality of conductive connectors 260 are disposed at one side of the package connecting member 200 away from the first and second die groups C1 and C2 and between the package connecting member 200 and the package substrate 300 to provide electrical connection therebetween. The conductive connection 260 may include a conductive bump, such as a Controlled collapsed chip connection (C4) bump, but the disclosure is not limited thereto. In some embodiments, an underfill layer (e.g., the underfill layer 229 in fig. 5A to 5C) is further disposed in the space between the package connection member 200 and the package substrate 300 to surround and encapsulate the plurality of conductive connectors 260.

In some embodiments, the plurality of conductive connectors 360 are disposed on a side of the package substrate 300 away from the package connection member 200; the package substrate 300 may include conductive traces therein for connecting the conductive connectors 260 and 360, such that the first and second die groups C1 and C2 may be connected to the conductive connectors 360 through the conductive connectors 160, the package connecting member 200, the conductive connectors 260, and the package substrate 300, and may be further connected to an external member, such as a Printed Circuit Board (PCB), through the conductive connectors 360. In some embodiments, the conductive connection 360 may be or include a solder ball (ball), such as a Ball Grid Array (BGA), but the disclosure is not limited thereto. In some embodiments, the package structure 500 may be further connected to other external components, such as a printed circuit board, through the conductive connection 360. For example, the package structure 500 may be mounted on a printed circuit board, the printed circuit board may be disposed on a side of the package substrate 300 away from the package connecting member 200, and the conductive connecting member 360 is disposed between the package substrate 300 and the printed circuit board to provide an electrical connection between the package structure 500 and the printed circuit board.

Fig. 3A and 3B illustrate schematic top and cross-sectional views ofbase:Sub>A package structure 600 according to further embodiments of the present disclosure, wherein fig. 3B isbase:Sub>A cross-sectional view taken along linebase:Sub>A-base:Sub>A' of fig. 3A. The package structure of the present embodiment is similar to that of the previous embodiment, except that the package structure of the present embodiment includes a plurality of package connecting members, and the connection between the first die of the first die group and the second die of the second die group is achieved through the plurality of package connecting members and the package substrate.

Referring to fig. 3A and 3B, in some embodiments, in the encapsulation structure 600, the plurality of encapsulation connecting members 200a and 200B are disposed on the encapsulation substrate 300, and the first and second die groups C1 and C2 are disposed at one sides of the plurality of encapsulation connecting members 200a and 200B, which are away from the encapsulation substrate 300. In some embodiments, the encapsulation coupling member 200a is disposed between the first die group C1 and the encapsulation substrate 300, and the encapsulation coupling member 200b is disposed between the second die group C2 and the encapsulation substrate 300; a plurality of conductive connectors 260 are correspondingly disposed between the package connecting member 200a and the package substrate 300 to provide electrical connection between the package connecting member 200a and the package substrate 300; a plurality of conductive connectors 260 are correspondingly disposed between the package connecting member 200b and the package substrate 300 to provide electrical connection between the package connecting member 200b and the package substrate 300.

In some embodiments, the package connection means 200a includes a plurality of conductive traces 201a in the first interconnection region to provide electrical connection between the die 100a and the memory dies 50a and 52a in the first die group C1, and the package connection means 200a further includes a plurality of additional traces 201d for providing electrical connection between the die 100a of the first die group C1 and the package substrate 300; the package connection means 200b comprises a plurality of conductive traces 201b in the second interconnection region to provide electrical connection between the die 100b and the memory dies 50b and 52b in the second die group C2, and the package connection means 200b further comprises a plurality of additional traces 201d for providing electrical connection between the die 100b of the first die group C2 and the package substrate 300. In this embodiment, the package substrate 300 further includes a plurality of conductive traces 301a for electrically connecting the first die group C1 and the second die group C2, for example, for electrical connection and data/signal transmission between the die 100a and the die 100b.

For example, the transceiving elements 106a1 and 106a2 in the first die 100a and the corresponding transceiving elements 106b2 and 106b1 in the second die 100b are electrically and communicatively connected to each other through the conductive connection 160, the additional trace 201d in the package connection members 200a and 200b, the conductive connection 260, and the conductive trace 301a in the package substrate 300, respectively.

In this embodiment, the encapsulating layer 80 includes a sub-encapsulating layer 80a and a sub-encapsulating layer 80b spaced apart from each other, and the sub-encapsulating layer 80a and the sub-encapsulating layer 80b are respectively disposed at sides of the encapsulation connecting members 200a and 200b, which are far from the encapsulation substrate 300, to respectively encapsulate the first and second core-tube groups C1 and C2. Referring to fig. 3A, the sub-encapsulation layers 80a and 80b each have edges E1 and E2 extending in the direction D2 opposite and parallel to each other in the direction D1, and edges E3 and E4 extending in the direction D1 opposite and parallel to each other in the direction D2. In this embodiment, in the encapsulating layer 80, viewed in its entirety, the edges E1 and E2 of the sub-encapsulating layer 80a and 80b face outwards and may be referred to as first and second encapsulating layer edges, respectively, of the encapsulating layer 80 opposite in direction D1; the edges E3 of the sub-encapsulation layers 80a and 80b face outward from the edges E4 of the sub-encapsulation layers 80a and 80b and may be referred to as third and fourth encapsulation layer edges of the encapsulation layer 80, respectively. Further, the edge E2 of the sub-encapsulation layer 80a and the edge E1 of the sub-encapsulation layer are adjacent in the direction D1 and face each other, and may be referred to as inner edges of the encapsulation layer 80, respectively.

In this embodiment, the orientation of the first group of dies C1 and the orientation of the second group of dies C2 are similar to that described in the previous embodiment, wherein the edge S1 of the first die 100a is proximate to the edge E2 of the sub-encapsulation layer 80a and toward the second encapsulation layer edge of the encapsulation layer 80 (i.e., the edge E2 of the sub-encapsulation layer 80 b), and the edge S1' of the second die is proximate to the edge E1 of the sub-encapsulation layer 80b and toward the first encapsulation layer edge of the encapsulation layer 80 (i.e., the edge E1 of the sub-encapsulation layer 80 a).

Fig. 4A to 4D are enlarged schematic views of the region P' of fig. 3A according to some embodiments of the present disclosure, and schematically illustrate the connection relationship between the transceiving elements 106a1 and 106a2 of the die 100a and the transceiving elements 106b2 and 106b1 of the die 100b. For simplicity and clarity of the drawings, only the transceiver devices and the conductive traces connecting the transceiver devices are shown in the enlarged view.

Referring to fig. 4A to 4D, in the present embodiment, the connection relationship between the transceiving elements 106a1 and 106a2 of the die 100a and the transceiving elements 106b2 and 106b1 of the die 100b is similar to that described with reference to fig. 2A to 2D, except that the conductive traces L1 to L4 are disposed in the package substrate 300, for example, the conductive trace 301a in the package substrate 300 includes conductive traces L1 to L4 for respectively connecting corresponding transmitting interfaces and receiving interfaces in the transceiving elements of the die 100a and the transceiving elements of the die 100b, and the conductive traces L1 to L4 are portions of the conductive trace 301a extending in a direction parallel to the main surface of the package substrate 300.

In embodiments of the present disclosure, the package connection members 200, 200a, and 200b may use any suitable connection members to provide the corresponding connection requirements. For example, each of the package connection members 200, 200a, and 200b may be selected from one of an interposer (interposer), a redistribution structure (redistribution structure), and a connection structure including a bridge die (bridge die).

Fig. 5A to 5C respectively show schematic cross-sectional views of a package connection member 200 in a package structure 500 according to an embodiment of the present disclosure employing an interposer, a rewiring structure, a connection structure including a bridge die.

Referring to fig. 5A, in some embodiments, in the package structure 500a, an interposer (inter) IS used as the package connection member 200, and the package structure 500a may also be referred to as a chip-on-wafer-on-substrate (CoWoS) package. For example, the interposer IS may include a substrate 221, a Through Substrate Via (TSV) 222, and an interconnection structure 226. The substrate 221 may be a semiconductor substrate, such as a silicon substrate, but may alternatively or additionally include other suitable semiconductor materials. The interconnect structure 226 is disposed on the substrate 221, for example, on a side of the substrate 221 adjacent to the first and second die groups C1 and C2. In some embodiments, the interconnect structure 226 includes one or more layers of conductive traces 201a-201c, 225 embedded in the dielectric structure 223; the material of the dielectric structure 223 may include silicon oxide, silicon nitride, silicon oxynitride, the like or a combination thereof, and the dielectric structure may be a single-layer or multi-layer structure; the material of the conductive traces 225 can be a material including a metal, such as titanium, copper, etc., the conductive traces 201a-201c, 225 can include conductive lines that can extend, for example, in a horizontal direction parallel to the major surface of the substrate 221 and can include conductive lines at different layers, and conductive vias that can extend in a vertical direction perpendicular to the major surface of the substrate 221 and connect the conductive lines at different layers; in some embodiments, the interposer IS includes conductive pads on the top of the interconnect structures 226, which may be, for example, the top portions of the conductive traces 225 near the respective dies, or conductive members formed on the side of the conductive traces 225 near the respective dies. The through substrate via 222 includes a conductive material, such as a metal including titanium, copper, etc., and the material thereof may be the same as or different from that of the conductive trace; the substrate through hole 222 extends through the substrate 221 and is electrically connected to the conductive trace 225; in some embodiments, an insulating layer is further disposed between the through substrate via 222 and the substrate 221, so that the through substrate via 222 is electrically isolated from the substrate 221.

In the interposer IS, the interconnection structure 226 includes a conductive trace 201a located in the first interconnection region CR1, a conductive trace 201b located in the second interconnection region CR2, a conductive trace 201c located in the third interconnection region CR3, and a conductive trace 225 located outside the interconnection regions; the functions of the conductive traces 201a to 201c in the first to third interconnection regions are the same as those of the previous embodiment, and are not described herein again; the conductive traces 225 are used for providing electrical connection between the first die group C1 and the second die group C2 and the package substrate 300. The package substrate 300 may include conductive traces 325. For example, the first and second die groups C1 and C2 can be connected to an external member, such as a printed circuit board, through the conductive connection 160, the conductive trace 225 in the interconnection structure 226 of the interposer IS, the through substrate via 222, the conductive connection 260, the package substrate 300, and the conductive connection 360.

Referring to fig. 5B, in some embodiments, a redistribution structure (redistribution structure) RS is employed as the package connection member 200. In some embodiments, the redistribution structure RS includes a dielectric structure 206 and one or more redistribution layers (RDLs), the dielectric structure 206 may include a suitable polymer material such as epoxy, polyimide, etc., and may be a single-layer or multi-layer structure; one or more redistribution layers are embedded in the dielectric structure 206; the redistribution layer may include a plurality of layers of conductive lines, and the conductive lines at different layers may be electrically connected to each other through the conductive vias; the redistribution layer comprises a suitable conductive material, for example a metal material comprising titanium, copper or the like. It should be understood that the arrangement and number of redistribution layers shown in the figures are merely illustrative and the disclosure is not limited thereto. For example, in this embodiment, the conductive traces 201a, 201b, 201C of the package connection component 200 located in the first to third interconnection regions are redistribution layers located in the first to third interconnection regions CR1 to CR3 in the redistribution structure RS, respectively, to provide electrical connection between the die 100a and the dies 50a and 52a in the first die group C1, electrical connection between the die 100b and the dies 50b and 52b in the second die group C2, and electrical connection between the die 100a of the first die group C1 and the die 100b of the second die group C2, respectively. In addition, the package connecting member 200 further includes conductive traces located outside the first to third interconnection regions, for example, in this embodiment, the redistribution structure RS further includes a redistribution layer RDL located outside the first to third interconnection regions for providing electrical connection between the first and second die groups C1 and C2 and the package substrate 300 (e.g., the conductive traces 325 thereof), respectively, so that the first and second die groups C1 and C2 can be further connected to an external member, for example, a printed circuit board, through the redistribution structure RS and the package substrate 300.

Referring to fig. 5C, in some embodiments, a connection structure BS is employed as the package connection member 200. In some embodiments, the connection structure BS includes a bridge die (bridge die) BD and a plurality of conductive members 203 and 205. In some embodiments, the bridge die BD is a die formed on the basis of a semiconductor substrate (e.g., a silicon substrate), and may include conductive traces 202 to provide electrical connections. The conductive trace 202, the conductive members 203 and 205 each comprise a conductive material such as a metal, including, for example, titanium, copper, gold, tungsten, aluminum, the like, alloys thereof, or combinations thereof. In some embodiments, the conductive members 203 and 205 may include conductive vias, conductive traces, or a combination thereof. The conductive member 203 is disposed on the bridging die 202, for example, on a side of the bridging die 202 away from the package substrate 300 and close to the first and second die groups C1 and C2, and the conductive member 203 is electrically connected to the bridging die 202 and the conductive connecting member 160. It should be noted that the structure of the bridge die BD and the structures of the conductive members 203 and 205 schematically illustrated in fig. 5C are merely illustrative, and the disclosure is not limited thereto. In some embodiments, the connecting structure BS further comprises a dielectric structure 216, the dielectric structure 216 surrounding the bridge die BD and the plurality of conductive members 203 and 205. Dielectric structure 216 may be a single layer or a multi-layer structure and may comprise a suitable dielectric material, which may include, for example, inorganic dielectric materials such as silicon oxide, silicon nitride, etc.; organic dielectric materials including polyimide, epoxy, EMC, and the like including polymer materials; or a combination thereof, and the disclosure is not limited thereto. In this embodiment, the conductive traces 201a-201C of the package connection means 200 in the first to third interconnection zones respectively include the conductive trace 202 in the bridging die BD in the first to third interconnection zones CR1 to CR3 and the conductive means 203 on the bridging die BD of the connection structure BS to respectively provide the electrical connection between the die 100a and the dies 50a and 52a in the first die group C1, the electrical connection between the die 100b and the dies 50b and 52b in the second die group C2, and the electrical connection between the die 100a of the first die group C1 and the die 100b of the second die group C2.

Further, in this embodiment, the conductive members 205 located outside the first to third interconnection zones CR1 to CR3 are electrically connected to the conductive connection members 160 and 260 to provide electrical connection between the first and second die groups C1 and C2 and the encapsulation substrate 300, so that the first and second die groups C1 and C2 can be further connected to an external member, such as a printed circuit board, through the conductive members 205 of the connection structure BS and the encapsulation substrate 300.

Fig. 6A-6B illustrate embodiments in which package connection members in a package structure 600 employ an interposer, a redistribution layer, and a connection structure including a bridge die, respectively.

Referring to fig. 6A, in some embodiments, in the package structure 600a, the interposer ISa and ISb are respectively adopted as the package connection members 200a and 200b, and the interposer ISa and ISb are similar to the interposer IS of the previous embodiment and are not described herein again. In this embodiment, the interconnection structures 226 of the interposers ISa and ISb respectively include conductive traces 201a in the first interconnection region CR1 for electrical connection of the die 100a and the dies 50a and 52a within the first die group C1 and conductive traces 201B in the second interconnection region CR2 for electrical connection of the die 100B and the dies 50B and 52B within the first die group C2, and also respectively include conductive traces 225 (i.e., conductive traces 201d in the package connecting members 200a and 200B described above with reference to fig. 3B) for electrical connection between the first and second die groups C1 and C2 and the package substrate 300. In this embodiment, the die 100a and the die 100b are connected to each other through the conductive connection 160, the conductive trace 225 of the interconnect structure 226 in the interposer ISa and ISb, and the through-substrate via 222, the conductive connection 260, and the conductive trace 301a in the package substrate 300.

Referring to fig. 6B, in some embodiments, in the package structure 600B, the rerouting structures RSa and RSb are respectively adopted as the package connection members 200a and 200B, and the rerouting structures RSa and RSb are similar to the rerouting structure RS of the previous embodiment and are not described again. In this embodiment, the redistribution layers of the redistribution structures RSa and RSb respectively include the conductive trace 201a in the first interconnection region CR1 for the electrical connection of the die 100a and the dies 50a and 52a in the first die group C1 and the conductive trace 201b in the second interconnection region CR2 for the electrical connection of the die 100b and the dies 50b and 52b in the first die group C2, and also include the redistribution layers RDL for the electrical connection between the first and second die groups C1 and C2 and the package substrate 300. In this embodiment, the conductive trace 201e (fig. 3B) in the package connection members 200a and 200B is the redistribution layer RDL, and the die 100a and the die 100B are connected to each other through the conductive connection member 160, the redistribution layer RDL of the redistribution structures RSa and RSb, the conductive connection member 260, and the conductive trace 301a in the package substrate 300.

Referring to fig. 6C, in some embodiments, in the package structure 600C, connection structures BSa and BSb including the bridge die BD are respectively adopted as the package connection members 200a and 200b, and the connection structures BSa and BSb are similar to the connection structures BS of the previous embodiments and are not described herein again. In this embodiment, the connecting structures BSa and BSb respectively include a conductive member 203 in the first interconnection region CR1 and a bridging die BD including a conductive trace 202a for electrical connection of the die 100a and the dies 50a and 52a in the first die group C1 and a conductive member 203 in the second interconnection region CR2 and a bridging die BD including a conductive trace 201b for electrical connection of the die 100b and the dies 50b and 52b in the first die group C2, and further include a conductive member 205 for electrical connection between the first and second die groups C1 and C2 and the package substrate 300, respectively. In this embodiment, the conductive traces 201e (fig. 3B) in the package connection members 200a and 200B are the conductive members 205 of the connection structures BSa and BSb, and the die 100a and the die 100B are connected to each other through the conductive connectors 160, the conductive members 205 of the connection structures BSa and BSb, the conductive connectors 260, and the conductive traces 301a in the package substrate 300.

The embodiments of the present disclosure may be applied to a chip system including various types of chips, for example, an intelligent inference chip, an intelligent training chip, a general GPU chip, an edge computing GPU chip, a general CPU chip, a specific CPU chip, and the like, but the present disclosure is not limited thereto.

In various embodiments of the present disclosure, by disposing the first and second die groups in the rotationally symmetric structure described above, the interconnection length between the first and second dies can be minimized, and the first and second dies having substantially the same structure can be manufactured using the same semiconductor process. In contrast, in some conventional package structures, the first die group and the second die group are arranged symmetrically, and the orientations of the first die and the second die are the same, so that the transceiving interface area of the first die located at the first edge faces the second edge of the second die and is far away from the transceiving interface area of the second die located at the first edge, so that the distance between the transceiving interface areas of the first die and the second die is far, the interconnection length between the transceiving interface areas of the first die and the second die is further increased, and the data/signal transmission speed is reduced; on the other hand, in the case that the orientations of the first die and the second die are the same as each other, if the transceiver interface region of the second die is disposed at the second edge thereof in order to reduce the interconnection length between the transceiver interface regions, the first die and the second die need to be formed using different semiconductor processes, or the first die and the second die use the same semiconductor process but need to be simultaneously disposed at the first edge and the second edge to achieve interconnection between chips, thereby increasing the manufacturing cost and reducing the yield. In the embodiment of the present disclosure, by arranging the dies/die groups to be rotationally symmetric, the interconnection between the dies can be realized by only arranging the transceiver interface region at one edge of each die, and the interconnection length can be minimized.

Therefore, compared with the conventional package structure, the package structure of the embodiment of the disclosure may use the dies formed from the same semiconductor process by the above-mentioned special orientation arrangement, thereby saving the manufacturing cost, improving the yield, and minimizing the interconnection length between the dies, thereby improving the transmission speed of signals/data between the dies and further improving the device performance.

On the other hand, the 2.5D packaging technology is combined with the multi-chip integration technology, and large-scale complex high-performance chip integration can be achieved. By setting the first chip set and the second chip set to be in the rotational symmetry structure, the warping problem of a packaging structure (such as an oversized chip system) can be avoided or reduced, and the performance of the device is improved.

The following points need to be explained:

(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to general designs.

(2) Features of the disclosure in the same embodiment and in different embodiments may be combined with each other without conflict.

The above is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and shall be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (20)

1. A package structure, comprising:

a package substrate; and

a first die and a second die disposed on the package substrate, the first die and the second die each having a first edge and a second edge opposite to each other in a first direction and extending in a second direction, and a third edge and a fourth edge opposite to each other in the second direction and extending in the first direction, the first direction and the second direction intersecting each other;

wherein the first die and the second die each include a transceiver interface region disposed at the first edge and including receive interfaces and transmit interfaces alternately disposed along the first edge,

a portion of the first edge of the first die where the transceiver interface region is disposed and a portion of the first edge of the second die where the transceiver interface region is disposed face each other in the first direction,

in the second direction, a portion of the first die not disposed at the first edge of the transceiver interface region extends to a side of the third edge of the second die away from the fourth edge of the second die, a portion of the second die not disposed at the first edge of the transceiver interface region extends to a side of the third edge of the first die away from the fourth edge of the first die,

the receiving interface in the transceiving interface region of the first die is electrically connected with the transmitting interface in the transceiving interface region of the second die, and the transmitting interface in the transceiving interface region of the first die is electrically connected with the receiving interface in the transceiving interface region of the second die.

2. The package structure of claim 1, wherein a distance between the transceiver interface region and the third edge is less than a distance between the transceiver interface region and the fourth edge.

3. The package structure of claim 1, further comprising:

a first memory die disposed on a side of the third edge of the first die away from the fourth edge in the second direction, the first memory die at least partially overlapping the second die in the first direction; and

a second memory die disposed on a side of the third edge of the second die away from the fourth edge in the second direction, the second memory die at least partially overlapping the first die in the first direction.

4. The package structure of claim 1, wherein the transmit interface and the receive interface of the first die and the second die that are connected corresponding to each other overlap in the first direction.

5. The package structure according to claim 4, wherein the sidewalls of the transmitting interface opposite in the second direction and the sidewalls of the receiving interface correspondingly connected opposite in the second direction are aligned with each other in the first direction, respectively.

6. The package structure according to claim 4, wherein the sidewalls of the transmitting interface opposite in the second direction and the sidewalls of the receiving interface correspondingly connected opposite in the second direction are offset from each other in the second direction, respectively.

7. The package structure of claim 1, wherein the transmit interface and the correspondingly connected receive interface do not overlap in the first direction but are adjacent to each other in the second direction.

8. The package structure of claim 1, further comprising at least one package connection member disposed on the package substrate, wherein the first die and the second die are disposed on a side of the at least one package connection member away from the package substrate, wherein the at least one package connection member or the package substrate comprises first conductive traces electrically connecting the transmission interface of the first die and the reception interface of the second die, and second conductive traces electrically connecting the reception interface of the first die and the transmission interface of the second die.

9. The package structure of claim 8, wherein portions of the first and second conductive traces that extend parallel to the major surface of the package substrate extend parallel to each other along the first direction.

10. The package structure according to claim 8, wherein portions of the first and second conductive traces that extend parallel to a major surface of the package substrate extend parallel to each other in a third direction that is parallel to the major surface of the package substrate and that intersects the first and second directions.

11. The package structure according to claim 8, wherein the at least one package connection member is one package connection member, and the first conductive trace and the second conductive trace are disposed in the one package connection member for electrical connection of the first die and the second die.

12. The package structure of claim 11, wherein the first die and the second die are both system chips.

13. The package structure of claim 11, further comprising:

a first memory die and a second memory die disposed on a side of the one package connection member away from the package substrate,

wherein the one package connection member includes a first interconnection region, a second interconnection region, and a third interconnection region, the first interconnection region is used for electrical connection between the first die and the first memory die, the second interconnection region is used for electrical connection between the second die and the second memory die, and the first conductive trace and the second conductive trace are disposed in the third interconnection region of the one package connection member.

14. The package structure of claim 8, wherein the at least one package connection member comprises a first package connection member and a second package connection member, the first package connection member being located between the first die and the package substrate, and the second package connection member being located between the second die and the package substrate, wherein the first conductive trace and the second conductive trace are disposed in the package substrate, and the corresponding transmit interface and the receive interface in the first die and the second die are connected to each other through the first package connection member, the second package connection member, and the package substrate.

15. The package structure of claim 14, further comprising:

a first memory die and a second memory die disposed on a side of the first package connection member and the second package connection member, respectively, away from the package substrate,

wherein the first package connection means comprises a first interconnect area for electrically connecting the first die and the first memory die and a first additional trace for connecting the first conductive trace of the first die and the package substrate, and the second package connection means comprises a second interconnect area for electrically connecting the second die and the second memory die and a second additional trace for connecting the second conductive trace of the second die and the package substrate.

16. The package structure of claim 8, wherein the at least one package connection member comprises an interposer, a redistribution structure, or a connection structure with a bridged die.

17. The package structure of any of claims 1-16, wherein no transceiver interface region is disposed at the second edge of the first die and the second edge of the second die.

18. The package structure of claim 3, further comprising at least one of a first dummy die and a second dummy die, the first dummy die disposed on the side of the third edge of the first die away from the fourth edge in the second direction and overlapping the first memory die in the first direction; the second dummy die is disposed on the side of the third edge of the second die away from the fourth edge in the second direction and overlaps the second memory die in the first direction.

19. The package structure of claim 1, wherein the second die has a same orientation as the first die after being rotated 180 degrees in a plane in which the first direction and the second direction lie, the same orientation comprising the first edge to the fourth edge of the second die facing the same direction as the first edge to the fourth edge of the first die after being rotated 180 degrees in the plane.

20. The package structure of any of claims 1-16, wherein the first die and the second die are dies having the same structure.

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