CN217821194U

CN217821194U - Thin film transistor substrate capable of reducing lower frame of screen

Info

Publication number: CN217821194U
Application number: CN202221933574.0U
Authority: CN
Inventors: 汪梅艺; 刘汉龙
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2022-07-26
Filing date: 2022-07-26
Publication date: 2022-11-15
Anticipated expiration: 2032-07-26

Abstract

A thin film transistor substrate capable of reducing the lower frame of a screen comprises from bottom to top: the device comprises a GE layer, a first insulating layer, an SD layer, a second insulating layer, a third insulating layer, a fourth insulating layer and an ITO layer; one end of a Data line and a gate drive circuit signal line is connected to an IC Pad of the sinking IC, and the other end of the Data line and the gate drive circuit signal line directly penetrate through the IC Dummy Pad of the sinking IC to be connected to the in-plane pixel. An organic insulating layer is further arranged between the second insulating layer and the third insulating layer. The utility model discloses a with Dataline and the design that gate drive circuit signal line directly passed IC dummy Pad, with the reduction of screen lower frame to effectively shorten probably 100-200um with screen lower frame.

Description

Thin film transistor substrate capable of reducing lower frame of screen

Technical Field

The utility model belongs to the technical field of display device's the manufacturing, concretely relates to but TFT (thin film transistor) base plate of screen lower frame of reducing.

Background

With the development of the times and the progress of science and technology, users have more sophisticated requirements on the appearance of mobile phone products, which leads to the continuous development of mobile phone products towards light, thin, power-saving and full-screen directions. The full screen display not only promotes the color value of the product, makes the product look more scientific and technological sense, and the higher screen accounts for the ratio and makes the system can show more information, promotes user's visual experience, so the full screen technique has become a popular trend of present display devices.

The overall structure of the liquid crystal display panel includes: the overall structure of the liquid crystal display panel includes: a TFT substrate and a color filter substrate (CF) are added with liquid crystal for synthesis; the TFT substrate includes an IC design, and thus includes an Indium Tin Oxide (ITO) film, an IC, a Data line, a gate driver circuit signal line, an in-plane PIXEL (PIXEL), and the like.

In order to increase the screen occupation ratio of the screen, reducing the frame of the screen has become an inevitable trend of current technology development. Mobile phone manufacturers gradually develop various special-shaped full-screen screens without reducing the necessary functions of a front camera, an infrared sensor, a loudspeaker receiver and the like, and the common special-shaped full-screen screens in the market comprise a sea-flowing screen, a water drop screen, a hole digging screen and the like. The screen occupation ratio of the hole digging screen reaches the highest specification, only a single photographic lens is left and arranged in the middle of the display screen after sensors required by all panels are integrated, the screen occupation ratio of more than 90 percent can be achieved, and the use experience of a user is greatly improved.

In addition, the design of the integrated circuit IC can also achieve the purpose of reducing the screen frame, the design of the IC is divided into a normal IC (as shown in fig. 1) and a sinking IC (as shown in fig. 2), and in the process of stitching the sinking IC, because stitching is easy to be unstable due to the design of the sinking IC, IC dummy pads (integrated circuit dummy pads) are placed above the left side and the right side of the sinking IC, so that the functions of supporting and stabilizing the IC can be achieved. Meanwhile, the IC needs to be connected to the in-plane pixels through datalines and gate driving circuit signal lines. In a traditional connection mode, data lines and signal lines of a grid driving circuit need to bypass an IC dummy Pad, and the design method can enlarge the frame of a lower screen and cannot realize the design of a narrow frame.

In the process of pressing, due to the fact that the pressing is easy to be unstable due to the design of the sinking type IC, the IC dummy Pads are placed above the left side and the right side of the sinking type IC, and the functions of supporting and IC stabilizing can be achieved. Meanwhile, the IC needs to be connected to the in-plane pixels through datalines and gate driving circuit signal lines. In the conventional connection method, because the layers of Dataline and gate driving circuit signal line are the same as the layers of the IC dummy Pad, the Dataline and gate driving circuit signal line need to bypass the IC dummy Pad during the wire pulling, and because the TFT substrate process (as shown in fig. 3) has 6 photo masks GE (gate metal layer), SE (semiconductor layer), PE (pixel electrode layer), SD (source drain layer), CH (bridge layer), and BC (common electrode layer), there is only one insulating layer and one Indium Tin Oxide (ITO) behind the Dataline (SD), there is a possibility that the insulating layer and ITO may break and short circuit due to the close distance between the Dataline and gate driving circuit signal line and the IC dummy Pad, and therefore, the Dataline and gate driving circuit signal line need to bypass the IC dummy Pad (as shown in fig. 4), and such a design method will increase the screen lower frame (as shown in fig. 5), and the lower frame can not reach 3400um, and the design of the narrow frame cannot be realized.

Disclosure of Invention

The utility model aims to solve the technical problem that a TFT base plate of frame under the screen can reduce is provided, lets Dataline and gate drive circuit signal line directly pass ICdummy Pad, makes its purpose that reaches the frame under the reduction screen.

The utility model discloses a realize like this:

a TFT base plate of the frame under the reducible screen, include from bottom to top: a GE (gate metal) layer, a first insulating layer, an SD (source drain) layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and an ITO (indium tin oxide) layer; an IC (integrated circuit) is arranged above the ITO (indium tin oxide film) layer, the IC (integrated circuit) is a sinking IC (integrated circuit), one end of a Dataline and a grid drive circuit signal line is connected to an ICpad (integrated circuit block) of the sinking IC, and the other end of the Dataline and the grid drive circuit signal line directly penetrate through an IC Dummy Pad (integrated circuit simulation Pad) of the sinking IC to be connected to in-plane pixels.

Further, an organic insulating layer is further disposed between the second insulating layer and the third insulating layer.

Further, the organic insulating layer is an OC (organic planarization layer).

Further, the first insulating layer is a GI (gate insulating layer).

Further, the second insulating layer is PV (insulating layer).

Further, the third insulating layer is VA (conductive via).

Further, the fourth insulating layer is CH (bridge).

The utility model has the advantages of: _{can be used for} Under the condition of not influencing the panel structure, the Data line and the signal line of the gate drive circuit directly pass through the design of the IC dummy Pad, so that the aim of reducing the lower frame of the screen is fulfilled. Therefore, the lower frame of the screen is reduced in this way, so that the lower frame of the screen is effectively shortened by about 100-200um.

Drawings

The invention will be further described with reference to the following examples with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a normal IC structure.

FIG. 2 is a schematic diagram of a sinking IC structure.

Fig. 3 is a schematic structural view of a TFT substrate of the related art.

Fig. 4 is a wiring method of a related art sinker IC.

Fig. 5 is a screen schematic of the prior art.

Fig. 6 is a schematic structural diagram of a TFT substrate according to a first embodiment of the present invention.

Fig. 7 is a schematic structural diagram of a TFT substrate according to a second embodiment of the present invention.

Fig. 8 shows a wiring method of a sink IC according to the present invention.

Fig. 9 is a screen schematic diagram of a TFT substrate structure according to the present invention.

Detailed Description

As shown in fig. 6, the TFT substrate structure of the first embodiment includes, from bottom to top: a GE layer, a first insulating layer GI, an SD layer, a second insulating layer PV, a third insulating layer VA, a fourth insulating layer CH and an ITO layer; an IC is arranged above the ITO layer, the IC is a sinking IC, one end of a Data line and a gate drive circuit signal line is connected to an IC Pad of the sinking IC, and the other end of the Data line and the gate drive circuit signal line directly penetrate through the IC Dummy Pad of the sinking IC to be connected to an in-plane pixel, as shown in figure 8.

As shown in fig. 7, the TFT substrate structure of the second embodiment is different from the first embodiment in that an organic insulating layer OC is further disposed between the second insulating layer and the third insulating layer.

The panel process has 10 photomasks GE (gate metal layer), SE (semiconductor layer), SD (source drain layer), DC (hole connecting GE and SD), OC (organic flat layer), CM (touch signal wiring metal layer), VA (conductive via), BC (common electrode layer), CH (bridge), PE (pixel electrode layer), thus the design of two embodiments is proposed, the first embodiment: two layers of insulating layers are added on the basis of the traditional design, so that three layers of insulating layers and one layer of ITO are arranged between the Dataline and the signal line of the grid driving circuit and the IC dummy Pad, the distance between the insulating layers and the ITO is enough, and the insulating layers and the ITO are not easy to break and generate short circuit; the second embodiment: in the first embodiment, an organic insulating layer is added, so that four insulating layers and an ITO layer are arranged between the Dataline and the gate driving circuit signal line and the IC dummy Pad, and the Dataline and the gate driving circuit signal line can directly pass through the IC dummy Pad, thereby achieving the purpose of reducing the lower frame of the screen. The design method of the utility model can shorten the lower frame of the screen by 100-200um (as shown in figure 9), thereby enlarging the effective area in the surface.

The above embodiments and drawings are not intended to limit the form and style of the present invention, and any suitable changes or modifications made by those skilled in the art should not be construed as departing from the scope of the present invention.

Claims

1. A thin film transistor substrate capable of reducing the lower frame of a screen is characterized in that: comprises from bottom to top: the semiconductor device comprises a grid metal layer, a first insulating layer, a source drain layer, a second insulating layer, a third insulating layer, a fourth insulating layer and an indium tin oxide film layer; the integrated circuit is arranged above the indium tin oxide film layer and is a sinking integrated circuit, one end of a data transmission line and a grid drive circuit signal line is connected to an integrated circuit block of the sinking integrated circuit board, and the other end of the data transmission line and the grid drive circuit signal line directly penetrate through an integrated circuit simulation pad of the sinking integrated circuit to be connected to an in-plane pixel.

2. The thin film transistor substrate capable of reducing the lower frame of the screen as claimed in claim 1, wherein: an organic insulating layer is further arranged between the second insulating layer and the third insulating layer.

3. The thin film transistor substrate according to claim 2, wherein: the organic insulating layer is an organic flat layer.

4. The thin film transistor substrate capable of reducing the lower frame of the screen as claimed in claim 1 or 2, wherein: the first insulating layer is a gate insulating layer.

5. The thin film transistor substrate according to claim 1 or 2, wherein: the second insulating layer is made of an insulating material.

6. The thin film transistor substrate capable of reducing the lower frame of the screen as claimed in claim 1 or 2, wherein: the third insulating layer is a conductive hole.

7. The thin film transistor substrate capable of reducing the lower frame of the screen as claimed in claim 1 or 2, wherein: the fourth insulating layer is a bridge.