CN217720777U - Chip with built-in equalization management circuit - Google Patents

Abstract

The present disclosure provides a chip with a built-in equalization management circuit, including: the balance management circuit, the balance management circuit carries out the balance between the electric core of battery module and the balance between the module of battery module, wherein, the balance management circuit includes balance management circuit between electric core and the balance management circuit between the module, balance management circuit carries out voltage balance between the electric core, and balance management circuit includes balanced resistance and balanced switch between the module, balanced resistance and balanced switch constitute series circuit, the highest voltage of battery module is connected to series circuit's one end, the minimum voltage of battery module is connected to series circuit's the other end, come to realize through balanced resistance balanced balance between the module through balanced switch's the switch-on or break-off.

Description

Chip with built-in equalization management circuit

Technical Field

The disclosure relates to a chip with a built-in equalization management circuit.

Background

At present, chemical batteries and the like are widely used, and a plurality of battery cells are generally connected in series to form a battery pack in use. However, no matter the manufacturing deviation or the use process, the cells of the battery pack will have inconsistency, that is, the cells cannot guarantee that the voltage of each cell is balanced during the use process. Therefore, energy exchange of partial cells cannot be realized, the service life of the battery is damaged, and safety accidents may occur.

At present, a balancing circuit is adopted to balance the voltage of each battery cell, so that the secondary distribution of energy in the battery pack is realized. However, the existing equalizing circuit has the problems of excessive energy loss, undersize equalizing circuit, low efficiency and the like. And complete balance of the battery pack cannot be achieved in the balancing process, and the capacity of each battery cell cannot be fully released. Therefore, there is a need to provide a control strategy that can address the increasing equalization demands.

SUMMERY OF THE UTILITY MODEL

In order to solve one of the above technical problems, the present disclosure provides a chip with a built-in equalization management circuit.

According to an aspect of the present disclosure, a chip with a built-in balancing management circuit, the balancing management circuit being configured to balance a battery voltage of each cell of a battery module, includes:

the gating circuit is connected with each battery cell so as to perform gating measurement on each battery cell;

the analog-to-digital converter is connected with the gating circuit and used for collecting the battery voltage and the battery temperature of each battery cell based on the on and off of the gating circuit;

a microcontroller connected to the analog-to-digital converter and configured to process information from the analog-to-digital converter; and

a balancing management circuit that performs inter-cell balancing of the battery module and module balancing of the battery module,

the balance management circuit comprises an inter-cell balance management circuit and a module balance management circuit, the inter-cell balance management circuit performs voltage balance among cells, the module balance management circuit comprises a balance resistor and a balance switch, the balance resistor and the balance switch form a series circuit, one end of the series circuit is connected with the highest voltage of the battery module, the other end of the series circuit is connected with the lowest voltage of the battery module, and the module balance is realized through the balance resistor by switching on or off the balance switch.

According to one embodiment of the disclosure, the equalizing resistor is an adjustable equalizing resistor and is arranged outside the chip, and the equalizing switch is arranged outside or inside the chip.

According to one embodiment of the present disclosure, the inter-cell equalization management circuit includes a first switch, a second switch, a third switch, a fourth switch, and a capacitor, which are provided for each cell, where the first switch and the third switch are connected in series to form a first series circuit, one end of the first series circuit is connected to a negative electrode of the corresponding cell, the other end of the first series circuit is connected to the other end of the other cell, the second switch and the fourth switch are connected in series to form a second series circuit, one end of the second series circuit is connected to a positive electrode of the corresponding cell, the other end of the second series circuit is connected to the other end of the other cell, and the capacitor is connected between a connection node of the first switch and the third switch and a connection node of the second switch and the fourth switch.

According to one embodiment of the present disclosure, the first switch and the second switch are turned on so as to charge the corresponding capacitors through the corresponding battery cells, then the third switch and the fourth switch are turned on so as to make the voltages of the corresponding capacitors of all the battery cells consistent, and then the first switch and the second switch are turned on so as to make the voltages of all the battery cells consistent.

According to one embodiment of the present disclosure, the equalization switch is a high voltage MOS transistor, and the first switch, the second switch, the third switch, and the fourth switch are MOS transistors.

According to one embodiment of the present disclosure, at least one of the first switch and the second switch is replaced with a current control portion by which a value of a current flowing from the current control portion into the capacitor is adjusted.

According to one embodiment of the present disclosure, the current value is a constant current value or a variable current value.

According to one embodiment of the present disclosure, the current control section includes a first PMOS transistor and a second PMOS transistor that constitute a series circuit having both ends connected to a battery cell and a capacitor, respectively, the current value being adjusted by changing on-resistances of the first PMOS transistor and the second PMOS transistor.

According to one embodiment of the present disclosure, the sources of the first PMOS transistor and the second PMOS transistor are interconnected, the drain of the first PMOS transistor is connected to a battery cell, the drain of the second PMOS transistor is connected to a capacitor, the electronic device further includes a series circuit formed by a first NMOS transistor and a resistor, the gate of the first NMOS transistor is connected to the drains of the first PMOS transistor and the second PMOS transistor, the source of the first NMOS transistor is connected to the first end of the resistor, the second end of the resistor is connected to the gates of the first PMOS transistor and the second PMOS transistor, and the gate-source voltages of the first PMOS transistor and the second PMOS transistor are changed by changing currents flowing through the first NMOS transistor and the resistor, so as to change the on-resistances of the first PMOS transistor and the second PMOS transistor.

According to one embodiment of the present disclosure, the sources of the first PMOS transistor and the second PMOS transistor are interconnected, the drain of the first PMOS transistor is connected to a battery cell, the drain of the second PMOS transistor is connected to a capacitor, the apparatus further includes a resistor, one end of the resistor is connected to the sources of the first PMOS transistor and the second PMOS transistor, the other end of the resistor is connected to the gates of the first PMOS transistor and the second PMOS transistor, and the gate-source voltage of the first PMOS transistor and the second PMOS transistor is changed by changing the current flowing through the resistor, so as to change the on-resistance of the first PMOS transistor and the second PMOS transistor.

According to one embodiment of the present disclosure, the current control section includes a first NMOS transistor and a second NMOS transistor that constitute a series circuit having both ends connected to a battery cell and a capacitor, respectively, and the current value is adjusted by changing on-resistances of the first NMOS transistor and the second NMOS transistor.

According to one embodiment of the present disclosure, the sources of the first and second NMOS transistors are interconnected, the drain of the first NMOS transistor is connected to a battery cell, the drain of the second NMOS transistor is connected to a capacitor, the apparatus further includes a third NMOS transistor, the gate of the third NMOS transistor is connected to the drains of the first and second NMOS transistors, the source of the third NMOS transistor is connected to the sources of the first and second NMOS transistors, and the gate-source voltage of the first and second NMOS transistors is changed by changing the current flowing through the third NMOS transistor, so as to change the on-resistances of the first and second NMOS transistors.

According to one embodiment of the present disclosure, the sources of the first and second NMOS transistors are interconnected, the drain of the first NMOS transistor is connected to a battery cell, the drain of the second NMOS transistor is connected to a capacitor, and the apparatus further includes a resistor, one end of the resistor is connected to the sources of the first and second NMOS transistors, the other end of the resistor is connected to the gates of the first and second NMOS transistors, and the gate-source voltage of the first and second NMOS transistors is changed by changing the current flowing through the resistor, so as to change the on-resistances of the first and second NMOS transistors.

According to one embodiment of the present disclosure, the current control portion may function as a sampling control portion, and the capacitance may function as a sampling capacitance, and the voltage of the corresponding cell is collected by the sampling control portion and the sampling capacitance.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 is a schematic diagram of a battery management system according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of an equalization management circuit according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram of an equalization management circuit according to an embodiment of the present disclosure.

Fig. 4 is a schematic diagram of an equalization management circuit according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram of an equalization management circuit according to an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of a current control portion according to an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of a current control portion according to an embodiment of the present disclosure.

Fig. 8 is a schematic diagram of a current control portion according to an embodiment of the present disclosure.

Fig. 9 is a schematic diagram of a current control portion according to an embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Thus, unless otherwise indicated, the features of the various embodiments/examples may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "over," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically connected, electrically connected, and the like, with or without intervening components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "under 8230; \8230;,"' under 8230; \8230; below 8230; under 8230; above, on, above 8230; higher "and" side (e.g., as in "side wall)", etc., to describe the relationship of one component to another (other) component as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "at 8230 \8230;" below "may encompass both an orientation of" above "and" below ". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the stated features, integers, steps, operations, elements, components and/or groups thereof are stated to be present but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

According to one embodiment of the present disclosure, a battery management system is provided, wherein the battery management system may be made in the form of a chip. Fig. 1 illustrates a battery management system, for example, in which the contents outlined in dashed lines may be made in the form of a battery management chip, according to one embodiment of the present disclosure. According to the battery management system disclosed by the invention, the collection of battery information, the estimation of the battery state and the balance of a battery system can be realized. In the present disclosure, management of the battery information may enable interaction with external information through the communication module. When the battery is manufactured into a chip form, a Microcontroller (MCU) is integrated in the chip, and the functions of estimating and controlling the SOC and SOH states of the battery can be conveniently realized.

As shown in fig. 1, the battery management system according to the present disclosure may include a first gating circuit, a first analog-to-digital converter, a microcontroller MCU, and a communication module, etc.

The first gating circuit is turned on and off according to the control signal so as to collect the voltages of the respective batteries B1, B2, \8230 \ Bn-1, bn through the first analog-to-digital converter. The first analog-to-digital converter may convert the voltages of the respective batteries into digital signals and provide them to the microcontroller. The microcontroller may transmit information to the external device via the communication module. Wherein the communication module is connectable to the isolated transceiver and communicates with the communication module through the isolated transceiver so that information can be transmitted to the external device. In addition, the information of the external device can also be transmitted to the microcontroller through the isolation transceiver and the communication module. Furthermore, a first gating circuit may be provided with respect to the battery voltage acquisition and a second gating circuit may be provided with respect to the temperature acquisition. It should be noted that the same gating circuit may be used to collect both voltage and temperature.

In the present disclosure, a second analog-to-digital converter may be further included, which may be used to acquire temperature information of each battery, wherein the temperature of each battery may be detected by a temperature sensor (external thermistor, NTC), for example, the voltage of each battery is collected by a second gating circuit, and the temperature information is converted into a digital signal via the second analog-to-digital converter and provided to the microcontroller. It should be noted that the first analog-to-digital converter and the second analog-to-digital converter may be one analog-to-digital converter ADC or may be different analog-to-digital converters ADCs.

A voltage conversion module LDO may also be included according to the present disclosure, which may receive the battery voltage and convert it to a desired voltage, e.g., 3.3V, 5V, etc. The converted voltage may provide a supply voltage to the associated component.

The battery management system may measure the voltage of the N series connected batteries and the temperature of the M batteries, e.g., N =16, M =16. The high-voltage analog front-end circuit can adopt a high-voltage process, the MCU adopts a low-voltage process, and the high-voltage analog front-end circuit and the MCU can be packaged in a chip. The low-voltage circuit and the high-voltage circuit can adopt a common ground design, and the required power supply is supplied with power through the LDO. The power supply circuit can comprise a control switch, and low power consumption design is achieved. A communication module such as a CAN controller is integrated in the chip, and information interaction is realized through an external isolated CAN transceiver. The measurement accuracy of the battery voltage can be controlled within the total measurement error of 3-5 mV in the whole temperature range, and the measurement range of the battery voltage can meet 0-5V so as to meet the requirements of most chemical batteries.

In the process of using the batteries, the voltage of each battery is different due to the manufacturing difference and the use difference of each battery. In order to prolong the service life of the battery and to prevent various problems such as overdischarge and overcharge during storage, it is necessary to perform balance management on each battery.

In the disclosure, the balance management circuit adopts a balance management technology of multi-level active and passive combination to realize balance management between the battery core and the battery module. The balance management among the battery cores in the battery module adopts an active balance management/passive balance management mode, and the balance management of the battery module assembly adopts a passive balance management mode.

The active equalization management mode will be described in detail with reference to fig. 2. As shown in fig. 2, each battery cell in the battery module is balanced and managed in an active balancing manner. For the battery cell B1, first to fourth switches and a switched capacitor may be employed. The first end of the first switch is connected with the negative electrode of the battery cell B1, the second end of the first switch is connected with the first end of the switched capacitor and the first end of the third switch, the first end of the second switch is connected with the second end of the switched capacitor and the first end of the fourth switch, the second end of the third switch is connected with the second ends of the third switches of other battery cells, and the second end of the fourth switch is connected with the second ends of the fourth switches of other battery cells.

The first to fourth switches are shown in fig. 2 in the form of transistors, which may be NMOS transistors or PMOS transistors or the like. The following description will be given taking an NMOS transistor as an example.

The source of the first NMOS transistor 101 is connected to the negative electrode of the battery B1, and the drain of the first NMOS transistor 101 may be connected to the first end of the switched capacitor 105 and the drain of the third NMOS transistor 103.

The source of the second NMOS transistor 102 is connected to the positive terminal of B1, and the drain of the second NMOS transistor 102 may be connected to the second terminal of the switched capacitor 105 and to the drain of the fourth NMOS transistor 104.

Gates of drains of the first NMOS transistor 101, the second NMOS transistor 102, the third NMOS transistor 103, and the fourth NMOS transistor 104 may be connected with a control signal to be turned on or off.

Likewise, for cell B2, the source of the first NMOS transistor 101 is connected to the negative pole of cell B2, and the drain of the first NMOS transistor 101 may be connected to the first end of the switched capacitor 105 and to the drain of the third NMOS transistor 103. The source of the second NMOS transistor 102 is connected to the positive pole of B2, and the drain of the second NMOS transistor 102 may be connected to the second terminal of the switched capacitor 105 and to the drain of the fourth NMOS transistor 104. Gates of drains of the first NMOS transistor 101, the second NMOS transistor 102, the third NMOS transistor 103, and the fourth NMOS transistor 104 may be connected with a control signal to be turned on or off.

A source of the third NMOS transistor of the battery cell B1 may be connected to a source of the third NMOS transistor of the battery cell B2, and a source of the fourth NMOS transistor of the battery cell B1 may be connected to a source of the fourth NMOS transistor of the battery cell B2.

Similarly, for other battery cores, the structure can be adopted, and for the battery module, the battery module comprises a plurality of equalizing units, and each equalizing voltage comprises one switched capacitor and four switching devices. And the sources of the third NMOS transistors of all the cells may be interconnected, and the sources of the fourth NMOS transistors may be interconnected.

In the active equalization process, each battery cell is connected with a corresponding capacitor in parallel until the voltages of the battery cells and the capacitors are consistent. For example, taking the battery cell B1 as an example, the first NMOS transistor 101 and the second NMOS transistor 102 may be controlled to be turned on, so that the battery cell B1 charges the capacitor 105 until voltages of the battery cell B1 and the capacitor 105 are consistent. Note that the third NMOS transistor 103 and the fourth NMOS transistor 104 are in the off state at this time. And finishing the voltage consistency processing of all the battery cores and the corresponding capacitors, wherein the processing can be finished sequentially or simultaneously.

After the completion of the coincidence process of all the cells, the first and second NMOS transistors 101 and 102 corresponding to each cell may be turned off, and the third and fourth NMOS transistors 103 and 104 corresponding to each cell may be turned on. This is equivalent to connecting all the switched capacitors in parallel, and in the process, the switched capacitor with higher voltage will automatically charge the switched capacitor with lower voltage. Thereby realizing the voltage consistency of each capacitor. After the voltages of the respective switch capacitances are consistent, the third NMOS transistor 103 and the fourth NMOS transistor 104 corresponding to each battery cell may be turned off, and the first NMOS transistor 101 and the second NMOS transistor 102 corresponding to each battery cell may be turned on, so that each battery cell and the respective switch capacitance are charged and/or discharged, and the voltages between the battery cells are balanced and consistent. In addition, the above processes may be circularly processed, so that electric energy may be automatically transferred from a cell with a higher voltage to a cell with a lower voltage, and direct transfer of electric energy between any elements may be achieved. According to the method disclosed by the invention, even in an application occasion with a large number of battery cells, a high balancing speed can be maintained.

In the present disclosure, the above-mentioned switches (transistors, NMOS transistors) are all integrated into a chip, and the switched capacitors may be connected outside the chip. This allows the formation of a lossless equalizing capacitor for energy transfer based on external capacitance, which facilitates chip integration. The balance management circuit is arranged in the chip, and external energy transfer adopts a capacitance mode to realize balance among the battery cores in the battery module, so that the balance current is large and the balance efficiency is high.

After voltage equalization is achieved between cells in the battery module, the consistency difference between cells in the battery module becomes very small. And the passive balance energy of the voltage of the battery module can be adopted.

A circuit schematic of active equalization and passive equalization according to the present disclosure is shown in fig. 3. The content of active equalization is not described in detail. An equalization resistor and a high voltage transistor (e.g., an NMOS transistor or a PMOS transistor) may be included in the passive equalization circuit. The balancing resistor 210 and the high voltage NMOS transistor 220 may form a series circuit, one end of which may be connected to the highest voltage end of the battery module and the other end of which may be connected to the lowest voltage end of the battery module. The equalizing resistor may be an adjustable equalizing resistor and may be disposed outside the chip, and the high voltage NMOS transistor 220 may be disposed outside the chip or integrated inside the chip.

Fig. 4 shows a schematic diagram of voltage equalization between battery modules. As shown in fig. 4, the battery pack may include a plurality of battery modules, for example, a battery module 1, a battery module 2, 82308230, a battery module N. A plurality of battery modules are connected in series to form a battery pack. In the process of actual use, the voltages between the battery modules may be unbalanced, and therefore, it is also necessary to balance the battery modules for safety, service life, and the like. As shown in fig. 4, each battery module includes an equalizing resistor 210 and a high voltage NMOS transistor 220. Whether the voltage among the battery modules has a balance problem is judged by detecting the highest voltage and the lowest voltage of each resistor module. In the process of voltage equalization between the battery modules, the high-voltage NMOS transistor 220 can be controlled to be turned on and off by a control signal, so that the corresponding battery modules are discharged, and electric energy is consumed by the equalizing resistor 210, thereby finally enabling each battery module to realize the effect of voltage equalization between the battery modules.

According to a further embodiment of the present disclosure, there is also provided an equalization management circuit. In the embodiment associated with fig. 2, when equalization is initiated, the cells will transfer charge to the corresponding capacitors, creating a current. Since there is no charge in the capacitor, a large current of several amperes is generated in the initial process, and the chip may be damaged.

Therefore, in order to solve the technical problem, an embodiment is further proposed in the present disclosure. As shown in fig. 5, in this embodiment, compared with the embodiment shown in fig. 2 and the like, the transistor 101 shown in fig. 2 may be replaced with a current control portion 301, and/or the transistor 102 shown in fig. 2 may be replaced with a current control portion 302. In the present disclosure, the transistor 101 shown in fig. 2 may be replaced with only the current control portion 301, or the transistor 102 shown in fig. 2 may be replaced with only the current control portion 302. Or both the current control section 301 and the current control section 302 replace the transistor 101 and the transistor 102 shown in fig. 2, respectively. In the present disclosure, a current control unit may be used to control a current flowing from the battery cell to the capacitor, and the current control unit may be a constant current unit, which may control a constant current to be formed between the battery cell and the capacitor, or may change the current according to a situation. The current control section can prevent a large current from being generated at least at the time of equalization management.

In order to realize the current control part suitable for the equalizing circuit, the utility model discloses the people can adopt following several kinds of realization modes according to reality.

Three practical circuit forms that can control the current and that can be applied to the equalization circuit are provided in fig. 6 to 8. In the embodiments of fig. 6 to 8, the current control section functions by controlling the on-resistance of the series transistor to control the current. In the embodiments of the present disclosure, the on-resistance of the transistor is changed by controlling the voltage flowing between the gate and the source of the transistor, for example, the larger the voltage, the smaller the on-resistance. Since the on-resistance of the transistor can be adjusted, the current is adjusted accordingly. In any of the embodiments of fig. 6 to 8, the circuit may be applied to the current control section 301 and/or 302.

As shown in fig. 6, the current control part may include a first PMOS transistor P1 and a second PMOS transistor P2. The first PMOS transistor and the second PMOS transistor are connected in series. The drain of the first PMOS transistor may be connected to the core terminal IN, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the drain of the second PMOS transistor is connected to the capacitor terminal OUT. The gate of the first PMOS transistor is interconnected with the gate of the second PMOS transistor. The source of the first PMOS transistor and the source of the second PMOS transistor are connected to the gate of the first NMOS transistor N1. The drain of the first NMOS transistor is connected to a power source VCC, wherein the power source VCC may be a voltage generated by the LDO shown in fig. 1. The source of the first NMOS transistor N1 is connected to one end of a resistor R, and the other end of the resistor R is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor. The other end of the resistor R may be connected to the drain of the second NMOS transistor N2, and the source of the second NMOS transistor N2 is connected to the drain of the third NMOS transistor N3. The source of the third NMOS transistor N3 is grounded. Wherein the gate of the second NMOS transistor N2 may be connected to an ENABLE signal ENABLE. The gate of the third NMOS transistor N3 may be connected to the control signal BIAS.

In operation, the enable signal turns on the second NMOS transistor and controls its turn on and off by the control signal of the third NMOS transistor, so that current will flow from the VCC terminal via N1, R, N2, N3. The current is varied by controlling the third NMOS transistor to be turned on and off. After the current changes, the voltage generated by the first NMOS transistor and the resistor changes, so that the voltage generated by the on-resistance of the first PMOS transistor and the resistor R changes, the gate-source voltage of the first PMOS transistor and the gate-source voltage of the second PMOS transistor change, the on-resistance of the first PMOS transistor and the on-resistance of the second PMOS transistor can be changed, and the flowing current can be changed. Thus, when the voltage equalization is performed, the change of the current can be controlled, thereby avoiding the generation of large current. Of course, a constant current mode, or other current values, etc. may be used in the charge transfer process.

Fig. 7 shows another embodiment of the current control section. According to this embodiment, a first PMOS transistor P1 and a second PMOS transistor P2 may be included, wherein the drain of the first PMOS transistor is connected to the core terminal IN, and the drain of the second PMOS transistor is connected to the capacitor terminal OUT. The sources of the first and second PMOS transistors P1 and P2 are interconnected. The current control part may include a control circuit, wherein the control circuit may provide a current flowing through the first NMOS transistor N1 as a reference current. In this embodiment, the first and second current mirror circuits may be current mirror circuits conventional in the art, such as gate-interconnected transistor circuits. The gate of the first NMOS transistor N1 may be connected to the gate of the transistor of the second current mirror. In this way, a desired reference current can be generated by the control circuit and fed back to the branch in which the resistor R is located by the current mirror circuit.

Thus, the voltage generated by the resistor R can be changed by adjusting the value of the current flowing through the resistor R. Since the resistor R is connected between the gate and the source of the first PMOS transistor P1, a change in the voltage of the resistor R will change the gate-source voltage of the first PMOS transistor P1, which correspondingly changes the on-resistance of the first PMOS transistor P1. Likewise, because the resistor R is connected between the gate and source of the second PMOS transistor P2, a change in the voltage of the resistor R will change the gate-source voltage of the second PMOS transistor P2, which correspondingly changes the on-resistance of the second PMOS transistor P2. Thus, the on-resistance of the first PMOS transistor P1 and the on-resistance of the second PMOS transistor P2 are changed, and the current between IN and OUT can be changed.

Fig. 8 shows a current control section according to a third embodiment of the present disclosure. In this embodiment, a protection diode D is used as a gate protection circuit, wherein a cathode of the protection diode D is connected to a source of the first NMOS transistor N1 (left side transistor) and a source of the second NMOS transistor N2 (right side transistor), and an anode of the protection diode D is connected to a gate of the first NMOS transistor N1 and a gate of the second NMOS transistor N2. The gate protection function of the first NMOS transistor N1 and the second NMOS transistor N2 is realized by the diode D.

This embodiment may include a first current mirror circuit and a second current mirror circuit, which may take the form of conventional circuits. The source of the first NMOS transistor is connected to the source of the second NMOS transistor, and the drain of the first NMOS transistor may be connected to the core terminal IN, and the drain of the second NMOS transistor is connected to the capacitor terminal OUT. The grid of the first NMOS transistor is connected with the grid of the second NMOS transistor. In addition, the transistor also comprises a third NMOS transistor N3, and the grid electrode of the third NMOS transistor is connected with the grid electrode of the first NMOS transistor and the grid electrode of the second NMOS transistor. The source electrode of the third NMOS transistor is connected with the source electrode of the first NMOS transistor and the source electrode of the second NMOS transistor. The drain electrode of the third NMOS transistor is connected with the first current mirror circuit.

And a fourth NMOS transistor N4, wherein the fourth NMOS transistor N4 is used for generating a reference current, and the generated reference current can be fed back to a branch of the third NMOS transistor between the first current mirror circuit and the second current mirror circuit, and by adjusting a current value of the reference current, an on-resistance between a gate and a source of the third NMOS transistor can be changed, so that the on-resistances of the first NMOS transistor and the second NMOS transistor can be adjusted. As above, this allows for the regulation of the current flowing through both.

Of course, the third NMOS transistor may be replaced by a resistor, in which case one end of the resistor is connected to the first current mirror and the gates of the first and second NMOS transistors, and the other end of the resistor is connected to the second current mirror and the sources of the first and second NMOS transistors. For example, as shown in fig. 9, the circuit through the resistors may be adjusted to change the gate-source voltages of the first NMOS transistor and the second NMOS transistor, thereby changing the on-resistances of the two transistors.

Further, in the present disclosure, the current control section may also be used for a sampling switch. For example, as in the inter-cell equalization circuit shown in fig. 5, the capacitance may be used as a sampling capacitance. The sampling capacitor is used for collecting the voltage of the battery cell, and in the sampling process, the charge of the battery cell can flow into the sampling capacitor by controlling the current control part/switch. Since there is also a case where the above-described large current occurs during the voltage sampling, in this case, in order to avoid the occurrence of the large current, the current control section may be used to control the current value as well.

According to the embodiment of the disclosure, compared with the prior art, the lossless equalization can be realized, and the advantages of large equalization current, high equalization efficiency, high equalization speed and the like are achieved.

In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims (14)

1. A chip with a built-in equalization management circuit, the equalization management circuit is used for equalizing the battery voltage of each battery cell of a battery module, and the chip is characterized by comprising:

the gating circuit is connected with each battery cell so as to perform gating measurement on each battery cell;

the analog-to-digital converter is connected with the gating circuit and is used for collecting the battery voltage and the battery temperature of each battery cell based on the on and off of the gating circuit;

a microcontroller connected with the analog-to-digital converter and used for processing information from the analog-to-digital converter; and

a balancing management circuit that performs inter-cell balancing of the battery module and module balancing of the battery module,

the balance management circuit between the electric cores performs voltage balance between the electric cores, the balance management circuit between the modules comprises a balance resistor and a balance switch, the balance resistor and the balance switch form a series circuit, one end of the series circuit is connected with the highest voltage of the battery module, the other end of the series circuit is connected with the lowest voltage of the battery module, and the balance switch is switched on or off to realize balance between the modules through the balance resistor.

2. The chip of claim 1, wherein the equalization resistor is an adjustable equalization resistor and is disposed outside of the chip, and the equalization switch is disposed outside or inside of the chip.

3. The chip of claim 1, wherein the inter-cell balancing management circuit comprises a first switch, a second switch, a third switch, a fourth switch, and a capacitor, the first switch and the third switch are connected in series to form a first series circuit, one end of the first series circuit is connected to the negative electrode of the corresponding cell, the other end of the first series circuit is connected to the other end of the other cell, the second switch and the fourth switch are connected in series to form a second series circuit, one end of the second series circuit is connected to the positive electrode of the corresponding cell, the other end of the second series circuit is connected to the other end of the other cell, and the capacitor is connected between a connection node of the first switch and the third switch and a connection node of the second switch and the fourth switch.

4. The chip of claim 3, wherein the first switch and the second switch are turned on to charge the respective capacitors through the respective cells, then the third switch and the fourth switch are turned on to make the voltages of the respective capacitors of all the cells uniform, and then the first switch and the second switch are turned on to make the voltages of all the cells uniform.

5. The chip of claim 3, wherein the equalization switch is a high voltage MOS transistor, and the first switch, the second switch, the third switch, and the fourth switch are MOS transistors.

6. The chip of claim 3, wherein at least one of the first switch and the second switch is replaced with a current control portion by which a value of a current flowing from the current control portion into the capacitor is adjusted.

7. The chip of claim 6, in which the current value is a constant current value or a variable current value.

8. The chip according to claim 6 or 7, wherein the current control section includes a first PMOS transistor and a second PMOS transistor, the first PMOS transistor and the second PMOS transistor constituting a series circuit having both ends connected to a cell and a capacitor, respectively, the current value being adjusted by changing on-resistances of the first PMOS transistor and the second PMOS transistor.

9. The chip of claim 8, wherein the sources of the first and second PMOS transistors are interconnected, and the drain of the first PMOS transistor is connected to the cell, and the drain of the second PMOS transistor is connected to the capacitor, further comprising a series circuit of a first NMOS transistor and a resistor, the gate of the first NMOS transistor being connected to the drains of the first and second PMOS transistors, the source of the first NMOS transistor being connected to a first end of the resistor, the second end of the resistor being connected to the gates of the first and second PMOS transistors, and wherein the on-resistance of the first and second PMOS transistors is changed by changing the current through the first NMOS transistor and the resistor to change the gate-source voltage of the first and second PMOS transistors.

10. The chip of claim 8, wherein the sources of the first and second PMOS transistors are interconnected, and the drain of the first PMOS transistor is connected to a cell, and the drain of the second PMOS transistor is connected to a capacitor, further comprising a resistor, one end of the resistor being connected to the sources of the first and second PMOS transistors, the other end of the resistor being connected to the gates of the first and second PMOS transistors, and wherein the on-resistances of the first and second PMOS transistors are changed by changing the current through the resistor to change the gate-source voltages of the first and second PMOS transistors.

11. The chip according to claim 6 or 7, wherein the current control section includes a first NMOS transistor and a second NMOS transistor, the first NMOS transistor and the second NMOS transistor constituting a series circuit having both ends connected to a battery cell and a capacitor, respectively, the current value being adjusted by changing on-resistances of the first NMOS transistor and the second NMOS transistor.

12. The chip of claim 11, wherein sources of the first and second NMOS transistors are interconnected, and a drain of the first NMOS transistor is connected to a cell, and a drain of the second NMOS transistor is connected to a capacitor, further comprising a third NMOS transistor, a gate of the third NMOS transistor is connected to drains of the first and second NMOS transistors, and a source of the third NMOS transistor is connected to sources of the first and second NMOS transistors, and wherein a gate-source voltage of the first and second NMOS transistors is changed by changing a current flowing through the third NMOS transistor, thereby changing on-resistances of the first and second NMOS transistors.

13. The chip of claim 11, wherein sources of the first and second NMOS transistors are interconnected, and a drain of the first NMOS transistor is connected to a cell, and a drain of the second NMOS transistor is connected to a capacitor, further comprising a resistor, one end of the resistor being connected to sources of the first and second NMOS transistors, the other end of the resistor being connected to gates of the first and second NMOS transistors, and wherein a gate-source voltage of the first and second NMOS transistors is changed by changing a current flowing through the resistor, thereby changing on-resistances of the first and second NMOS transistors.

14. The chip of claim 6 or 7, wherein the current control portion is capable of functioning as a sampling control portion, and the capacitance functions as a sampling capacitance, and the voltage of the corresponding cell is collected by the sampling control portion and the sampling capacitance.

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