CN217719569U - Chip on film and display device - Google Patents
Chip on film and display device Download PDFInfo
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- CN217719569U CN217719569U CN202221670898.XU CN202221670898U CN217719569U CN 217719569 U CN217719569 U CN 217719569U CN 202221670898 U CN202221670898 U CN 202221670898U CN 217719569 U CN217719569 U CN 217719569U
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Abstract
The application provides a chip on film and a display device, the chip on film at least comprises a chip on film body and a first stress buffer layer, the chip on film body is provided with a first surface and a second surface which are opposite, and the first stress buffer layer is positioned on the first surface of the chip on film body. The first stress buffer layer is provided with a plurality of first hollow patterns, so that the stress of the chip on film body can be shared, the stress of the chip on film is reduced, the peeling risk of the chip on film is reduced, and the product quality is improved.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a chip on film and a display device.
Background
With the development of display technology, curved displays are popular with users due to their appearance and display effect, and after the curved displays are assembled, the warpage of the flip-chip film caused by the bending of the panel and the printed circuit board is more serious than that of the flat displays, so that the stress of the flip-chip film is larger, the peeling risk of the flip-chip film at the binding position with the display panel or the printed circuit board is larger, and the display is abnormal.
Therefore, how to reduce the stress of the flip chip is a problem to be solved.
Disclosure of Invention
The present disclosure provides a flip chip on film and a display device, which are capable of reducing stress of the flip chip on film, thereby reducing a risk of peeling the flip chip on film.
In one aspect, the present invention provides a chip on film and a display device, the chip on film at least includes:
the chip on film body is provided with a first surface and a second surface which are opposite;
the first stress buffer layer is positioned on the first surface of the flip chip thin film body;
the first stress buffer layer is provided with a plurality of first hollow patterns.
In some embodiments, the shape of the first cutout pattern includes one of a circle, a square, and an ellipse.
In some embodiments, the plurality of first hollow patterns are uniformly distributed on the first stress buffer layer.
In some embodiments, the first stress buffer layer includes a middle region and an edge region located at a periphery of the middle region, and a density of the first hollow patterns in the edge region is greater than a density in the middle region.
In some embodiments, the material of the first stress buffer layer comprises one of polyimide, polycarbonate, polypropylene, and rubber.
In some embodiments, the first stress buffer layer has a thickness of 0.005-0.015mm.
In some embodiments, the chip on film further comprises:
the second stress buffer layer is positioned on the second surface of the flip chip thin film body;
the second stress buffer layer is provided with a plurality of second hollow patterns.
In some embodiments, the first stress buffer layer is attached to the flip-chip on film body.
In some embodiments, the first stress buffer layer is integrally fabricated with the flip-chip on film body.
In another aspect, the present application provides a display device, including at least:
in the chip on film provided in any of the above embodiments, the chip on film includes a first bonding end and a second bonding end that are disposed opposite to each other;
the display panel is bound with the first binding end;
and the printed circuit board is bound with the second binding end.
The beneficial effect of this application is: the flip chip film at least comprises a flip chip film body and a first stress buffer layer, wherein the flip chip film body is provided with a first surface and a second surface which are opposite, and the first stress buffer layer is positioned on the first surface of the flip chip film body. The first stress buffer layer is provided with a plurality of first hollow patterns, so that the stress of the chip on film body can be shared, and the stress of the chip on film is reduced, thereby reducing the peeling risk of the chip on film and improving the product quality.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a chip on film according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of a first stress buffer layer provided in an embodiment of the present application;
fig. 3 is a stress simulation cloud of the flip chip film including the first stress buffer layer in fig. 2 according to an embodiment of the present disclosure;
FIG. 4 is a stress simulation cloud of a COF not including a first stress buffer layer according to an embodiment of the present disclosure;
FIG. 5 is a schematic structural diagram of a first stress-buffer layer according to another embodiment of the present disclosure;
fig. 6 is a stress simulation cloud of the flip chip film including the first stress buffer layer in fig. 5 according to an embodiment of the present disclosure;
FIG. 7 is a schematic structural diagram of a first stress buffer layer according to yet another embodiment of the present disclosure;
FIG. 8 is a schematic structural diagram of a COF according to another embodiment of the present application;
fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the recitation of a first feature "on" or "under" a second feature may include the recitation of the first and second features being in direct contact, and may also include the recitation of the first and second features not being in direct contact, but being in contact with another feature between them. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip on film according to an embodiment of the present disclosure. The flip chip 100 can be applied to various displays or Display devices, such as a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED), a Micro-LED (Micro-LED), and the like.
The COF 100 at least comprises a COF body 10 and a first stress buffer layer 11, wherein the COF body 10 has a first surface 101 and a second surface 102 which are opposite to each other, and the first stress buffer layer 11 is located on the first surface 101 of the COF body 10. The first stress buffer layer 11 has a plurality of first hollow patterns (not shown in fig. 1), which will be described below. The shape of the first hollow pattern may include one of a circle, a square and an ellipse. The shape of the first hollow pattern is not limited in the embodiment of the application.
In some embodiments, the material of the first stress buffer layer 11 includes one of Polyimide (PI), polycarbonate (PC), polypropylene (PP), and rubber.
In some embodiments, the first stress buffer layer 11 has a thickness of 0.005-0.015mm. Preferably, the thickness of the first stress buffer layer 11 is 0.01mm. The thickness of the first stress buffer layer 11 may be determined according to practical circumstances.
In some embodiments, the first stress buffer layer 11 may be attached to the first surface 101 of the flip-chip on film body 10. In other embodiments, the first stress buffer layer 11 may be integrally formed with the main body 10.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a first stress buffer layer according to an embodiment of the present disclosure.
The first stress buffer layer 11a may have two rows of first hollow patterns 111a, and the first hollow patterns 111a are square, for example, rectangular. The plurality of first hollow patterns 111a are uniformly distributed on the first stress buffer layer 11a to share the stress of the flip chip film body.
Referring to fig. 3, fig. 3 is a stress simulation cloud diagram of a flip chip film including the first stress buffer layer in fig. 2 according to an embodiment of the present disclosure. Referring to fig. 4, fig. 4 is a stress simulation cloud diagram of the flip chip without the first stress buffer layer according to the embodiment of the disclosure.
In this embodiment, a curved display with 27 inches and a curvature of 1500mm is taken as an example, as shown in fig. 3, the stress simulation cloud chart shows that the maximum stress of the flip chip film including the first stress buffer layer 11a in fig. 2 is 104.9MPa. As shown in fig. 4, the stress simulation cloud chart shows that the maximum stress of the flip chip film without the first stress buffer layer is 132.7Mpa. Therefore, compared with the flip chip film without the first stress buffer layer, the flip chip film with the first stress buffer layer 11a has the advantages that the maximum stress is reduced by 26.5%, the stripping risk is smaller, and the product quality is higher.
Because the maximum stress of the flip chip film has the greatest influence on the flip chip film, the peeling risk is positively correlated with the maximum stress at the position where the flip chip film is bound with the display panel or the printed circuit board, and the peeling risk of the flip chip film can be reduced by reducing the maximum stress.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a first stress buffer layer according to another embodiment of the present disclosure.
The first stress buffer layer 11b may have two rows of first hollow patterns 111b thereon, and the first hollow patterns 111b are elliptical. The plurality of first hollow patterns 111b are uniformly distributed on the first stress buffer layer 11b to share the stress of the flip chip film body.
In some embodiments, the first hollow pattern 111b may also be circular.
In some embodiments, the first stress buffering layer 11b has a thickness of 0.005 to 0.015mm.
Referring to fig. 6, fig. 6 is a stress simulation cloud of a chip on film including the first stress buffer layer in fig. 5 according to an embodiment of the present disclosure.
In this embodiment, taking a curved display with 27 inches and a curvature of 1500mm as an example, the stress simulation cloud chart shows that the maximum stress of the flip chip film including the first stress buffer layer 11b in fig. 5 is 108.5MP. As shown in fig. 4, the stress simulation cloud chart shows that the maximum stress of the flip chip film without the first stress buffer layer is 132.7Mpa. Therefore, compared with the flip chip film without the first stress buffer layer, the flip chip film with the first stress buffer layer 11b has the advantages that the maximum stress is reduced by 22.3%, the stripping risk is lower, and the product quality is higher.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a first stress buffer layer according to another embodiment of the present disclosure.
The first stress buffer layer 11c includes a middle region a and an edge region B located at the periphery of the middle region a, and the density of the first hollow patterns 111c in the edge region B is greater than that in the middle region a. Since the stress at the edge of the general COF body is larger, more first hollow patterns 111c are disposed in the edge region B of the first stress buffer layer 11c, and less first hollow patterns 111c are disposed in the middle region A, so as to improve the stress at the edge of the COF body or the COF body. The edge position of the common flip chip is a binding area, so that the stress of the edge position is reduced, and the stripping risk after the flip chip is bound can be reduced.
In this embodiment, the first hollow pattern 111c is square.
In some embodiments, the first stress buffer layer 11c has a thickness of 0.005-0.015mm.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a chip on film according to another embodiment of the present application. For ease of understanding and brief description, the same reference numerals are used in this embodiment for the same structures as in the embodiment of fig. 1.
The COF 200 at least comprises a COF body 10, a first stress buffer layer 11 and a second stress buffer layer 20. The COF body 10 has a first surface 101 and a second surface 102 opposite to each other, the first stress buffer layer 11 is located on the first surface 101 of the COF body 10, and the second stress buffer layer 20 is located on the second surface 102 of the COF body 10. The first stress buffer layer 11 has a plurality of first hollow patterns, and the second stress buffer layer 20 has a plurality of second hollow patterns. The shapes of the first hollow pattern and the second hollow pattern can comprise one of a circle, a square and an ellipse. The shape of the first hollow pattern and the second hollow pattern is not limited in the embodiment of the application.
In some embodiments, the material of the second stress buffer layer 20 includes one of Polyimide (PI), polycarbonate (PC), polypropylene (PP), and rubber.
In some embodiments, the plurality of first hollow patterns are uniformly distributed on the first stress buffer layer 11. The plurality of second hollow patterns are uniformly distributed on the second stress buffer layer 20.
In some embodiments, the second stress buffer layer 20 includes a middle region and an edge region located at the periphery of the middle region, and the density of the second hollow pattern in the edge region is greater than that in the middle region.
In some embodiments, the second stress buffer layer 20 has a thickness of 0.005-0.015mm. Preferably, the thickness of the second stress buffer layer 20 is 0.01mm.
In some embodiments, the first stress buffer layer 11 and the second stress buffer layer 20 may be respectively attached to the first surface 101 and the second surface 102 of the flip-chip body 10. In other embodiments, the first stress buffer layer 11 and the second stress buffer layer 20 may be integrally formed with the flip-chip body 10.
The embodiment of the application provides a chip on film, which at least comprises a chip on film body and a first stress buffer layer, wherein the chip on film body is provided with a first surface and a second surface which are opposite, and the first stress buffer layer is positioned on the first surface of the chip on film body. The first stress buffer layer is provided with a plurality of first hollow patterns, so that the stress of the chip on film body can be shared, and the stress of the chip on film is reduced, thereby reducing the peeling risk or probability of the chip on film, improving the product quality and improving the product stability.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
The display device 300 at least comprises a chip on film 30, a display panel 31 and a printed circuit board 32, wherein the chip on film 30 can be a chip on film in any of the above embodiments, and thus the display device has the same beneficial effects as the chip on film in any of the above embodiments, and the details are not repeated herein.
The COF 30 at least comprises a COF body and a first stress buffer layer, wherein the COF body is provided with a first surface and a second surface which are opposite, and the first stress buffer layer is positioned on the first surface of the COF body. The first stress buffer layer is provided with a plurality of first hollow patterns.
The chip on film 30 includes a first bonding end 30a and a second bonding end 30b which are oppositely disposed, the display panel 31 is bonded to the first bonding end 30a, and the printed circuit board 32 is bonded to the second bonding end 30 b.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A chip on film, comprising:
the chip on film body is provided with a first surface and a second surface which are opposite;
the first stress buffer layer is positioned on the first surface of the flip chip thin film body;
the first stress buffer layer is provided with a plurality of first hollow patterns.
2. The chip on film of claim 1, wherein the first cutout pattern has a shape selected from the group consisting of a circle, a square, and an ellipse.
3. The chip on film of claim 1, wherein the plurality of first hollow patterns are uniformly distributed on the first stress buffer layer.
4. The chip on film of claim 1, wherein the first stress buffer layer comprises a middle region and an edge region located at the periphery of the middle region, and the density of the first cutout pattern in the edge region is greater than that in the middle region.
5. The chip on film of claim 1, wherein the material of the first stress buffer layer comprises one of polyimide, polycarbonate, polypropylene and rubber.
6. The chip on film of claim 1, wherein the first stress buffer layer has a thickness of 0.005-0.015mm.
7. The chip on film of claim 1, further comprising:
the second stress buffer layer is positioned on the second surface of the flip chip thin film body;
the second stress buffer layer is provided with a plurality of second hollow patterns.
8. The COF of claim 1, wherein the first stress buffer layer is attached to the COF body.
9. The COF of claim 1, wherein the first stress buffer layer is integrally formed with the COF body.
10. A display device, characterized in that the display device comprises at least:
the chip on film of any one of claims 1-9, comprising first and second oppositely disposed bonding ends;
the display panel is bound with the first binding end;
and the printed circuit board is bound with the second binding end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221670898.XU CN217719569U (en) | 2022-06-28 | 2022-06-28 | Chip on film and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221670898.XU CN217719569U (en) | 2022-06-28 | 2022-06-28 | Chip on film and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217719569U true CN217719569U (en) | 2022-11-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202221670898.XU Active CN217719569U (en) | 2022-06-28 | 2022-06-28 | Chip on film and display device |
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| CN (1) | CN217719569U (en) |
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- 2022-06-28 CN CN202221670898.XU patent/CN217719569U/en active Active
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